JPH01165126A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01165126A JPH01165126A JP62322917A JP32291787A JPH01165126A JP H01165126 A JPH01165126 A JP H01165126A JP 62322917 A JP62322917 A JP 62322917A JP 32291787 A JP32291787 A JP 32291787A JP H01165126 A JPH01165126 A JP H01165126A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- cvd
- etching
- opening
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000010410 layer Substances 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract description 3
- 239000002356 single layer Substances 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract 3
- 238000000059 patterning Methods 0.000 abstract 1
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法、特にリフトオフ法
によるパターン形成の方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a pattern using a lift-off method.
電界効果トランジスタのダート電極のパターン形成など
には、リフトオフ法によって行われるものがある。The pattern formation of dirt electrodes of field effect transistors is sometimes performed by a lift-off method.
従来、上記のような場合などのリフトオフ法によるパタ
ーン形成は、二重レジスト構造あるいは金属又は酸化物
をはさむ三重レジスト構造を用いて行われていた。Conventionally, pattern formation by the lift-off method in the above cases has been performed using a double resist structure or a triple resist structure sandwiching metal or oxide.
第２図、第３図にそれぞれ二重レジｆｉト構造、三重レ
ジスト構造を用いる従来のりフトオフ法によるパターン
形成の方法の例を示す。FIGS. 2 and 3 show examples of pattern forming methods using a conventional lift-off method using a double resist structure and a triple resist structure, respectively.
図において１は第１層レジスト、２は第２層レジスト、
３は酸化膜、４はＧａＡｇ動作層、５はダート電極メタ
ルである。In the figure, 1 is the first layer resist, 2 is the second layer resist,
3 is an oxide film, 4 is a GaAg active layer, and 5 is a dirt electrode metal.
二重レジスト構造あるいは三重レジスト構造によってそ
れぞれ第２図（Ｃ）、第３図（ｅ）に示すような側面が
段差をもったあるいは逆向きのテーパー状部分をもつ開
口をつくシ、蒸着メタルをリフトオフさせてｒ−ト電極
パターン５を形成するものである。By using a double resist structure or a triple resist structure, an opening with a stepped side surface or a tapered part in the opposite direction as shown in FIGS. The r-to-electrode pattern 5 is formed by lift-off.
なお、図はチャンネル領域をリセス構造にした例を示す
。Note that the figure shows an example in which the channel region has a recessed structure.
従来の二重レジスト構造あるいは三重レジスト構造を用
いる方法は、多大の工数を要する上に、高温にするとレ
ジストの形状がずれるために、パターン材料に高融点金
属が使用できないという問題があった。Conventional methods using double resist structures or triple resist structures require a large number of man-hours and have the problem that high melting point metals cannot be used as pattern materials because the shape of the resist shifts when heated to high temperatures.
この発明は上記問題を解消するためになされたもので、
工数が従来の方法に比べ大幅に減るとともに、パターン
材料として高融点金属を使用できるリフトオフ法を提供
することを目的とする。This invention was made to solve the above problem.
The purpose of the present invention is to provide a lift-off method that requires significantly less man-hours than conventional methods and allows the use of high-melting point metals as pattern materials.
この発明の製造方法は、リフトオフ法によるパターン形
成を、ＣＶＤ法で温度を変化させながら堆積させた窒化
膜の選択エツチングによって形成される厚み方向のエツ
チングレート差により側面が逆向きテーパー状となる開
口を利用して行うものである。The manufacturing method of the present invention combines pattern formation by a lift-off method with selective etching of a nitride film deposited by a CVD method while changing the temperature.The opening has an oppositely tapered side surface due to the difference in etching rate in the thickness direction. This is done by using.
上記方法は、窒化膜の単層のみを用いるので工数が減る
とともに、・平ターン材料に高融点金属を使用できる。Since the above method uses only a single layer of nitride film, the number of steps is reduced, and a high melting point metal can be used as the flat turn material.
〔発明の実施例〕
第１図にこの発明に係るパターン形成の方法の一例を示
す。図は増幅率の大きな大出力のＧａＡｓショットキゲ
ート電界効果トランジスタ（ＧａＡｓＭＥＳ ＦＥＴ
）のデートパターン形成の例である。[Embodiments of the Invention] FIG. 1 shows an example of a pattern forming method according to the present invention. The figure shows a large output GaAs Schottky gate field effect transistor (GaAsMES FET) with a large amplification factor.
) is an example of the formation of a dating pattern.
図において１１は半絶縁性基板、１２はＧａＡｓ動作層
、１３はソース電極、１４はドレイン電極、１５ｉＰ−
ＣＶＤ窒化膜、１６１１’ｉｔ／シフ１．ト、１７はダ
ート金属。In the figure, 11 is a semi-insulating substrate, 12 is a GaAs active layer, 13 is a source electrode, 14 is a drain electrode, 15iP-
CVD nitride film, 1611'it/Schiff 1. 17 is dirt metal.
半絶縁性基板１１上に形成したＧａＡｓ動作層１２にソ
ース電極１３、ドレイン電極１４を形成し〔図（ａ）〕
、ＣＶＤ装置でデポ温度を低温から高温に変えながら表
面にＰ −ＣＶＤ窒化膜１５を形成する〔図（ｂ）〕。A source electrode 13 and a drain electrode 14 are formed on a GaAs active layer 12 formed on a semi-insulating substrate 11 [Figure (a)].
A P-CVD nitride film 15 is formed on the surface while changing the deposition temperature from a low temperature to a high temperature using a CVD apparatus [Figure (b)].
次に、Ｐ −ＣＶＤ窒化膜１５表面にレジスト１６を塗
布し、レジスト１６のパターニングを行ない、開口を設
け〔図（Ｃ）〕、Ｐ −ＣＶＤ窒化膜１５の選択エツチ
ングを行う。この場合、デポ温度の低い窒化膜１５のエ
ツチングレートはデポ温度の高い窒化膜１５のエツチン
グレートより太きいために、エツチング開口部の側面が
逆向きチー・や−状と、２る〔図（ｄ） ） ＠
レジスト１６を除去し〔図（、） ） 、リセスエッチ
ングを行い〔図（ｆ）〕、ダート金属１７を蒸着して窒
化膜１５の開口周端でリフトオフさせ〔図（ｇ）〕、窒
化膜エツチング液で窒化膜１５及び窒化膜１５上に蒸着
したダート金属１７を除去する〔図（ｈ）〕。Next, a resist 16 is applied to the surface of the P-CVD nitride film 15, the resist 16 is patterned, an opening is formed (FIG. (C)), and the P-CVD nitride film 15 is selectively etched. In this case, since the etching rate of the nitride film 15 with a low deposition temperature is greater than the etching rate of the nitride film 15 with a high deposition temperature, the side surfaces of the etching openings are in an inverted chi-shaped shape (see Fig. 2). d) ) @Remove the resist 16 [Figures (, )), perform recess etching [Figure (f)], deposit dirt metal 17 and lift off at the peripheral edge of the opening of the nitride film 15 [Figure (g)] Then, the nitride film 15 and the dirt metal 17 deposited on the nitride film 15 are removed using a nitride film etching solution [Figure (h)].
この後の工程は従来と同じである。The subsequent steps are the same as before.
以上、幅広いリセス構造を得るのに、単純な工程で済み
、また、ダート金属１７に高融点金属を使用してもパタ
ーンくずれが起こらないという利点がある。As described above, there is an advantage that a simple process is required to obtain a wide recess structure, and pattern deterioration does not occur even if a high melting point metal is used for the dart metal 17.
以上説明したように、Ｐ −ＣＶＤ窒化膜単層のエツチ
ング開口でリフトオンさせることができるので、工程が
簡単になり、工数が減るとともに、パターン材料に高融
点金属を使用できるという効果がある。As explained above, since lift-on can be performed using the etched opening in the single layer P-CVD nitride film, the process is simplified, the number of man-hours is reduced, and a high melting point metal can be used as the pattern material.
第１図はこの発明に係るパターン形成の方法の一例を示
す説明図、第２図、第３図はそれぞれ二重レジスト構造
、三重レジスト構造を用いる従来のリフトオフ法による
パターン形成の方法の例を示す説明図である。
１１・・・半絶縁性基板、１２・・・ＧａＡｓ動作層、
１３・・・ソース電極、１４・・・ドレイン電極、１５
・・・Ｐ−ＣＶＤ 窒化膜、１６・・・レジスト、１７
・・・ダート金属なお図中同一符号は同一または相当す
る部分を示す。
特許出願人 新日本無線株式会社
Φ −一一一FIG. 1 is an explanatory diagram showing an example of the pattern forming method according to the present invention, and FIGS. 2 and 3 show examples of the pattern forming method by the conventional lift-off method using a double resist structure and a triple resist structure, respectively. FIG. 11... Semi-insulating substrate, 12... GaAs operating layer,
13... Source electrode, 14... Drain electrode, 15
...P-CVD nitride film, 16...Resist, 17
...Dart Metal The same reference numerals in the drawings indicate the same or corresponding parts. Patent applicant: New Japan Radio Co., Ltd. Φ-111
Claims (1)
体装置の製造方法において、リフトオフ法によるパター
ン形成を、ＣＶＤ法で温度を変化させながら堆積させた
窒化膜の選択エッチングによって形成される厚み方向の
エッチングレート差により側面が逆向きテーパー状とな
る開口を利用して行うことを特徴とする半導体装置の製
造方法。In a semiconductor device manufacturing method in which part of the pattern is formed by a lift-off method, the difference in etching rate in the thickness direction is formed by selectively etching a nitride film deposited by a CVD method while changing the temperature. 1. A method for manufacturing a semiconductor device, characterized in that the manufacturing method is performed using an opening whose side surface is tapered in the opposite direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62322917A JPH01165126A (en) | 1987-12-22 | 1987-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62322917A JPH01165126A (en) | 1987-12-22 | 1987-12-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01165126A true JPH01165126A (en) | 1989-06-29 |
Family
ID=18149069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62322917A Pending JPH01165126A (en) | 1987-12-22 | 1987-12-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01165126A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2157478A2 (en) | 2008-08-22 | 2010-02-24 | Fujifilm Corporation | Method of producing lithographic printing plate |
| EP2166410A2 (en) | 2008-09-22 | 2010-03-24 | Fujifilm Corporation | Method of preparing lithographic printing plate and lithographic printing plate precursor |
| EP2339405A1 (en) | 2009-12-25 | 2011-06-29 | Fujifilm Corporation | Method of preparing lithographic printing plate |
-
1987
- 1987-12-22 JP JP62322917A patent/JPH01165126A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2157478A2 (en) | 2008-08-22 | 2010-02-24 | Fujifilm Corporation | Method of producing lithographic printing plate |
| EP2166410A2 (en) | 2008-09-22 | 2010-03-24 | Fujifilm Corporation | Method of preparing lithographic printing plate and lithographic printing plate precursor |
| EP2339405A1 (en) | 2009-12-25 | 2011-06-29 | Fujifilm Corporation | Method of preparing lithographic printing plate |
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