JPH01132167A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which can suppress an effect of a parasitic npn transistor, whose effective epitaxial thickness is thick and whose breakdown strength is high by a method wherein a high-concentration impurity diffusion region of a second conductivity type is formed in a self-aligned manner with reference to a high-concentration impurity diffusion layer of a first conductivity type and its diffusion depth is made shallower than that of a low-concentration impurity diffusion region of the second conductivity type. CONSTITUTION:The following are formed: a low-concentration epitaxial layer 2 of a first conductivity type formed on a high-concentration substrate 1 of the first conductivity type; a gate oxide film 11 deposited selectively on the layer; a gate electrode layer 12. In addition, the following are formed: a low-concentration impurity diffusion layer 14 of a second conductivity type which has been extended up to a region covered with the gate electrode layer 12 and which has been diffused into the epitaxial layer 2; a high-concentration impurity diffusion layer 15 of the first conductivity type which is situated inside the diffusion layer 14 and which has been diffused into a surface region of the epitaxial layer 2 not covered with the gate electrode layer 12 by using a prescribed pattern; a high-concentration impurity diffusion layer 16 of the second conductivity type which is situated inside the diffusion layer 14, which is overlapped with the high-concentration impurity diffusion layer 15 of the first conductivity type in a self-aligned manner and which has been formed also in a surface region where a high-concentration impurity of the first conductivity type has not been diffused by using said pattern.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a high voltage power MO3F
ET) Concerning the structure of transistors.

[Conventional technology] MOS (Metal Oxide Sem1co
field effect transistor (hereinafter referred to as MOS)
FE↑) has excellent characteristics such as high-speed operation and large power gain, and is widely used as a power transistor. Figure 3 shows the conventional power MOS
A cross-sectional view of the FET is shown, and the structure thereof will be explained below using the figure.

In the power MO8FET, an n- epitaxial layer 2 is formed on an n+ substrate 1 by epitaxial growth. Then, a low concentration p-diffusion layer 3 is formed on the surface of the n-evitaxial layer 2, and the diffusion 6J of this p-diffusion layer 3 is
! A high concentration n+ source layer is formed in the i region. Further, in the lower region of the n+ source layer 4, a heavily doped p+ diffusion layer 5 is formed by being deeply diffused. Furthermore, this n-
A gate oxide film 6 is deposited on the epitaxial layer 2, and a portion of the gate oxide film 6 is formed to cover the p- diffusion layer 3. Furthermore, a polysilicon layer 7 serving as a gate electrode is deposited on this, and this gate electrode is covered with an oxide film 8 for insulation.

Then, on the n+ source layer 4, an All source electrode 9 is deposited.

In such a structure, the n-substrate 1 and the n-epitaxial layer 2 constitute the drain of the MOS FET;
+source 4 constitutes a source, and gate electrode 7 constitutes a gate.

Next, the operation of this device will be explained. When a voltage equal to or higher than the threshold voltage VVH is applied to the gate electrode 7, an n channel of an n-type inversion layer is formed at the interface between the p- region 3 sandwiched between the source 4 and the drain 2 and the gate oxide film 6. Then, electrons flow from the n+ source 4 through the channel to the drain 2.1, and this transistor is activated (ON). Then, the voltage applied to the gate electrode 7 is the threshold voltage vTH
This transistor is cut off (OFF) when
do. When a gate voltage equal to or lower than the threshold voltage vTH is applied in the OFF state, a voltage is applied to the junction surface between the p − diffusion layer 3 and the p + diffusion layer 5 and the low epitaxial layer 2 . At this time, the breakdown voltage of this transistor is determined by the impurity concentration of the epitaxial layer 2 and the distance between the p+ diffusion layer 5 and the n+ substrate 1 (this is called the effective epitaxial thickness). That is, qualitatively speaking, it can be said that the lower the impurity concentration of the epitaxial layer 2 and the thicker the effective epitaxial thickness, the higher the breakdown voltage of this transistor. In addition, the current that flows when this transistor is ON increases as the channel width (w: width in the direction perpendicular to the paper surface of FIG. 3) of the channel increases, so generally, the transistor shown in FIG. A large number of these are arranged as one unit so that a large current flows through them. Therefore, by reducing the size of this one unit,
The larger the number of units per unit area, the better the characteristics of a high-voltage power MOS transistor.

[Problems to be Solved by the Invention] However, when an inductance load is connected to this transistor, the back electromotive force generated at turn-off causes the drain 1.2 to become the emitter, the p-diffusion layer 3 to be the base, and the n-diffusion layer 3 to be the base.
A parasitic npn transistor whose collector is +source 4 may operate. In order to suppress such effects, a high concentration of p+ is added inside the p- diffusion layer 3 that serves as the base.
A diffusion layer 5 is provided to reduce the electron passage rate within the base. Therefore, this p+ diffusion layer 5 is n
It is desirable that the + source 4 be formed so as to cover the surface area on the epitaxial layer 2 side other than the surface area where the channel is formed. However, in the conventional device, since multiple photolithography processes are used, the p+ diffusion layer 5 is formed to completely cover the lower surface of the n+ source 4 due to misalignment of the mask during the process of forming the diffusion layer. I can't. Therefore, the operation of the parasitic npn) transistor could not be completely suppressed. Moreover, the conventional p+ diffusion layer 5
Since the diffusion depth is deep, the effective epitaxial thickness becomes thinner, which is inconvenient for increasing the breakdown voltage. On the other hand, if a desired breakdown voltage is to be ensured, it is necessary to form the epitaxial layer 2 thickly, which has the drawback of increasing the ON resistance of this transistor.

Therefore, an object of the present invention is to provide a high breakdown voltage semiconductor device that can suppress the effect of the parasitic npn transistor and has a large effective epitaxial thickness.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a low concentration epitaxial layer of a first conductivity type formed on a substrate of a high concentration first conductivity type, and an epitaxial layer of a first conductivity type formed on the epitaxial layer of the first conductivity type. A selectively deposited gate oxide film and a gate electrode deposited on the gate oxide film. and a low concentration second conductivity type impurity diffusion layer extending into the first conductivity type epitaxial layer until reaching a region covered by the gate electrode layer; a high concentration first conductivity type impurity diffusion layer diffused in a predetermined pattern in a surface region of the first conductivity type epitaxial layer located within the layer and not covered with the gate electrode layer;
is located within the conductivity type impurity diffusion layer and is formed to overlap with the high concentration first conductivity type impurity diffusion layer in a self-aligned manner, and the high concentration first conductivity type impurity is not diffused by the pattern. A second conductivity type impurity diffusion layer of high concentration is also formed in the surface region.

The meaning of "self-consistent" as used in this book is
A state in which a plurality of impurity diffusion layers are formed using the same mask pattern is shown. That is, in the above expression, the first
This means that the conductivity type impurity diffusion layer and the high concentration second conductivity type impurity diffusion layer are "self-aligned", that is, they are formed by diffusion using the same mask pattern.

[Function] The high-breakdown-voltage power MO5FET of the semiconductor device according to the present invention has a high concentration second conductivity type impurity diffusion region for suppressing the effect of a parasitic transistor in a self-aligned manner with a high concentration first conductivity type impurity diffusion layer. The diffusion depth is shallower than that of a low concentration second conductivity type impurity diffusion region for forming a channel. This not only allows the effective epitaxial thickness to be sufficiently thick and optimizes the epitaxial thickness for the required withstand voltage, but also reduces the area of one unit of the device and minimizes the ON resistance of this transistor. In addition, to prevent the parasitic transistor effect, it is possible to replace the highly doped second conductivity type impurity region with the highly doped first conductivity type impurity region.
Since it is formed in a self-aligned manner with the conductive type impurity diffusion layer, its suppressing effect can be sufficiently exhibited.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

Figures 2A to 2G illustrate the power MO3 according to the present invention.
FIG. 3 is a cross-sectional view showing the FET according to its manufacturing process.

First, as shown in FIG. 2A, an epitaxial layer 2 having an n-type impurity concentration is formed on an n+ substrate 1 by epitaxial growth to a thickness corresponding to a required breakdown voltage. next,
After the surface of the epitaxial layer 2 is oxidized to about 500 to 100 OA and a nitride film is deposited by the CVD method, areas other than the active region are etched and oxidized by so-called selective oxidation to form a field oxide film 10. Furthermore, the nitride film on the active region is removed and the oxide film is thinned to <1000~1500A.
After removing the oxide film on the base active region, a gate oxide film 11 of about 500 to 120 OA is formed again.

Next, as shown in FIG. 2B, a polysilicon layer 12 that will become a gate is deposited at a thickness of about 2,500 to 5,000 Å using the CVD method, and highly concentrated phosphorus is diffused into this polysilicon layer 12, and then an oxide film 13 is deposited using the CVD method. A thickness of about 2 μm is deposited.

Then, as shown in FIG. 2C, a pattern having openings is formed in the oxide film 13 and the polysilicon layer 12 by patterning using photolithography and etching techniques.

Furthermore, as shown in FIG. 2D, B+ (boron) is added to the epitaxial layer 2 by I
Ion implantation is performed at about m-2, 50 keV, and then heat treatment is performed to diffuse the p-gate diffusion layer 14. The diffusion depth is 2-5 μm, which corresponds to the channel length.

Next, as shown in FIG. 2E, after etching the regions of the gate oxide film 11 corresponding to the openings of the pattern, As
+ (arsenic) lXl0" ~ 5X10" cm-2,
Ion implantation is performed at 50keVi 7 degrees.

Thereafter, as shown in FIG. 2F, after annealing at approximately 900 to 1000°C (this step may be omitted), the gate oxide film 11, polysilicon layer 12, and oxide film sandwiched between the openings are removed. Of the mesa portion 13 consisting of three layers, the uppermost oxide film 13 is removed by photolithography. Next, B
+200 to 400keV, 12X10” to 5X10
'' Ion implantation is carried out at approximately cm-2.At this time, the portion where the three layers of CVD oxide film 13, polysilicon layer 12, and gate oxide film 11 are deposited on the Evitacal layer 2 is made so that this B+ does not penetrate. In addition, for the portion where the two layers of polysilicon layer 12 and gate oxide film 11 are deposited, sufficient implantation energy is selected so that this B+ can penetrate and be implanted into the epitaxial layer 2.Next, 9
Heat treatment is performed at about 00 to 1000℃, and the n+ source 1
5 and p+ region 16 are formed.

Furthermore, as shown in Figure 2G, p
After removing the polysilicon layer 12 and gate oxide film 11 deposited on the + region 16, an oxide film (which may contain phosphorus) is deposited by CVD, and then the n+ source 15 is deposited again by photolithography. A contact hole 17 is formed in the exposed region.

Finally, as shown in FIG. 1, AfL or the like is deposited to form a wiring layer 18. After this, a surface protective film and the like are formed to complete the manufacturing process.

In the power MOSFET manufactured by such a method, the p+ region 16 is in contact with the lower part of the n+ source 15 inside the p- region 14, and extends over a region between the n+ sources 15 reaching the interface in contact with the pole 18. This p+ region 16 is diffused with a high concentration of p-type impurity and functions to keep the p- region 14 at the same potential.Furthermore, it is self-aligned with the n+ source 15, and has an n+ Since it is formed to cover the entire lower part of the source 15, n+
The effect of reducing the current amplification factor (br E ) of the parasitic npn transistor having the source 15 as the collector, the p-region 14 as the base, and the drain 2.1 as the emitter can be maximized. Furthermore, since p+ region 16 is formed inside p- region 14, the effective epitaxial thickness does not become thinner due to formation of p+ region 16.

Therefore, the epitaxial layer 2 can be formed with the minimum necessary thickness. Furthermore, since the n+ source 15, the p- region 14, and the p-medium region 16 are each formed in a self-aligned manner, the size of this unit can also be minimized. Due to the above two effects, high voltage power MO5F
The ON resistance of ET can be minimized.

Although the above embodiments have been described using p type as the first conductivity type and p type as the second conductivity type, the opposite case may be used.

[Effects of the Invention] As described above, according to the present invention, the low concentration second conductivity type diffusion region, the high concentration first conductivity type diffusion layer, and the high concentration second conductivity type diffusion layer are self-aligned. A high-concentration second-conductivity type diffusion layer is formed inside a low-concentration second-conductivity type diffusion region, so it is a high-voltage power MOS with a high parasitic element suppression effect and excellent operating characteristics. FET is obtained.

[Brief explanation of the drawing]

Figure 1 shows a high breakdown voltage power MO3F according to an embodiment of the present invention.
It is a sectional view showing ET. Figure 2A, Figure 2B, Figure 2C
2D, 2E, 2F, and 2G are cross-sectional views showing the manufacturing method thereof. FIG. 3 is a cross-sectional view of a conventional power MO8FET. In the figure, 1 is an n+ substrate, 2 is an n- epitaxial layer, 10 is a field oxide film, 11 is a gate oxide film, 12 is a
13 is a polysilicon layer, 13 is an oxide film, 14 is a gate region, 15 is an n+ source, and 16 is a p+ region. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A low concentration first conductivity type substrate formed on a high concentration first conductivity type substrate.
A semiconductor device comprising a conductivity type epitaxial layer, a gate oxide film selectively deposited on the first conductivity type epitaxial layer, and a gate electrode layer deposited on the gate oxide film, the semiconductor device comprising: a conductivity type epitaxial layer; extends until it reaches the covered area,
a low concentration second conductivity type impurity diffusion layer diffused into the first conductivity type epitaxial layer; and a second conductivity type impurity diffusion layer located within the low concentration second conductivity type impurity diffusion layer and not covered with the gate electrode layer. In the surface region of the first conductivity type epitaxial layer,
a highly concentrated first conductivity type impurity diffusion layer diffused in a predetermined pattern; and a highly concentrated first conductivity type impurity diffusion layer located within the low concentration second conductivity type impurity diffusion layer and self-aligned with the high concentration first conductivity type impurity diffusion layer. a high concentration second conductivity type impurity diffusion layer formed so as to overlap with the second conductivity type impurity layer and also formed in a surface region where the high concentration first conductivity type impurity is not diffused by the pattern; Features: Semiconductor device.