JPH01129371A - Raster scan display device and graphic data transfer - Google Patents

Abstract

PURPOSE: To easily utilize a high-speed pipeline by reading pixel data from a frame butter means and storing the pixel data in an OFF display memory means corresponding to a frame buffer address decided by a vector. CONSTITUTION: When a present stage is not prepared to receive data, a first in first out(FIFO) functions as the FIFO of a depth 1 in the input of respective pipe stages for storing the data sent from an upstream stage. A register clocked by pipeline clocks is added to the respective stages, and before present hold signals sent from a downstream stage are sent to the upstream stage, the signals are latched. Since a processing for latching the data and transferring the hold signals are continued in the pipeline, during a next clock cycle period, by the hold signals of a certain stage, the next upstream stage generates the different hold signals. Thus, constitution is easily extended without being limited by the number of pipe stages.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to raster scan display devices and methods for transferring graphical data, and more particularly to bus techniques and communication methods for interfacing an image processor to a frame buffer.

BACKGROUND OF THE INVENTION As the price of semiconductor memory decreases, raster-scanned frame buffer displays are becoming increasingly popular. The image to be displayed is represented in a mass memory that digitally represents each pixel on the screen, ie the brightness and/or color of the pixel. Frame buffer memory includes the hardware that generates the video signals to refresh the display and the memory that allows the host computer or display processor to modify the frame buffer memory to change the displayed image.
Installed with boat. An overview of this field was published in 1980.
It is described in the ``Raster Graphics Handbook'' published by Conrac Division, Conrac Corporation, Covina, California, USA.

Interactive graphics applications need to quickly change displayed images, which requires rapid changes to frame buffer memory. While the speed of the host processor and display processor is clearly important for high performance, memory system performance such as update bandwidth, ie, the speed at which each pixel is accessed by the host processor or data processor, is also important. be.

Some type of bus separates many graphics so that the image drawing engine is separated from the frame buffer. In low-performance systems where the drawing engine is a general purpose microprocessor and the frame buffer is dual boat memory, this bus may be the system bus. In high performance systems such as engineer workstations where the drawing engine is a special purpose image processor, this bus may be a high speed dedicated bus between the image processor and the frame buffer. In either case, to draw a vector in any direction, it is necessary to send an address and data to the bus for every pixel to be written. This requires either enough bus signal lines to send address and data simultaneously, or, in the case of a multiplexed address/data bus, to write all pixels in the address cycle followed by the data cycle. It means that there must be.

In traditional raster scanning devices, two-dimensional blocks (in color systems, three-dimensional blocks of data) are stored in a frame buffer.
dimension) to represent the image to be displayed. Each data element defines a pixel.

Note that pixel data consists of an address that defines the two-dimensional coordinates of the pixel, and a value that is represented by a single binary bit in a monochrome system or by many bits in a color system. Pixel data is generated and transferred one pixel at a time, first the address and then the pixel value, to the frame buffer control circuit. This circuit reads the address and stores the corresponding pixel value in the frame buffer. Repeat this process for all pixels to be changed into the image.

Transferring an address every time you transfer a pixel value is
Requires high bandwidth of the communication interface between the display processor and frame buffer.

Most bus systems include a "block transfer" mode to increase data transfer bandwidth. In this mode, one address is followed by successive entries starting from this initial address. This is followed by a number of data words that are aged into the alpha position.

You can use this mode to send vectors along the X or Y axis, but frame vectors in any direction.
For drawing to a buffer, -targeting is not useful. This is because the frame buffer is not logically oriented as an X-Y array, and the physical memory address is a combination of X and Y addresses. Since the arbitrary direction bits move in any direction, adjacent pickle addresses are generally not consecutive memory addresses.

US Pat. No. 458 by Rosener et al.
No. 6037 discloses an octant 1/registor circuit and operating mode in which the starting point of the vector I , enables all addresses to be transferred to frame buffer memory along with pixel values.

Continuous pixel data is transferred in parallel with the 3-bit '7 address defined by the octant, but the next pixel value is
Placed in relation to the previous address.

Thus, instead of sending a full address C: before each pixel, 3-bit octant data defines the location of the next pixel to attack adjacent to the previous pixel.

In particular, in the application of straight-line drawing algorithms in large memory arrays, this approach can significantly improve efficiency, but at least 3
Requires Pitsu I.

In other areas of interest, draw images such as a cursor and lines on top of the already displayed image, so that the lines can be drawn over the cursor image without destroying the underlying image stored in the frame buffer. move. Sukonic
U.S. Pat. No. 4,197,590 to K. et al. discloses an exclusive OR, or X0RII, capability that allows selective erasure to recreate straight lines that intersect or coexist with erased lines. This XOR function allows you to move or drag a portion of the diagram to any desired location without erasing other parts of the diagram. This approach requires significant computational expense and has many operational limitations.

Developed at the Xerox Palauld Research Center, the D, H, H,
Engles) is a part-time job (BYTE) 1981) (Gekkin's 168 page-194-C-
Another approach described in Graph 2 and Kernel 1 is ``Bit Bit''.
This is an action called J. This bit blitting process uses a rectangular bit map to define the image to be written to the frame buffer. When writing nine images to the frame buffer, it reads the previous information at the same address location and uses a rectangular bit map to define the image to be written to the frame buffer. Store in memory. When a new image is moved or deleted, the old information is played back to its original position in the frame buffer. This method is very efficient when applied to approximately rectangular blocks of pixel data, especially to small sizes such as cursor images.

However, the efficiency is greatly reduced when pre-existing images have to be stored and reproduced. This is the case when placing relatively simple new images on the display, such as lines, curves or simple polygons.

Another communication interface limitation in conventional raster display devices is relaying or pipelines through multiple data processing stages. Gharachorlo
U.S. Pat. No. 4,658,247 to J.D. O.) discloses an example of a conventional graphics display system that uses a line buffer pipeline connecting a series of pixel processors to achieve real-time image generation. In an ideal pipeline using this system, all stages would be
Corresponding data are processed in the same amount of time. The data transfer mechanism between each stage can be as simple as 11 registers, which are loaded with new data at the end of each processing cycle by a pipeline clock common to all pipeline stages. However, a problem arises when one of the pipelines takes more than one pipeline clock cycle to process data. When this problem occurs, the flow of data from the previous stage must be stopped until that stage finishes its processing. In other words, the process is 2
Separate into pipe stages or more. This problem is exacerbated if the time required for a pipe stage to complete its processing is variable, depending on the input data or some random or pseudo-random event occurring at the pipe stage. What can be done in this case is for the previous or upstream process to stop sending new data until the slower downstream process is ready to accept the new data. This means that each process
This means that the status of all subsequent pipe stages must be known, ie whether these subsequent stages are ready to receive new data. A simple way to accomplish this is to send a hold signal from the current stage to the previous pipe stage. This halt signal is a busy signal from the current stage and is logically ORed with the halt signal from the next stage, ie, the downstream stage. However, due to the signal delays associated with each OR game, this technique is not suitable for multi-stage high speed systems when implemented in a bus-based system.

It is therefore an object of the present invention to generate pixel data and to transfer this pixel data to and from a frame buffer.
The present invention provides a raster scan display device and method for transferring graphical data using an improved architecture and communication protocol for transmitting data.

SUMMARY OF THE INVENTION The present invention improves the method by which vector pixel data is generated and transferred to and from a frame buffer. embedded (i
The present invention, called vector direction control (mbedded),
Emphasis for Multi-Brex Address/Take Bus Systems Provides a block transfer command so that a vector in any direction can be drawn in one address cycle followed by one data cycle for each pixel of the vector. In addition to the X and Y starting axes, each address word specifies (]) the X direction, (2) the Y direction, and (3) whether X or Y is the "major" axis. 1, i.e.
Contains a 3-bit value that determines whether X or Y should be incremented for each pixel of the vector. Transfer the data word for each pixel by writing to the frame buffer. This data word contains one pinto of information that specifies whether to step along a "minor" bar perpendicular to the major axis. This bin 1- is interchangeably referred to as the small axis bit, or FBSel. When writing to the frame buffer, each data word sends a pixel value to the frame buffer. F I7-J, - Do not send pixel values when continuing to read from the buffer. That is, the data line
It remains open for pixel values to be read from the buffer or returned to system memory or other off-screen (off-display) memory. In preferred operation,
The first word is sent with the complete starting point address and the major and minor axis direction information for that vector.

A second word is then sent for each pixel value to be transferred or read. This second word includes a minor axis bit that specifies whether to step along a minor axis in the direction indicated by the axis direction bit transferred with the starting address. To write pixel data into the frame buffer, each second word is
Also contains pixel values. Upon receiving each second word, the frame buffer control circuit increments along a particular major axis direction as indicated by three bits of specific information, and increments along the first word as determined by the minor axis focus. Increment or no increment along the minor axis in the specified direction. This approach increases the effective bandwidth because it saves bus lines and additional bus cycles to draw vectors. Bus efficiency may be reduced somewhat.
The number of lines increases, but 1. This approach can also be achieved by sending the major axis selection bit and the direction bit of the major axis in the first word, and sending both the minor axis bit and the direction of the minor axis in the second word. This method can be applied to the drawing of curves and straight lines, and can also be used to draw more complex curves or straight lines by transferring the new starting address and direction information at appropriate octant transition points, i.e. vertices, of the This method can be used to form polygonal images.

Also, “Vector Blt
) is a method for extracting or interpolating pixel ray lines in a series of addresses in a frame buffer, and generates addresses using a digital straight-line drawing algorithm to control the system bus. transfer pixel values between the frame buffer and off-screen memory.

This can be used as a way to non-destructively place a cursor, icon, or other graphical entity in the frame buffer when the entity is described in a vector list. This method can be extended to curves and other scan-converted graphical entities. When using vector blits to temporarily position cursors, icons, etc. defined by vectors, you can save portions of the image to off-screen memory and transfer pixel data to frames.
Can be played in buffer. Vector bullets are made up of few straight lines such as crosses, circles and other simple shapes,
It is a more efficient way to save/reclaim pixels of a graphical entity that spans a large area. Thus, vector blitting operations can move blocks of information defined by polygons that are not limited to rectangles along the X and Y axes of the frame buffer. Use vector blit to dump 3 pixels of the pre-existing image under the cursor and safe to off-screen memory. A cursor is written non-destructively over these pixels, and when the cursor is deleted or moved, other vector blitting operations are used to reclaim the saved pixels from off-screen memory. With appropriate abbreviation and display processor software,
By using vector blits interchangeably or in combination with bit blits, a combination of vectors, curves, and block information can be used for temporal placement and movement within a frame buffer. efficiency. By implementing with embedded vector direction control for reading and writing frame buffer pixel data,
The speed and efficiency of vector blitting can be further emphasized.

Further, the present invention is a pipeline structure and method,
Pipelines can be easily extended without affecting performance, even if the processing times of pipe stages are different or variable.

This is a first-in-first method between pipe stages.
This can be realized by distributing out (F I FO). Add transparent latches to the front of each pipe stage. When the current stage is not ready to receive data, this FI
FO is a one-deep FIFO at the input of each pipe stage to accumulate data sent from the previous stage, i.e., the upstream stage.
It acts as. A register clocked by the pipeline clock is added to each stage to latch the current hold signal sent from the next or downstream stage before it is sent to the previous or upstream stage. do. Since the process of latching data and transferring hold signals continues in the pipeline, a hold signal in one stage causes the next upstream stage to generate another hold signal during the next clock cycle. . In reality, the hold signals at each stage are pipelined in the opposite direction to the data.

Since the hold signal is delayed by one clock cycle in each pipe stage, the ability to latch one clock cycle's worth of data into the FIFO is required. However, by pipelining the hold signal, no cascading or extensive logic is required to collect the signal from all pipe stages. As a result, the configuration is not limited to the number of pipe stages and is easily expandable.

The above and other objects, features and advantages of the present invention will become more apparent from the following description with reference to the accompanying drawings.

〔Example〕

(Outline of graphics system) FIG. 1 is a functional block diagram of a graphics system in which the present invention is implemented. As shown in FIG. 1, the graphics system (20) has three types of subsystems: an application gauge system (graphic data generation means) (22);
, a graphical display system (24L), and a communication channel (26) that links these application systems and graphical display systems.By separating the application system and display system, the application system and communication system can be configured according to user requirements. Graphical system functionality can be organized in many different ways with different display system performance characteristics.

The application system (22) includes an application engine, an application program, an application database, and an interface. This interface is for a communication channel that can be linked with a display system. Application engines range from local workstation computational engines to top-of-the-line mainframe supercomputers, and span a wide range of functions.
Run an application program.

The application system (22) consists of an application engine or a general purpose computer. This application system (22) is executed by application software (22A), a software interface library (22B) and an operating system (22C), which are interconnected as shown in FIG. . Further details of the application system are omitted as they are not closely related to the present invention.

FIG. 3 is a functional block diagram of the display system J of FIG. 1. The display system (24) of FIG. 3 handles interactive devices, manages graphical data structures, generates display images, and interfaces communication channels connecting application systems.

This graphics system includes all the elements that close the loop from user input to Yuri's graphics return. Advanced conversational graphics applications can be run when the communication channel has low bandwidth. A display system can store graphical data structures and generate display images. Even though communication bandwidth is very high, this ability removes a significant amount of work from the programs running on the application system.

The communication channel (26) between the application system and the display system can take many forms. The bandwidth of this channel varies between the bandwidth of an asynchronous serial communication line to the bandwidth of a direct connection with a high speed data bus. The data protocol for this channel can be as simple as asynchronous R3232C or IE
It can also be complicated like EE802.3 (Etherneft).

(Overview of Display System) The display system (24) functionally includes communication/control command/input (CGCI) (communication channel handler).
(30), Display List and Structure Storage (DLSS) (32
), graphics pipeline (GP) (34), and image storage and display (ISD) (36) subsystems. These subsystems and their interconnections are shown in FIG.

The communication channel handler (30) includes both hardware drivers and software protocols. Hardware drivers for communication devices handle hardware signal levels, timing and protocol details. A driver that controls special integrated circuit chips.
These integrated circuits, as well as software, are available to drive most communication protocols. Software communication protocols are used with communication hardware to control the passing of messages and data over channels.

Display system control includes run time control,
There are data path controls and context controls that monitor and control the display system. At the start of system operation, the display system is powered on and initialized. Diagnostics and self-tests are performed during system initialization, but can also be performed on command after system operation. Monitoring services in the run-time environment of the display system include messages, message forwarding, processing synchronization, and resource allocation. Control of data paths and data transfer is an important part of display system monitoring. For example, depending on the structure and state of the system, many different data consuming processes may handle the flow of commands from the communication channel. Display system status (context) for the graphical environment of windows and virtual terminals
Monitoring refers to the coordination and control of communications, commands, interactive input devices, graphical structures, and display list storage. Overall, the resources of a display system, including communication channels, interactive devices, image storage, and display controls, are allocated to various situations, either for dedicated use or for shared use.

The flow of commands from the application system is
Allows application programs to use display system features. The user command interface allows users of the display system to execute commands locally. Using interactive input devices, the system provides device control, reading and processing device data, and initiates graphical operations within the display system context for a graphical environment with windows and virtual terminals.

Graphical actions initiated by input from an interactive device include movement of graphical objects, 3J of visible objects, t
R, or "picking", is a switching of the graphical status of an input device or the flow of commands from an application system. Under the control of the input device, the graphical object can be moved, rotated, and transferred. Any attribute (contiguous or discrete) of a graphical structure or object can be changed by data from an input device. This includes color, shading and lighting models, along with position and orientation. Selection of graphical objects and menu items is typically performed by an interactive positioning device.

Display List 1-Storage (32) maintains display lists and structures used by both the CCCT (30) and the Graphics Pipeline (CP) (34). These display lists and structures act as key roles in the communication between CCCl and CP. Graphical "objects" are represented by display lists (configured to be in-tabletted by the CP) and control structures used to generate images on the display screen. Creating a graphical object means creating both the display list and the control structure. After creating an object, these display lists and control structures can be modified to change the displayed image. The graphical data structure variable is
Decide on the state. Control of the graphical status of windows and virtual terminals j11 includes data variables and structures representing graphical segments or objects, viewing, display lists,
and means switching the state of image generation processing.

A graphics pipeline (CAP) (34) provides a display list for scan converting display list descriptions of graphical entities into low-level pixel descriptions and for direct manipulation of pixel descriptions such as pixel arrays or bitmaps. reading and inter-screening]. When the system needs to generate a display image, it uses a control protocol to generate a graphics pipeline display list traverser (t
ravcrser ) with a display list representing the images. This causes the display list traverser to begin examining the display list. The display list includes shape primitives,
Contains a flow of graphical commands, such as pixel alignment criteria, mode settings, and attribute setting instructions, as well as control instructions. Transformations allow the construction of complex objects 1 to 1 using simple primitive shapes that are used repeatedly in a manner similar to subroutine calls in programming languages.

Scan conversion involves the process of converting a description of a graphical primitive (eg, line, character, polygon, etc.) into a set of pixels that are stored in a frame. The descriptions entered into this process are very high-level, including geometric information and attributes such as the position and size of the text, the endpoints and colors of lines, the edges of polygons, and the patterns used to fill their interiors. It is information.

Pixel/raster operations include moving pixel processors within the frame buffer itself, between the frame buffer and general system memory, or within general system memory. The architecture described herein makes a distinction between these two memory address spaces.

When transferring pixels, some limited form of processing is performed on a pixel by pixel basis.

The image storage and display system (36) provides the primary feedback to the user/operator. This feature provides the user with graphical output from the application and graphical feedback for local user input. This image storage is a pixel-based memory system that can be written to and read from by the image generation system, and is typically a frame buffer (i.e., each displayed (accumulates information that describes pixels).

In addition to storing images, this system controls and outputs data to a physical display. Since most pixel-based displays must be refreshed, this system must also include a high speed output channel to the physical display. This physical display is a device on which an image or video is formed under the control of an image storage system. Preferably this is a raster scan video type display capable of producing a full color image. The resolution of this display is commensurate with the size and addressability of the image generation system.

(Display System Architecture) The physical layout of the display system (24) is shown in FIG. All control processor functions, with the exception of the conversation device and the boot device (38), can preferably be implemented on one large multilayer circuit board called the CP board (40), with the microcode on the CP board. The software can be executed on the server. Interactive input devices, such as a keyboard (42), mouse (44), and graphics input tablet (46), connect to the CP board (40) via a serial R3-232 board or other suitable interface. CP board (40
) communicates with the graphics pipeline (34) via a system bus (VME) (48).

A block diagram of this CP board is shown in FIG. 5 and will be described later.

All functions of the graphics pipeline (34) except the final stage of three-dimensional (3D) shading are performed by the image processor 2.
(Processing means) (PP2) (50) can be realized on a single circuit board. The final stage of 3D shading is implemented on an optional Z-buffer board (Figure 8).

PP2 connects to the CP via the ME system bus (48).
and shared memory (52), as well as a frame buffer system (54) via a special purpose local display bus (56). The high-level functionality of the graphics processor (pipeline) (34) is implemented in microcode running on a microcode engine (Figure 12A) called the Bit Slice Engine, while the image transfer and embedding Low-level functions such as vector direction control are performed using special purpose hardware (first
2B, 12c and 12D).

There are various implementations of the frame buffer (54). For example, for a color display, a single board may be an 8-plane (256 colors) system, or two boards may be a 12-plane (4096 colors) system. 2nd frame・
By adding a buffer board, a 12-brane system can also be configured like a 24-brane system. By reducing the 8-plane board, a single-board 4-brane (16-color) system can be constructed.

A single plane board is sufficient for a single color display.

The preferred embodiment is a 1280X1024 color CRT monitor operating at 60 Hz non-incremental.

FIG. 5 is a block diagram of the control processor (40) of FIG. 4. This control processor (40) executes high level graphics and I10 control rasters. These rasters include processing of communication with the application engine (AE) (22), translation or routing of the flow of commands from this AE, generation of commands for the graphics pipeline at appropriate times, and internal geometry structures. generation and management, management of input from users, and management of graphics pipelines. In the extreme, the CP is the part of the display system that determines the functionality and semantics of the graphical display system (20) from the AE and user's perspective. In a preferred embodiment, the control processor (CP) (40) is a Motorola 16 MHz
68020 type microprocessor (CPU) (60)
and a Model 68881 floating point coprocessor (FPU) (62). Also, CP(4
0) connects the 68020 to the system bus (VME) (48
) for interfacing to a system bus interface circuit (64). Thus, the CP can communicate with other processors or memory systems via the bus. CP memory (66) provides 4 megabytes on board RAM. With the communication interface (6B),
The CP can communicate with external devices. This interface supports R3-232 serial communication (asynchronous) with over 38,400 volts (higher speeds are possible with an external clock)
, 2 R3-232C serial communication ports and Centronics type bar 1~” copy boat, and I rEEE
It supports 802°3 (Ethernet) and Neso1-work.

Immediately after power-up, the microprocessor performs initial diagnostic tests to ensure that the system can load from the boot device. After the initial self-test, use the boot device to load the DS software and CP microcode. The boot device is 5.25 with a storage capacity of 1 MB.
An inch floppy disk may also be used. The power-on code, initial self-test, and boot load of the CP system are stored in FROM/ROM;
/ROM is the microprocessor address space (66
) is present in the specific "power up" part of

Control processor subsystem (40) (for workstation configurations, application engine (A)
E) Subsystem (22) also logically supports display lists and other data structures (32) in shared memory (52).
) and physically communicates with the graphics pipeline via the VME system 1 bus (48). (See Figure 7) Any memory that can be accessed by the bus (for example, memory (66) on the CP board in the case of a standard terminal structure) can be connected to a pipeline that is a bus mask, such as the image processor described below. Accessible by steps.

This communication is performed between the CP board (40) and the PP2 board. CP and PP2 provide both a mask and slave interface to the VME bus (48). The mask interface is the primary interface used during normal system operation. These are used to examine display lists and access data structures (which may or may not logically share the CP or other VMEbus masters). ■ME of PP2
The slave interface is used during initialization, microcode debugging, self-test execution, and receiving interrupt requests. The slave interface connects P to the CP/AE via the VME bus.
Make certain hardware elements of P2 visible.

The most important data structure constructed by CP for the graphics pipeline subsystem is the display list (32) (Figure 3), which contains a byte organization of instructions containing graphics commands and associated data. 15. I can do it. frame buffer subsystem 1,
All graphical operations, such as actions performed on the board, are controlled (or at least monitored) by the display list.

(Graphic Pipeline Subsystem) Top functions of the graphic pipeline (34) (Figure 3)
A breakdown of the levels in the form of a data flow diagram in the sixth section.
As shown in the figure. In this diagram, circles represent processes and horizontal lines represent data structures. The arrow represents the flow of data, and the box represents I.
10 devices (data sources/sinks). The entities shown in this data flow diagram will be briefly explained below. The geometry pipeline is divided into three main processing subsystems: the modeling of spatial processing and control (MSPC) subsystem (MSPC) (80), and the transformation subsystem (82).
, and a screen space and pixel processing (SSPP) subsystem (84). Many data structures in common memory can be accessed (
some changes). All three subsystems are
Can perform fixed-point and floating-point operations.

Within the context of a graphics pipeline, the term "space modeling" is used to describe the geometric coordinate space defined in the display list. The MSPC subsystem (80) monitors all interfaces between the control processor (and/or application engine (AE)), the graphics pipeline, and the frame buffer system, as well as many situations within the graphics pipeline. / Responsible for raster management and adjustment. The MST)C subsystem (80) performs "pre-transformation" (spatial modeling) operations on the display list coordinate data, if necessary.

The transformation subsystem (82) performs intensive operations on scales, points (coordinate transformations), vectors (dots and intersections, length normalization), and matrices (matrix multiplication, decision evaluation, solving linear systems) numerically. Treat it as such.

Screen space and pixel processing nub system (84)
Shape primitives (lines, text, panels and areas)
, and direct manipulation of pixel data (bit blit, vector blit), which facilitates scan conversion of frame buffers and direct manipulation of pixel data (bit blit, vector blit), and clipping/leathering (scis
soriB).

The graphics pipeline operates as an instruction set processor and executes display programs residing in system memory. This system memory is
Shared by the application engine, control processor, and graphics pipeline subsystem.

This program is called a display list (86). This display list can be generated by the application engine and/or the controlling processor. The graphics instruction set includes instructions called opcodes that draw graphic primitives and control their attributes. In addition to regular graphical opcodes, the graphical pipeline architecture also supports simple "generic" instruction
Allow sets to be added. This can facilitate the generation of spontaneous algorithmic display lists (with the aid of real-time dynamics, programmed animation, and CP-free systems). Separately defined opcodes can be added to the pipeline instruction set to access microcode for customized operations. In addition to the display list, there is a control block (88) in the shared memory. These include pipeline control blocks, display raster control blocks, and associated data (eg, stack). These structures maintain "environmental state" information for the various display lists. Each "independent" display list has its own raster control block and stack.

The MSPC subsystem (80) handles the pipeline side of the display list and control block access protocols. It includes a display list parser and dispatching mechanism. It converts data from display list format to internal pipeline form. It manages the stacks associated with each display list. The MSPC subsystem executes generic pipeline opcodes. The MSPC may contain "hot side data," pipe data, pixel primitives, and/or control information or other pipeline data.
Subsystems and receive status and/or results from various subsystems. The MSPC module is the central control f in the data flow network for the graphical biplin.
ffll and communication nodes. Support for display list checking and pond external protocols are logically contained within this module. Display list whose function is mainly control-oriented C mode setting operation, change of control operation, etc.)
The opcode is executed within the MSPC subsystem.

The code that allows CP to access the hot side mechanism is also
A logical ζ exists within the MSPC subsystem. term"
Hot side j is the video output side of the frame buffer; this hardware assists the frame buffer in raster scanning and generates video and timing signals for the CRT (58). All other video signal sources also
Included in this category are those that mix their output into a digital video stream on the path to the CRT. On the other hand,
The "cold side" of the frame buffer is a random access port, which performs scan conversion and raster operations. All access to the hot side facility occurs through the pipeline and accesses hot side data through display list opcodes. "Pixel primitives" are geometric primitives (
lines, text, markers, panels, etc.) whose geometric coordinates are directly represented in frame buffer pixel coordinates. Since it is like this, there is no need to convert it. Pixel space primitives provide the frame buffer with the highest achievable pipeline throughput from the display list by bypassing all conversion processing. Display list to disable conversion processing
The instructions provide pixel space primitives in microcode/rough 1-ware.

The primary purpose of the transformation subsystem (82) is to model and observe transformations in display list coordinate data. It also performs matrix multiplication on the coordinate data. It also performs matrix multiplications (to generate complex transformation matrices) and perspective partitioning. Other advanced arithmetic operations are performed within the conversion subsystem.

Primarily, "pipe data" is a stream of geometric primitive coordinates (modeling in-space, out-of-screen space) that flows from the MSPC subsystem through the transformation subsystem to the S S P subsystem.

The 5SPP subsystem (84) is capable of responding to viewboard/viewboard raster clipping, scan conversion of graphics primitives, and raster operations on pixel arrays. 5SPP provides a description of a specified graphical entity in pixel space (and Z buffer) coordinates and generates (or retrieves) the appropriate set of pixels and moves them to/from the frame buffer or main memory.

This algorithm executed by the 5SPP subsystem is
This is realized by a combination of microcode and hardware.

Architecturally, the pixel array (92) in the system memory (52) may be the source and/or destination of the bi-nodprint and hector-blit operations. Scan conversion of graphics primitives by the 5SPP subsystem is performed using these main memory
You can change the pixel array and pixels in the frame buffer.

When scan conversion fits (arbitrary area) into a frame, 5SPP
The subsystems are "Siding List", "Scanline List J" and "Fill Pattern Data Structure".
using a scan-converted data structure containing Bit map character fonts and marker phono 1- are stored in a format similar to other pixel arrangements. Each character/marker definition occupies approximately a rectangle of the overall font pixel array. Dash patterns for straight lines and halftone patterns for bit bullets and background prints have their own special data formats.

Finally, some data to/from the frame buffer subsystem (54), I! There is a lag. There is one control register data (96). A number of control registers exist within the frame buffer subsystem. Some of these are on the "hot side" such as the video multiplexer routing registers and the frame buffer visibility mask. The others are: pixel combination rules register, read/write massier,
and on the "cold side" such as the local display bus address manager register.

Pipeline subsystem and frame buffer
The primary data flow between nub systems is that of pixel data (98).

The basic mode of conversion is to sequentially write (pixel (98)) or read ( It is like a linear block of (100) pixel data. With embedded direction control, the necessary side of the address cycle occurs only at the beginning of each block, but the data cycle occurs at each pixel.

Overall bit plan index chi
Color map data (102
) to these tables via the graphics pipeline. By reading the return path through the pipeline, the output color data (104) is available to the system for diagnostic testing.

"Haku" data (104) is data stored in the local display bus activity register. Using this, V
The ME bus mask can capture pipeline output data initially going to the frame buffer, update the "virtual" frame buffer in system memory,
or can be used for other purposes such as diagnostic testing. The bug is activated/deactivated by writing to the control j11 register in the frame buffer subsystem. When activated, each LDB write cycle defined for the frame buffer memory is blocked and accumulated in the bug.

Also, the pipeline is kept off until the VMEbus mask is not loaded this cycle.

FIG. 7 is a simplified block diagram of two examples of graphics pipeline configurations. In the two block diagrams shown in FIG. 7, pipeline data flows from left to right depending on board position. The control processor subsystem (40) is logically to the left of the graphics pipeline (34) (including PP2 (50) and LDB (56)) and the frame buffer subsystem (54).
is logically correct. The preferred embodiment includes a picture processor (PP2) board and its microcode, and optionally a Z-buffer (ZB) board. When using a ZB board, this ZB board divides the LDB into two parts (56A) and (56B).
Divide into.

FIG. 8 is a high level block diagram of the ZB board.

The Z-buffer algorithm (110) implemented in the central part of this figure is simple and is a known technique for hidden surface removal used in the depiction of 3D geometric images on mask displays, so a detailed explanation will be omitted. do. In the preferred embodiment, the Z-buffer (110) has a 1280x1024x16 bit Z-buffer memory (112) for storing depth information for each pixel location. The ZB board also includes special hardware to perform triangle allocation. This hardware consists of a programmed logic controlled θU unit and a brane equation generator (P
GE) data path gate array (114
). The functions of this hardware are (1)
Calculate the depth and brightness at each pixel of each triangle,
(2) pass the luminance value of the pixel (in the visible part of the triangle) to the frame buffer; (3) update (so that each pixel position always contains the Z value from the triangle closest to the viewing position) The main purpose is to maintain a Z-buffer memory. The ZB board also includes a bus through path (116) to bypass data around the Z buffer function.

PP2 and 7 on the “right side” or “downstream” of PP2
The hardware interface between the 8977s is a clocked, bidirectional, 32-bit multiplexed address and data bus, which is the Local Display Bus (LDB). This bus has an input side (I
LDB) (56A) and output side (56B). Therefore, the ZB board has I L on the input (left, upstream) side.
There is a slave interface for D B (56A), an output (right, downstream) side, and a mask interface (118) for DI3 (56B). Data enters via a 2-deep bus unit (120) and outputs via a 16-deep data FIFO (122) to the LDB bus driver (124). This bus driver (124) transfers data to the frame buffer subsystem (54). The ZB board has
Return data path (12) bypassing ZB (110)
) is also available. Return data enters the 2-deep FIFO (126) from the LDB (56B) and is output to PP2 by the ILDB driver (12B). This FIFO and its operation will be further described below with reference to FIG.

In the following description, we will discuss the interface between the graphics pipeline and frame buffer (local display bus), the image processor (PP2), and the frame buffer system 1ll.
(FBC).

(Local Display Bus (LDB)) As mentioned in i, the graphics pipeline uses the local display bus (LDB).
L D B ) to the frame buffer. Below, Figure 9, 108th to 10th F
The structure and function of LDB will be briefly explained with reference to the drawings.

LD B is connected to PP2 and ZB board.
Connect ZB to the FB frame buffer (54) (or if using ZB (110), connect PP2 directly to the FB). The bus (shown in more detail in Figure 15) is
Preferably, it is a 32 pin multiplexed address/data bus synchronized with a 74 nanosecond common lock. Each address or data cycle is one
Exists in the clock cycle. Many data cycles are allowed for each address cycle, implying an address increment (the increment value previously communicated to the slave). Each board has a FIFO of two or more depths for receiving data (or addresses). The ZB has two left-to-right FIFOs (120), (122) and a return or read FIFO (126), as described above, which can accept data from both sides. Frame buffer nub system (54) is FB manual FIF
O (130) and FI3 read FxFo (132) to write or read pixel data in the frame buffer memory (130).

below,? i'+- is provided with a communication interface for the PP2 board (50) by a vector address generator or tiling address generator called rTAG chip J (13B). (Preferably, a tiling feature is provided to allow use of ZB boards, but is not directly relevant to the present invention. The TAG chip (138) has an output FIFO (
140) and input FIFOs (142), which can be easily combined into a single FIFO to provide alternate l10 data on multiplexed address/data buses.
Can be used as FIFO.

Handshaking is performed using the input ready and output ready signals. The sending side of the board does not require a FIFO, but must generate an output ready signal and receive an input ready signal. In systems without ZB, PP
2 is a mask, and FB is a slave. When not reading pixel data from FB, FIFO (130), (
132), (140) and (142) control the pipeline. When ZB is present but not active, LDr
3 transmits with a delay of 3 pipe stages in each direction (burst rate is not affected, only latency).

I also listen to ZB as a slave.

When signaled active (by writing to the ZB control register when tiling is about to start), ZI3 splits the LDB into two buses (56A) and (56B) and acts as a slave and as a mask for the FB (during the tiling period, PS2 sends the starting address and brane equation increment for each horizontal line segment to ZB;
Send pixel data write and address update to FB.

FIG. 15 (7' of frame buffer control circuit.

In the diagram), the LDB (56) consists of 32 address/data lines (150) and 7 control lines, and does not include reset and clock signal lines (not shown).

The address/data lines are tri-stated, but are not control lines. A system called F B S E L
<'Ill life (152) is 2 on FB and ZB
Select between two address increment values. The read, write and address control signals sent by PP2 (or ZB) are encoded into two lines (154) and (156). By the logical sum (OR) of these two tree lines, P
Obtain an output ready signal (155) from P2. FB is
7 via oven collector wire and line
and returns the input ready (IR) signal (158) to PP2. The IR determines whether the input FIFO (130) accepts an address, write data, or subsequent command by applying a "not held" signal to the upstream FIFO (p, indicating readiness). The output data is sent in a different direction (FI
i3 to PP2) and two different handshake signals, namely Read Output Ready (ROR) (162).
and read input ready (RIR) (164).

When read data is available in output FIFO(1,32), FB sends ROR(162) to Pl)2. This is an open collector wire and line. The FB sets this line (it can be raised ``high'') not only when reading available data, but also when it is released. PP2 sends RIR (164) to FB indicating that it is ready to receive read data. In addition to the two read handshake signals, a read output enable (ROE) (16
There is a third line called 0). This line explicitly controls the slave's output buffer enable with one clock delay (ie, the slave must register this line and connect this line to the output buffer enable).

Some timing examples will now be described to make the use of these signals more clear. These timing diagrams (Figures 10A to 10F) show which signals are asserted (output) in which clock cycles.
It does not indicate the delay time within a clock cycle.

Vertical lines indicate rising (active) clock edges. The space between a pair of vertical lines is one clock cycle (
74 nanoseconds). Signal names are shown on the left side of the diagram, but do not represent the polarity of the corresponding physical bus line.

A horizontal line drawn on each clock cycle indicates that the signal is asserted. No signal is asserted in the remaining space. Address/data buses use three-letter codes in horizontal line segments to indicate what information is on the bus.

'a a i3 J represents the address, rrdl' represents the first word of read data, rwd I J represents the first word of write data, and so on.

Blank represents a high impedance state on the address/data bus; .

Figure 10A shows a simple burst of 9 writes. This example is typical of pixel representation of vertical vectors. After performing the address cycle, the mask (PP2)
Perform 1 write data cycle. Whenever input ready (IR) is not sent from FB, PP2 keeps the same write data on the bus for the next clock period. In this example, the FB sends the first 5 words to its FIF
must be fetched into O and wait for a memory cycle. Since two pixels of the vertical vector can be populated in each memory cycle, two additional words are captured after each memory cycle.

Next, Figure 10B shows a burst of six reads. F
The IR line from B is used to indicate that it is ready to accept a read command, even if no data has been passed. In this example, the FB buffers 5 subsequent commands and eliminates IRs until there is room for a 6th. This (as happened for the vertical double tacho)
Returns data from the read in two bursts.

PP2 does not remove its read input ready line (RIR) because it is always ready to accept data. The XXX at the beginning of ROR and RIR is a "bit care" because the previous state is unknown. Even with very fast slaves, the first read data word may not be returned before the third cycle. Thus, up to that point (ie, for the cycle during which the first read request is sent), the associated handshake lines (ROR and RIR) can be undefined.

Thereby, the slave (FB) determines whether these are selected or not. Buffered bus-through boards (ZBs) clear their read data FIFO logic on subsequent address cycles to remove any shadow of unknown control lines. The following example is PP
2 shows what happens when the entire burst of read data cannot be received at once.

The first OC diagram shows a burst of four reads with a short latency. Here, FB receives all bursts of read commands at full rate, but PP2 cannot handle full rate data returns.

P P 2 takes the first two words and removes the RIR. Two clocks later, PP2 is primed for one more word and reasserts RI_R. Furthermore, after two clocks, quasi 67,y is applied to other words. After this fourth word, remove RIR again and PP
2 indicates that the quasi (I+if) has not been completed for another word. Since the read data is no longer available, the next RI R has no effect. The data is returned in the next cycle. If so, set ROE simultaneously with the first cycle of RD to enable the slave's output buffer.As the final word of read data is clocked by the '7 star, ROE is removed.

Figure 10D shows two reads followed by two writes. To avoid data bus contention, writes (including address cycles) should not begin until two cycles after ROE has been removed.

This allows one cycle for slaves to disable their drivers in response to ROE deassertion and bus dead cycles to prevent contention.

Figure 10E shows a slow write (typical of a control register load). This example represents two interrupts, each with an address cycle. This is typical of a control register load on a ZB or FB. Note that the data cycle does not immediately follow the address. Such gaps are allowed in some other instances as well. It is also allowed to have gaps in the middle of many read or write cycles, as shown below.

Figure 10F shows slow readout. This example shows a slow burst of three reads. Until a clock after the first read request (until cycle 5 in this example), the slave does not need to respond to the known state of ROR. R
Note that the slave does not drive the data bus until one clock after OE is asserted.

(LDB Address Map) Next, the address map of the local display bus, the definition of its structure, and the function of data communicated via the LDB will be described. LDB each addresses 232 32-bit words. Byte or other partial word conversions are not supported. Devices below 32 bits simply return undefined data (garbage) on unused lines during read periods and ignore extra bits during write periods.

The address space consists of 16 words of 2211 words each.
Split into sections. The lowest section is I1
0 space (bits 31, 30, 29 and 28 are all 1). The lowest section (bits 31-28 are all O)
) is the frame and Z-baso memory space. The remaining 14 sections between them are reserved for future systems that reside on the LDB. Neither FB nor ZB responds to these addresses.

The I10 space is further divided into 16 slots of 224 words each. Each slave LDB board has f-
4 slot pins on a side connector (not shown). It also supports other software, if properly configured.
Also responds to slot address. Clear (disable) all soft slot addresses by reset. In a hard slot, the I10 space is 11
L l5SSSaaaaaaaaaaaaaaaaaaa
It's aaaaaa. where 5sss is the slot number and a represents the remaining 24 address lines available to decode the I10 location within a given board.

The memory space of FB and ZB is 00001]xY in binary
Myyyyyyyyyyyyyxxxxxxxxx
It is. where H is the "hesitation" bit (when set, this bit indicates no step before the first pixel) and X is the X step direction (the set is from right to left). ), Y is the Y step direction (the set indicates top to bottom), M is the major axis indication bit (the set indicates the X axis is the major axis), and yyyyyyyyyyyy is the initial +ItJI]
where xxxxxxxxxxxxx is the initial X position.

Both frame buffers of the double buffer system ZB and all of the overlay frame buffers occupy this one address space. Control registers accessible through the 110 space allow each buffer to be enabled and disabled. Accessing any one buffer can be accomplished by enabling it and disabling all others.

The FBSEL is used to control address increments during data cycles in the memory space. When FBSEL is set, it steps both the major and minor axes before transferring data. Unless FBSEL is set, only the major axis is stepped. If the hesitation bit is set within an address cycle,
The first data cycle ignores FBSEL and does not step any axis. Additionally, data cycles typically follow the FBS EL.

F B S E L has additional meaning to ZB. During the address cycle for the memory space, F
BSEL determines which brane equation increments register for use. This function is used in 3D tiling. PP2 sends FBSEL during the address cycle and the new X position is the left (small crawl) of two possibilities.

(Image Processor (PP2)) FIG. 11 is an overall block diagram of the image processor (PP2) used in the graphic pipeline of FIG. 7. This image processor (50) comprises many functional elements. Connect PP2 to the vME bus from VME master ink 7, z-s (170) 2. This also means that V
Boot and debug circuitry (172) connected to the ME bus
). The implementation of this is mostly prior art and is not directly related to the present invention. Information communicated by the VME bus via the VME master interface (170) is transferred to the internal picture processor bus (PBU).
S) (174). This bus is Pippi...
Main data used by slice engine (17G)
It's a bus. A vector or tiling address generator (TAG chip) (138) connects the local display bus (5
6) Interface to. TAG chip (1
38) is shown connected to the conversion engine (178). Further, as described below, the information on the PBUS (174) can be passed directly to the local display bus via the TAG chip (138) without being converted by the conversion engine (17B).

Figure 12A shows the microcode or bit slice
Preferred realization of the engine (176) and PBUS (17
4) VMEbus interface (170) via
The details of the interconnection between and conversion engine (17B) are shown. The general structure and operation of a bit slicing engine is:
Since it is well known to those skilled in the art, only those parts relevant to the present invention will be described.

12th A 1, 12th A2, 1213th, 12th C
and FIG. 12D are more detailed block diagrams of the image processor of FIG. 11. In operation, the VME bus interface operates under the control of a program counter. This program counter provides a pointer to the next instruction in the display list to be executed. Following this program counter, the interface then fetches each command. As the interface processes each word, it loads each word into a rotation register (180), maps it off, loads one byte of this word into a sequencer (182), and loads the remainder of the word into the data r.
Accumulate in Scrunch Pad RAM (184). If the word is an image command, such as a move instruction, this instruction conveys that the next two 32 bin 1-words are the X and Y coordinates of the first address of the vector. The bytes loaded into the sequencer address relative positions in the lookamp table, and the array of instructions has jumps controlled by the bytes loaded into the sequencer. This causes the sequencer to move or branch to a routine that proceeds to the first point of the plane.

Due to the flow of control of the sequencer in the movement instruction, the instruction is
Reads the next two words from the M E Hass interface, sustains the chain with a list of instructions in the sequencer, and sends these words to the transformation engine (1
78). If these words are relative coordinates of the starting point of the vector, the bit slicing engine performs the appropriate addition or other subtraction in an arithmetic unit (ALU) (186). If these words are in a format that does not require ALU processing, a command that says this is the first point of the vector will transfer them directly to the conversion engine. If no conversion is required, the conversion engine simply passes the vector information to the TAG chip for encoding. The endpoints of the vector are treated similarly, TA
Send it to G-chip. At this time, the TAG chip has enough data to encode and send the vector to the frame buffer subsystem.

The bit slicing engine constitutes a single pipe stage process with distributed FIFO control. This control uses the same 11 FIFOs in the TAG chip and conversion engine.
By control, processing can be delayed if a hold signal is received from the frame buffer or Z buffer. one downstream stage,
For example, when the frame buffer encounters processing delays,
This sends a hold signal to the next upstream process in the pipeline. The process stops sending further data until the hold signal is removed. When that FIFO is full, it sends a hold signal to the next upstream stage. In this method, due to the intermediate FIFO stage, the corresponding
After a number of cycles, the bit
Processing in the slice is preserved.

The bit slicing engine processes vectors used to read and write frame buffers to perform vector blitting operations. This is V M 17.
obtain commands (opcodes) and coordinates for the vector from, execute commands that generate output commands and data for the transformation engine, further process (transfer) the data,
Output data and commands to the TAG chip to generate vectors using embedded vector control. To read a vector in the frame buffer, the bit slice engine receives a read mode command, forwards it to the TAG chip, and transfers subsequent vector address information to the frame buffer sub Place the TAG chip in read mode to send to the system.

However, this time the TAG chip does not send data.

This enables the logic circuitry to read the frame buffer data so that the accumulated pixels along the vector are read back along the local display bus to the TAG chip for the bit slicing engine.
Accumulate in off-display memory. After all vectors of pixel data stored in a frame buffer have been read out, new pixel data can be loaded into the frame buffer location H defined by the same vector using a vector blitting operation. .

Figure 12B details the conversion engine (17B) and the TAG chimp (162) for the local display bus (156).
) shows the interface.

The structure and operation of the transformation engine (178) is well known in the art, and its operation is transparent in the context of the present invention to briefly describe this transformation. Generally, the input to the conversion engine is via the P bus (174). The conversion command is stored in the command register (1
90) and sends it to the sequencer (192). Other commands and data can be entered via registers (194) if a conversion is to be performed, otherwise
Bypass this register and use the internal bus (TBUS) (
196) directly. The transformation engine includes a multiplier (193) and an adder a (195) controlled by a sequencer (192) to perform the transformation. If these are not transformed, the vector coordinates will be stored in the register (194
) and is directly transmitted to the TBUS TAG chip (13B). If a vector is to be converted, the appropriate conversion command (opcode) is stored in the command register (
190) and a sequencer (192), which controls the operation of the conversion engine in a conventional manner and registers (19
4) Convert the vector coordinates input in the conventional format.

The transformed vector coordinates are output to the TAG chip (138).

Figures 12C and 12D show the TAG chip (138) in more detail. First, refer to FIG. 12C. TAG
The chip interfaces TBt, Is (196) on the left and the local display bus (56) on the right. The other input and output lines shown on the right side of this figure correspond to the input and output lines shown on the left side of FIG. 15, which will be described later. The TAG chip includes a control '4'[l+ state machine, the operation of which is relevant to the present invention, is
This will be described later with reference to FIGS. 16B and 16C. This state machine controls the Address Engine (202), which generates embedded vector control information. Color register (204) receives and relays color information regarding pixels to be written within the frame frame. This information becomes part of the pixel data, which becomes the pixel value. The address output from the address engine and the data output from the color register are
input to the multiplexer (206). This multiplexer is controlled by control lines from the state machine (200) to transfer address and data words to the FrF
o (140) to the local display bus in the form of 'UtR. TBUS is input directly to the multiplexer (206), selected for vector blit write operations instead of color registers, and output to the local display bus (56).

One after another, 9 included, F B S E L, input ready (I
R) Control lines (152) to (15B) are also FIFO (1
40) is output in the same way. Read, write and FBS
The EL bit is passed from the state machine (200) to the FIF
Enter O. Pipeline the "input ready" upstream and control the unloading of the output FIFO (140). T.A.
The G-chip also includes an input or outgoing FIFO (142) through which the outgoing pixel data from the frame buffer is transferred to the TBUS (196). A state machine (200) generates a "continue output enable" signal. "Read output ready"
Signal (162) is used to control the loading of FIFO (142). “Empty Coline (165) is FI
Tells the state machine (200) whether the FO (142) contains the word to be read. "Read input ready"
Signal line (164) provides a hold or non-hold signal to the output of the frame buffer subsystem or to the follow-on FtFO.

In Figure 12D, the TAG Chip Address Engine (201) includes an input multiplexer (210) that interfaces with the TBUS (196). The address engine (202) is a conventional digital differential analyzer hardware implementation of the type commonly used to implement Presenham's algorithm or similar vector drawing algorithms.

For an example of this, see US Patent Application No. 709,629, filed July 30, 1987. address·
The engine includes a series of registers (212)-(224) to hold variables used in computing Presenham's algorithm.

These variables are generated in the process shown in the flowcharts of Figures 16A, 16B, and 16C. The respective outputs of these registers are input in parallel to two multiplexers (226) and (22B), and their outputs are added/subtracted ALU (23
0). The output of the ALU (230) is input to both the multiplexer (210) and the read counter (232) and pixel counter (234). The X and Y addresses are input to the multiplexer (206) (Figure 12C) via the address latch (236). The independent octant latch (238) receives four additional bits and outputs them to a multiplexer to provide embedded hector control direction information. Two of these bits are the sign bits of registers (222), (224) and correspond to directions in the Y and X axes. The third bit is the sign of the ALU output, and represents the maximum component (X or Y) of the vector from the start point to the end point as a major axis. The fourth bit is the movement flag (11) register (24
This is the hesitation bit received from the STATE l-machine (200) via 0).

(Frame Buffer Control) FIG. 13 is a block diagram of a frame buffer control circuit for accumulating image data for image data accumulation in the system of FIG. 15 is a preferred embodiment of the buffer controller;
The figure is a block diagram showing the operation of the frame buffer control circuit.

A frame buffer subsystem (54) and a display (58) provide high performance connections to the graphics pipeline;
Provides a high-resolution, flicker-free display. A schematic block diagram of the FB subsystem is shown in FIG. High system throughput is obtained with a flexible frame buffer controller designed to balance single pixel (vector) performance to pixel block transfer operations. With this frame buffer configuration, several memory cycles go to separate sections of memory at the same time, so that random directional vectors affect memory close to the maximum available bandwidth. VME system・
There is no direct connection between the bus and the frame buffer. Therefore, there is no way for the CP or AE to interact directly with frame buffers as if they were general purpose real memory. Instead, the frame buffer interface (248) supports this possibility, but it is not directly relevant to the present invention and will not be discussed further.

The preferred embodiment uses a 12-plane frame buffer configured as two individual boards, with one board containing the frame buffer memory and associated controllers (FF3C). The other board includes a color map RAM and a video circuit (250) associated with the DAC1. A timing circuit (254) is provided to generate the appropriate timing signals to drive a 60 Hz non-inclace color monitor and to provide all timing necessary for the frame buffer and graphics pipeline subsystems. give a signal.

Gate array, frame buffer controller (FBC)
The IC (260) each has a 4-bit brain frame.
Control buffer memory.

One of the FBCs (260) is shown in general block diagram form in FIG. FIG. 15 is a more detailed diagram, but limited to features suitable for the present invention, showing an alternative implementation of the frame buffer subsystem.

These implementations are described below, with similar elements designated by the same reference numerals.

FI3C (260) is the local display bus (1-DI3
) read/write registers (262), (26
4) and a register (266) for generating a screen refresh address. Resident of the FBC is a small ALU (266) that performs the operation of pixel data to/from the frame buffer memo'j (136).

In response to the data and control fff[l signals, input and output FIFOs (130), (
132) via the local display bus (56). Upon receiving the first word denoting the address for the starting point of the vector on the multiplexed data/address line (150) (FIG. 15), the X and Y address counters (280), (282) 1 word X
and is set to the address included in the Y address portion. A multiplexer (284), controlled by the bus control stage 1-machine (2F36), inputs the second word following the first word and the pixel values from the following words into the data register (264).

The state machine (286) has as input and output:
Various signal lines (151) to (164) (Figure 15)
It is equipped with Upon receiving the second and subsequent word of pixel data, the state machine increments the major axis address counter and, if F I3 S E L is set, also increments the minor axis counter. incremented x
and Y address along with the corresponding pixel value into the data register (264).

Launch address and pixel ray direct data (266)
and passes it to N deep FIFO (2811). This FIFO is controlled by a FIFO controller (290), and its operation is detailed in U.S. Patent Application No. 702,982 filed on February 19, 1985 (Japanese Unexamined Patent Publication No. 61-190).
(corresponding to Publication No. 387). Since the details of this system are not directly related to the present invention, a detailed explanation will be omitted.

Conventional circuitry (
292). A data output circuit (294), including AL[J (268), writes pixel values to addressed locations in the frame buffer. This data circuit uses a frame signal when a read operation is performed.
A register into which pixel data is input from the buffer (
269) is also included.

FIG. 15 implements the above-described situation of the invention using hard logic rather than state machines. 15th
Many of the features shown in the figure are based on the LDB structure (line (150)
~ (164)), FIFO3 (130), (132),
Those already described include the frame buffer memory (136) and the X and Y address counters (280), (282).

Octant latches (270) are embedded in the first address word of each vector. '
[D 117 Receive and accumulate information. This latch has X and Y direction outputs to the address counter,
Controls whether these counters count up from the starting point address or restart the count. The major axis bit is a set of game 1. (271), (272)
is output to. These gates determine whether the counter (major counter) increments (decrements) in response to each subsequent "read" or "write" signal (line (154)). Read and write signals to other Im
Input to game 1-(273), (27/l). These gates increment (or decrement) the major axis counter
To do this, provide an output to each counter and increment (or decrement) the Mylar-axis counter when the FBSEL line (152) is set. When both the “read” and “write” J lines (line (155)) are set, this indicates an address cycle and logic (27
1) to (274) give a "load" signal to the counter and input the prayer address X and Y.

The data register (265) corresponds to the low part of the l/register (264) in FIG. /s counter outputs the pixel value to the frame buffer memory (136).

This input is controlled by the input (156) via the OR gate stage of the logic (274) and the register (275). This line is
When sent high, it reads the pixel value from the frame buffer and sends it to the output FIFO via the data output line.
(132)). A cycle request from the output of the game 1 (274), 1 line, is sent to the game 1 through the register (276). - Input to the system buffer start cycle control ■.

The FO control block 1 (278) controls both the input and output FT FO. The logical formula governing this operation is as follows.

IIJnload = GRead and GWrite
Or Gl? ead and done and no LOFu
l lor GWrite and Done OLoad = Gleanad and not GWrit
e and Done and notOFull This block uses the input FIFO during the write operation.
and controls the unloading of data to the output FIFO during read operations.

(Embedded vector control processing) Figures 16A, 16I3 and 16C show the control state machine (200) and address engine (202).
FIG. 12C illustrates the process of implementing an embedded vector control protocol to write or read pixel data along vectors in the frame buffer.

The processing section shown in FIG. 16A receives a large car, a
From the starting and ending points of the vector, determine which axis is the major axis and the direction (plus or minus) of the X and Y components of the vector from that starting point.

Place the initial point in registers Xold and Yold.

11 people finished. - placed in registers X and Y; These registers are shown in Figure 12B. The first step is
D73 and Yold data are latched, the starting point of this heckle is determined, and the starting point address is saved in the address latch (236) (FIG. 12D).

Next, along each of the X and Y axes, the difference between the start and end points is calculated to determine the sign of the direction of movement from the start point. Furthermore, the difference in magnitude between the vectors X and Y components is determined, and the longer component axis is selected as the major axis.

In preparation for proceeding to the next sub-process shown in Figure 16B, the process branches into a left path and a right path. The left path is slightly more efficient than the right path and is chosen when the magnitude of the X component of the vector is greater than or equal to the Y component. The final step in the processing portion of FIG. 16A is to input the octant bits,
Determine the next address position along the vector in Figure 16B by latching the axial, In this case, whichever route is selected, for the next calculation by the ALU (230),
The path computes the Presenham algorithm variables in registers (212)-(224).

Furthermore, a pixel called a "movement flag" indicating whether the first pixel of the hexagonal is extracted or drawn is added to the pixel and readout counts for the major axis component. The bin l-slice engine "moves"
Sets the "move flag" bit depending on the opcode. This bit is transferred via the register (21IO) to the fourth bit position in the octane 1-u-nochi (238) and becomes the hesitation bin h. The remaining steps of the left and right paths of FIG. 16B are known in the art;
Further explanation will be omitted.

The final step knob of this subprocess sends the starting address and contents of the octant launch to start the Digital Differential Analysis Dual (DDA) subprocess, which handles the operations depending on whether the operation is a vector write or a vector continuation operation. branch out. The left branch initiates DDA, and this process is shown on the left side of FIG. 160. The right branch proceeds to determine if the operation is a vector read rather than a vector write. If it is not a vector read, this process ends and the DDA process is executed as a vector write. If it is a vector sequence operation, this branch is
The readout 7 process shown on the right side of FIG. 16C now proceeds.

The DDA processing shown on the left side of FIG. 16C follows whether the operation is a hexagonal write or a vector read.

Wooden-wise, this subprocess runs Bresenha's algorithm to determine the position at which each successive pixel of the vector is written or read, but first this Or, from the hesitation bit, it is determined whether to write or read the first pixel, corresponding to the starting point of the current bit. The current vector is
If it has a start point that coincides with the end point of the previous vector I, then using this (i.e. without cell I-L), such a pixel is overwritten twice on [-1]. , prevent it from being read. This is not set when the first pixel is drawn but read. The DDA subprocess continues during each step along the major axis until the end of the vector is reached (pixel count - zero).

If the operation is vector read, the right side of Fig. 16C'
Bu process is the signal line! Enable the output data to be read from the frame buffer along the vector tracked by the ZAZOP1 process on the left side of Figure 16C. The next step is to determine if the read FIFO is empty. Typically, a few cycles are used for the first pixel value read from the frame J. buffer and read into the FIFO. This subprocess will loop until this occurs. Then,
This Zabubu[''JSeth decrements the read counter by 1,
Read the first word from the Offer I/'IFO and send it to the microcode engine. Zapupu [-1 Seth then checks to see if the Mike 1 code engine has accepted this word. Otherwise, in case of pipeline delay, the issuer will wait for a cycle and test again. Once a word has been accepted, the process first loops, checks for the presence of the next -1. Return to It advances to this point for each successive word along the vector until the end of the vector is reached.

This leave one process then clears the read output enable and ends.

For normal vector +:;i picture operations (not read), the DDA process sets the L D B write line, 1. , II outputs the pixel value on the B data line. As determined by the processing on the left side of Figure 16C, F
B S rE L line set or unset, Frame 1 - Determines where in the buffer to store pixel values. This is accumulated at the next step along the major axis, or at the diagnostic step corresponding to the step along both the major and minor axes in the direction indicated by the octant data. This pixel value comes from a previously loaded color register.

For example, the present invention can be used to draw an octagon on a display. Define each segment of the octagon as a vector with a starting point and an ending point. Each vector is then drawn, starting from the starting point of the first vector and continuing until the final vector (1.ri point) that closes the geometric diagram. At each vertex of the octagon, the next vector As needed to change the direction of the octant, send new octant information to change one or more of the octants. Circles can be drawn in the same way. Traditional methods draw a series of short straight line segments. To approximate a circle, we sent a new address at the start of each short straight line segment.However, we extend the vector definition to include arc segments and use the octagon base described above. , we can draw a circle.When the change in the slope of the arc is outside the range of 0 degrees and 45 degrees from the major axis in the minor axis direction, we need to send a new address.These principles can be applied to any curve It can also be extended to

(Vector Blit Mode) In Figure 18, the presence of an 8-bit opcode in the display list initiates a vector blit operation, which causes the microcode engine to perform the vector blit write or read operation described above. Execute. The command structure includes pointers to off-screen memory locations of an array of pixels to be written to the frame buffer along a vector, or to accumulate pixels read from the frame buffer along a vector. This is followed by a conventional sequencer of move, draw or read commands, which define the start and end points of the vector to be written or read.

If you temporarily place an octagon or circle or other vector-defined diagram on the screen, cross the vector twice. First, perform a vector blit read and read the frame.
Save the previous pixel value along the vector from the buffer to off-screen memory. Vector drawing is then performed along the same set of vectors and a new vector definition diagram is written into the frame buffer for screen display. When a figure is removed or moved, a vector blit write procedure is read to restore the previously accumulated data to the frame buffer and overwrite the accumulated figure pixels. Each of these vector blit operations is
Transfer pixel values between main memory and frame buffer via TBUS. Each vector blit operation is terminated by an opcode that inverts the vector blit mode.

(Distributed FIFO Control) FIG. 17 shows the principle of the distributed FIFO pipeline structure and method. Even if the processing time of the board and pipe stages increases or changes, this will not affect the performance.
Pipelines can be easily expanded. This is accomplished by distributing first-in-first-out (FIFOs) between pipe stages, as shown in FIG.

Transparent latches (300) and (301) are added to the front stage of each pipe stage, and operate as a 1-deep FIFO at the input of each pipe stage process (302) and (304). Alternatively, transparent latches and resistors (not shown) can be used to
(or more) can be operated as a deep FIFO.

Each pipe stage also has an output register (306), (30
B) is also included. When the current stage is not ready to receive data sent from the previous or upstream stage, F
This data is stored using IFO. A control register (310), (311) clocked by the pipeline clock (line (312)) is added to each stage to send the next holding signal (line (314)) to the previous, i.e., upstream stage. Latch the previous one, next, or current hold (IR) signal (line (315)) sent from the downstream stage (not shown). Each stage logically ORs the hold signal input to the control register with the busy signal from its own stage, so either the downstream hold signal (line (315)) or the busy signal (line (317)) or when both are sent, send the next upstream hold signal (line (314)) to the cell l-
do.

For convenience, the current stage (301) is represented as stage r1. The previous or upstream stage (300) is designated by 1-1 and the next or downstream stage (300) is designated by n+-1.

As long as pipe stage n is ready for the next data, it will not generate a "busy n" signal (line (31B)), so pipe control the "hold n" signal during the next clock cycle. Do not send to I line (314). If pipe stage n is not ready for new data, this stage generates a "busy n" signal. Latch the ``busy nJ'' signal into register n at the end of the clock cycle and generate a ``hold n'' signal on line (314). ``Due to the presence of the hold nJ times signal, the latch n(3
01) can hold the data from the previous clock cycle and the signal of pipe stage n-1 (302);
Continue sending the current data until there is no longer any disconnection. As the process of latching data and transferring hold signals continues to advance down the pipeline, the presence of the "hold n" signal causes the "hold n-1" signal h< on line (313) to occurs in In fact, the hold signal is pipelined in the opposite direction to the data.

Although preferred embodiments of the invention have been described, six modifications can be made without departing from the spirit of the invention.

〔Effect of the invention〕

As described above, according to the present invention, pixel data is generated and this pixel data is transferred between the frame buffer and the frame buffer.
A mask scanning display device 4 and method of transferring graphical data can be provided that uses an improved architecture and communication protocol for transmitting data.

Additionally, an off-screen (off-display) memory is provided so that the cursor, icon, and image pixels under the cursor can be stored in this off-screen memory. Therefore, efficient saving/reproduction can be performed by vector blitting or the like between the frame buffer and this off-screen memory. Furthermore, since a FIFO is provided in the pipeline for transferring graphic data, differences in operating speeds of each pipe stage can be absorbed. Therefore, a high-speed pipeline can be easily used.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a graphics system using the present invention. FIG. 2 is a functional block diagram of the software architecture of the application system shown in FIG. FIG. 3 is a functional block diagram of the display system shown in FIG. 1. FIG. 4 is a block diagram of a preferred physical implementation of the display system shown in FIG. FIG. 5 is a block diagram of the control process shown in FIG. 4. FIG. 6 is a data flow diagram of the graphics pipeline shown in FIG. FIG. 7 is a simplified block diagram of two examples of the structure of a graphics pipeline. FIG. 8 is a high level block diagram of the Z buffer used in the graphics pipeline of FIG. FIG. 9 is a more detailed block diagram of the local display path portion of the graphics pipeline of FIG. 10A-10F are timing diagrams of example read and write operations on the local display bus. FIG. 11 is an overall block diagram of the image processor (PP2) used in the graphic pipeline of FIG. 12th A1, 12th A2, 12th B, 12th C and 1st
The 2D diagram is a more detailed block diagram of the image processor of FIG. 11. FIG. 13 is an overall block diagram of a frame buffer control circuit for image data stored in the system of FIG. FIG. 14 is a more detailed block diagram of a preferred implementation of the frame buffer controller used in the circuit of FIG. 13. FIG. 15 is a block diagram showing the operation of the frame buffer control circuit. Figures 16A, 16B, and 16C are flowcharts illustrating the operation of the processor of Figure 12C. Figure 17 shows the distribution FI used in the circuits of Figures 8 and 15.
FIG. 3 is a more detailed block diagram of FO processing. FIG. 18 is a diagram illustrating instructin processing. In the figure, (22) is a graphic data generation means, (34)
(50) is a processing means, (54) is a frame buffer, and (58) is a mask scanning display means.

Claims (1)

[Scope of Claims] 1. Graphic data generation means for generating graphic commands that define a display image; raster scanning display means for displaying graphic data; processing means for converting the pixel data into the frame buffer means for storing the pixel data and outputting the pixel data to the display means;
frame buffer control means for controlling accumulation in a buffer; off-display memory means for accumulating a portion of a graphical image; and frame buffer control means for reading out pixel data from said frame buffer means and controlling said frame buffer determined by a vector. - means for storing said pixel data in said off-display memory means in response to an address. 2. A method for transferring graphics data in the form of pixel data, including the address and value of each pixel, between an image processor and a frame buffer for raster scan display, as a series of successive pipe stages in a pipeline along a bus. , processing means and frame buffer means; in each pipe stage, first-in first-out means are provided for transferring pixel data from the upstream pipe stage to the downstream pipe stage in response to a clock signal; controlling each pipe stage with a clock signal and a hold signal from the downstream pipe stage, holding the operation of the pipe stage until the hold signal is removed, and transferring the hold signal from the downstream pipe stage to the upstream pipe stage; Each upstream pipe stage hold signal is controlled by the clock signal, the logical sum of the hold signal from the downstream pipe stage and the busy signal from the upstream pipe stage is calculated, and the corresponding pipe stage hold signal is used to control each of the upstream pipes. A graphic data transfer method characterized by controlling first-in/first-out means of stages.