JPH01101671A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To allow high-frequency operation by providing sidewalls consisting of an insulator whose relative dielectric constant is small on the source and drain sides of a gate electrode. CONSTITUTION:A two-dimension electron gas layer 10 is formed on the interface between GaAs semiconductor layers 2, 4 and AlGaAs semiconductor layer 3, a depletion layer around a gate electrode 5 buried in the AlGaAs semiconductor layer 3 vertically extends by an applied operating voltage, whereby the carrier accumulation condition in the two-dimensional electron gas of the two layers is controlled at the same time. Accordingly, the buried gate electrode structure increases the amount of controllable currents, whereby high mutual conductance can be obtained. Silicon oxide sidewalls 11 whose relative dielectric constant is small and which are provided on the source and drain sides of the gate electrode 5 being the insulating sidewalls, which reduce both gate-source and gate-drain parasitic capacitances. According to the constitution, high-frequency characteristics and high speed switching characteristics of the field-effect transistor can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an A I GaAS/
A heterojunction device, typified by a field effect transistor with a GaA3 selectively doped structure, i.e., a HEMT (
The present invention relates to a semiconductor device having a two-dimensional electron gas layer as an active layer, such as a high-mobility transistor.

[Prior Art] Conventionally, in semiconductor devices such as HEMT, an undoped GaAS semiconductor layer and an impurity-doped AI GaAS semiconductor layer are used.
In order to utilize the two-dimensional electron gas layer formed at the hetero interface with the mixed crystal semiconductor layer as an active layer, the Ga
The two-dimensional electron gas layer of one layer or multiple layers is formed by growing the As semiconductor layer and the A I GaAs semiconductor layer alternately, and the single or multiple electron gas layers are embedded in each layer of the A I GaAs semiconductor layer. A structure was adopted in which traveling carriers in each of the two-dimensional electron gas layers were controlled by a gate electrode.

FIG. 3 shows an example of a structure in which a gate electrode is buried in a semiconductor layer in a conventional HEMT.

The gate electrode 35 is made of impurity-free GaAs layers 32, 3.
4 or the effect of embedding in the impurity-added AlGaAs layer 33 is, first, improvement of source resistance;
Second, the GaAs layer 32, 34 and the A I Ga
When a multilayer two-dimensional electron gas layer 40 is formed by growing As layers 33 alternately on the substrate 31, when operating the two-dimensional electron gas layer 40 as a channel,
A method of burying a single or multiple gate electrodes is considered to be effective.

[Problems to be Solved by the Invention] However, in the transistor of the conventional structure described above, by changing the width of the depletion layer generated on the side of each two-dimensional electron gas layer 40 of the gate electrode 35, the two-dimensional electron gas layer 40, the semiconductor on the drain side or the source side of the gate electrode 35 is essentially unnecessary, and it also acts as a parasitic capacitance between the source and the gate or between the drain and the gate. This causes a major drawback in high frequency characteristics or high speed switching characteristics.

The present invention was devised in view of the above-mentioned problems, and therefore provides a semiconductor device that can reduce the parasitic capacitance between the gate and the source or drain, and improves the high frequency characteristics or high speed switching characteristics of a field effect transistor. The purpose is to provide.

[Means for Solving the Problems] The present invention provides two-dimensional electrons formed along the hetero-interface between the semiconductor layers on the side of the semiconductor layer with the larger electron affinity between different semiconductor layers having different electron affinities. It has one or more gas layers, an alloy electrode for extracting the current flowing through the two-dimensional electron gas layer, and one or more gate electrodes embedded in the semiconductor layer. A semiconductor device characterized in that a side wall on a source side and a drain side of a gate electrode is formed of an insulator having a dielectric constant lower than that of the semiconductor layer.

In the present invention, an example of the insulator having a dielectric constant lower than that of the semiconductor layer is silicon dioxide.

[Function] The present invention provides a method for reducing the parasitic capacitance between the source and the gate or between the drain and the gate in a field effect transistor having a buried gate electrode with a two-dimensional electron gas layer as an operating layer. The high-frequency operation is achieved by providing side walls made of an insulator with a low relative dielectric constant on the side surface of the gate electrode on the source side and the side surface of the gate electrode on the drain side.

Conventionally, the parasitic capacitance on both the source and drain sides of the buried gate electrode was caused by the GaAs layer or AIGaAS layer in contact with the gate electrode and was a non-negligible problem, but the present invention In a field effect transistor, an insulator with a low dielectric constant is used on the source side and train side sides of the gate electrode.
For example, since a silicon oxide film is disposed, the parasitic capacitance is significantly improved compared to the conventional case. The relative permittivity of GaAS and A I GaAs is 12.5 to 13.0, but the relative permittivity of 5i02 is 3.5 to 4.0, which is approximately 173 or less compared to that of GaAs and A I GaAs. This greatly contributes to improving the high-frequency characteristics of field-effect transistors.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a longitudinal sectional view showing an embodiment of a field effect transistor according to the present invention. In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 and 4 are undoped GaAs semiconductor layers, 3 is an impurity-doped AI GaAs semiconductor layer, 5 is a gate electrode, 6 is a source electrode, 7 is a source region, 8 9 is a drain electrode, 9 is a train region, 10 is a two-dimensional electron gas layer, and 11 is a 5i02 side wall. The field effect transistor shown in this example basically consists of two layers of undoped Ga.
AIGa doped with impurities between As semiconductor layers 2 and 4
The A I GaAS semiconductor layer 3 sandwiching the AS semiconductor layer 3
It has a structure in which a gate electrode 5 is embedded. In this structure, two GaAS semiconductor layers 2 and 4 and an A I G
A two-dimensional electron gas layer 10 is formed at the interface with the aAS semiconductor layer 3. The depletion layer around the gate electrode 5 embedded in the A I GaAs semiconductor layer 3 expands in the vertical direction due to the operating voltage, and simultaneously controls the carrier accumulation state of the two two-dimensional electron gas layer 10 . Therefore, this buried gate electrode structure can improve the amount of current that can be controlled compared to conventional HEMTs, and can also obtain high mutual conductance. The side walls 11 of the silicon oxide film provided on the source and drain sides of the gate electrode 5 shown in FIG. 1 are the insulator side walls of the present invention.
1 reduces the parasitic capacitance N between the gate and source and the parasitic capacitance between the gate and train, improving the high frequency characteristics and high speed switching characteristics of the field effect transistor.

Next, an example of the manufacturing process of the buried gate electrode having the sidewalls will be explained with reference to FIGS. 2(a) to 2(d).

Each figure shows impurity-free GaAs grown on a semi-insulating GaAs substrate 21 by, for example, an organometallic chemical deposition method.
A case will be described in which a gate electrode 23 is buried in a semiconductor layer or an impurity-doped AI GaAs semiconductor layer 22. A metal or metal compound such as tungsten silicide is used as the material for the gate electrode 23, and is deposited to a thickness of 400 mm by sputtering, electron beam evaporation, or CVD as shown in FIG. The gate electrode 23 is formed by a method or a lift-off method so that the metal width is 5,000 mm or less.

This metal width corresponds to the gate length.

After forming the gate electrode 23, as shown in FIG.
Attach the body to about the same level as a person, and perform MIE (Magnetron Ion Etch) using a mixed gas of CF4 and SF6.
The upper surface of the gate electrode 23 and the GaA
The silicon oxide film 24 is etched until just before the surface of the s semiconductor layer or the A I GaAs semiconductor layer 22 appears. Thereafter, the silicon oxide film 24 is etched using a mixture of hydrogen peroxide and hydrofluoric acid until the surface is completely exposed.

As a result, as shown in FIG. 2(C), the gate electrode 23
Side walls 25 of silicon oxide film 24 are formed on both sides of the silicon oxide film 24 .

Thereafter, the GaAs semiconductor layer or the AlGaAs semiconductor layer 22 is grown again by the organometallic chemical deposition method in the same manner as before forming the gate electrode. The effectiveness and reproducibility of metal-organic chemical deposition methods for selective growth is ', e.g. 19
It was reported by Nakamura et al. at the 45th Annual Meeting of Japan Society of Applied Physics 14a-J-7 in 1984, and regarding buried growth of metal gate electrodes, Carl ,0. Boz
It has been reported in detail by ler et al. Gate electrode 2
As material No. 3, tungsten has been shown to be effective as it is sufficiently inert to GaAs and other products used during the epitaxial growth process. However, for the gate electrode 23, low-resistance GaAs doped with p-type impurities at a high concentration may be used instead of metal or its compound.

Through the above steps, GaAs semiconductor layer or AIGaA
The operation of embedding the gate electrode 23 in the S semiconductor layer 22 sandwiched between the silicon oxide films 24 is shown in FIG. 2(d).
Complete with a shape like this.

Although we have shown an example using the GaAs/A I GaAs crystal system, there are also cases where the InAlAs I
The present invention can also be practiced with nAlAs systems, InP/InGaAS systems, and the like. Furthermore, although the embodiments of the present invention have been explained using specific values, this is for ease of understanding; for example, if the amount of deposited gate electrode increases, the amount of silicon oxide film sidewalls also increases proportionally. Needless to say, the gate-to-source and gate-to-source
The amount may be sufficient as long as it sufficiently reduces the parasitic capacitance between the drains. Furthermore, the material used for the sidewalls is not limited to silicon oxide as long as it is an insulator with a dielectric constant lower than that of the respective semiconductors used.

[Effects of the Invention] As described above, according to the present invention, in a field effect transistor that uses a two-dimensional electron gas layer as a channel and controls it by a gate electrode embedded in a semiconductor layer, By providing sidewalls made of an insulator with a low dielectric constant on the source side and drain side, the capacitance between the gate and source and the parasitic capacitance between the gate and drain are reduced. Therefore, it is possible to provide a semiconductor device with improved high frequency characteristics or high speed switching characteristics of a field effect transistor.

[Brief explanation of the drawing]

FIG. 1 is a vertical sectional view showing one embodiment of the present invention, and FIG.
) to (d) are explanatory diagrams of the manufacturing process of an embodiment of the present invention, and FIG. 3 is a longitudinal sectional view of a conventional example. 1, 21.31 ... Semi-insulating GaAs substrate 2, 4
．． 32.34... Impurity-free GaAs semiconductor layer 3.
33... Impurity-doped AIGaAS semiconductor layer 5, 23,
35. ...Gate electrode 6.36...Source electrode 7,37...Source region 8.38...Drain electrode 9,39...Drain region 10, 40...Two-dimensional electron gas layer

Claims (2)

[Claims] (1) between different semiconductor layers having different electron affinities, one or more two-dimensional electron gas layers formed along the hetero interface between the semiconductor layers on the side of the semiconductor layer having a large electron affinity; an alloy electrode for extracting a current flowing through the two-dimensional electron gas layer, and a semiconductor layer embedded in the semiconductor layer.
In a semiconductor device comprising one or more gate electrodes, a side wall formed of an insulator having a dielectric constant lower than that of the semiconductor layer is provided on a side surface on the source side and a side surface on the drain side of the gate electrode. A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein the insulator having a dielectric constant lower than that of the semiconductor layer is silicon dioxide.