JPH098862A - Driver circuit, receiver circuit and signal transmission circuit - Google Patents

Abstract

(57) [Abstract] [Object] To simultaneously realize low power consumption, a small area, and high noise resistance. A signal transmission circuit 100 includes a signal wiring 1, a driver circuit 2 that drives the signal wiring 1, and a receiver circuit 3 that receives a signal transmitted through the signal wiring 1. The driver circuit 2 includes one of a first output portion that outputs a reference potential to the signal line 1 in the first period and a first information potential or a second information potential in accordance with an input signal in the second period. And a second output section for outputting one of them to the signal wiring 1. The receiver circuit 3 includes a signal wiring 6 having a predetermined capacitance, a signal wiring 7 having a predetermined capacitance,
The control units 31 and 32 connect the signal wiring 1 and the signal wiring 6 in the third period and connect the signal wiring 1 and the signal wiring 7 in the fourth period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit for driving a signal wiring, a receiver circuit for receiving a signal transmitted via the signal wiring, and a signal transmission circuit including the driver circuit and the receiver circuit.

[0002]

2. Description of the Related Art In recent years, the scale and speed of semiconductor integrated circuits have increased, and it has become necessary to drive long-distance signal wiring at high speed.

1A to 1C show the configuration of a conventional signal transmission circuit. The signal transmission circuit includes a signal wiring 201, a driver circuit 202, and a receiver circuit 203.

The driver circuit 202 drives the signal wiring 201 according to the signal input to the signal transmission circuit and changes the potential of the signal wiring 201. When the potential change of the signal wiring 201 reaches the terminal, the receiver circuit 203 outputs a signal according to the potential of the terminal of the signal wiring 201. When the wiring distance of the signal wiring 201 is long and the load capacitance related to signal transmission is large, the power consumption generated by charging and discharging this load capacitance becomes large, and since it takes an extra time to charge and discharge, signal transmission The speed will also slow down.

In the signal transmission circuit shown in FIG. 1 (b),
The driver circuit 202 converts the input signal into a signal having a small amplitude, and the signal having such a small amplitude is transmitted through the signal wiring 201. The transmitted signal is returned to its original amplitude by the receiver circuit 203.

In the signal transmission circuit shown in FIG. 1B,
The amplitude of the signal passing through the signal wiring 201 is smaller than that of the signal transmission circuit shown in FIG. Therefore, FIG.
The signal transmission circuit shown in (b) reduces power consumption as compared with the signal transmission circuit shown in FIG.

However, the signal transmission circuit shown in FIG. 1B has a low noise resistance because the signal amplitude is small. Therefore, it is difficult to reduce the amplitude of the transmitted signal so as to obtain a sufficient power consumption reduction effect.

In the signal transmission circuit shown in FIG. 1 (c),
A complementary signal corresponding to an input signal is transmitted to the two signal wirings 201 and 201 ′. The two signal wirings 201 and 201 ′ are arranged adjacent to or immediately adjacent to each other. As a result, the noises received by the two signal wirings 201 and 201 ′ become substantially the same, and the potential difference between the complementary signals is maintained. Like this, 2
By transmitting complementary signals using the signal wirings 201 and 201 ′ of the book, the potential difference between the signal wirings 201 and 201 ′ is transmitted from the driver circuit 202 to the receiver circuit 203 even when the amplitude for driving the signal wiring is small. be able to. This makes it possible to reduce the power consumption required to drive the signal wiring.

However, the signal transmission circuit shown in FIG. 1C requires two signal wirings to transmit one signal. This increases the layout area required for the signal wiring.

[0010]

Table 1 shows the three viewpoints of power consumption, layout area, and noise immunity.
It is an evaluation of the signal transmission circuits shown in (a) to (c). In Table 1, “◯” indicates that the method is superior to the other methods, and “X” indicates that the method is inferior to the other methods.

[0011]

[Table 1]

As shown in Table 1, the conventional signal transmission circuit cannot simultaneously realize the three characteristics of low power consumption, small layout area, and high noise resistance.

An object of the present invention is to reduce power consumption,
It is an object of the present invention to provide a driver circuit, a receiver circuit, and a signal transmission circuit that can simultaneously realize the three characteristics of a small layout area and high noise resistance.

[0014]

A driver circuit according to the present invention is a driver circuit for driving a signal wiring, which comprises a first output section for outputting a reference potential to the signal wiring in a first period, and a second output section. The second output section for outputting one of the first information potential and the second information potential to the signal wiring in accordance with the input signal during It

The first period and the second period may be alternately repeated.

Each of the first output section and the second output section may be controlled by a clock signal.

A receiver circuit of the present invention is a receiver circuit that receives a signal transmitted through a first signal line, and has a second signal line having a predetermined capacity and a third signal line having a predetermined capacity. Signal wiring and the first in the first period
And a control unit that connects the second signal wiring to the second signal wiring and connects the first signal wiring to the third signal wiring during the second period. To be achieved.

The control unit connects the first signal wire and the second signal wire with a first switch and connects the first signal wire with the third signal wire with a second switch. The switch may be provided, and the first switch and the second switch may be controlled by a clock signal.

The clock signal may be synchronized with the signal transmitted via the first signal wiring.

The receiver circuit may further include an amplifier for amplifying a potential difference between the potential of the second signal wiring and the potential of the third signal wiring.

The amplifier may include a holding circuit that holds the output of the amplifier.

Another receiver circuit of the present invention is a receiver circuit that receives a signal transmitted through a first signal wiring, and the receiver circuit includes a second signal wiring and a third signal wiring. A delay circuit that delays the potential of the signal transmitted through the first signal wiring by a predetermined delay time and transmits the delayed signal to the third signal wiring, and the second signal wiring is , The third signal wiring is directly connected to the first signal wiring, and the third signal wiring is connected to the first signal wiring via the delay circuit. This achieves the above object.

The receiver circuit may further include an adjusting circuit for adjusting the delay period according to a clock signal.

The receiver circuit may further include an amplifier for amplifying a potential difference between the potential of the second signal wiring and the potential of the third signal wiring.

The amplifier may include a holding circuit that holds the output of the amplifier.

The signal transmission circuit of the present invention comprises a first signal wiring, a driver circuit for driving the first signal wiring, and a receiver circuit for receiving a signal transmitted through the first signal wiring. A signal transmission circuit including: a first output portion that outputs a reference potential to the first signal line during a first period; and a first output portion that responds to an input signal during a second period. And a second output section for outputting one of the second information potential and the second information potential to the first signal wiring, and the receiver circuit has a second signal wiring having a predetermined capacitance. A third signal wiring having a predetermined capacitance, the first signal wiring and the second signal wiring are connected in a third period, and the first signal wiring and the second signal wiring are connected in a fourth period. And a control unit for connecting to the third signal wiring. This achieves the above object.

The signal transmitted via the first signal line may be synchronized with the timing at which the third period and the fourth period are switched.

Another signal transmission circuit of the present invention comprises a first signal wiring, a driver circuit for driving the first signal wiring,
A signal transmission circuit including a receiver circuit that receives a signal transmitted through the first signal wiring, wherein the driver circuit is configured to select one of a first information potential and a second information potential according to an input signal. One is output to the first signal line, and the receiver circuit includes a second signal line having a predetermined capacitance, a third signal line having a predetermined capacitance, and the first signal line in the first period. And a control unit that connects the second signal wiring to the second signal wiring and connects the first signal wiring to the third signal wiring during the second period. To be achieved.

The signal transmitted via the first signal line may be synchronized with the timing at which the first period and the second period are switched.

Another signal transmission circuit of the present invention comprises a first signal wiring, a driver circuit for driving the first signal wiring,
A signal transmission circuit including a receiver circuit that receives a signal transmitted through the first signal wiring, wherein the driver circuit outputs a reference potential to the first signal wiring during a first period. A first output part and a second output part for outputting either one of the first information potential and the second information potential to the first signal wiring in accordance with the input signal in the second period. The receiver circuit includes the second signal wiring, the third signal wiring, and the potential of the signal transmitted via the first signal wiring by delaying the potential of the signal by a predetermined delay time. And a delay circuit for transmitting the signal to the signal wiring of No. 3, the second signal wiring is directly connected to the first signal wiring,
The third signal wiring is connected to the first signal wiring via the delay circuit. This achieves the above object.

Another signal transmission circuit of the present invention comprises a first signal wiring, a driver circuit for driving the first signal wiring,
A signal transmission circuit including a receiver circuit that receives a signal transmitted through the first signal wiring, wherein the driver circuit is configured to select one of a first information potential and a second information potential according to an input signal. One of the signals is output to the first signal wiring, and the receiver circuit sets a predetermined potential of the signal transmitted through the second signal wiring, the third signal wiring, and the first signal wiring. And a delay circuit for transmitting the signal to the third signal line after delaying the delay time of the first signal line.
Is directly connected to the first signal wiring, and the third signal wiring is connected to the first signal wiring via the delay circuit. This achieves the above object.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 shows a configuration of a signal transmission circuit 100 according to the present invention. Signal transmission circuit 100
Is a signal wiring 1, a driver circuit 2, and a receiver circuit 3.
And

Input signal IN representing full level data
Are input to the driver circuit 2. The driver circuit 2 is
The input signal IN is converted into a signal having a small amplitude, and the converted signal is transmitted to the receiver circuit 3 via the signal wiring 1. The level of the signal transmitted from the driver circuit 2 to the receiver circuit 3 changes according to the level of the input signal IN.

The receiver circuit 3 receives the signal transmitted from the driver circuit 2 via the signal wiring 1, and the received signal is an output signal OUT representing full level data.
Converted to and output. The level of the output signal OUT changes according to the level of the signal transmitted from the driver circuit 2 to the receiver circuit 3.

The receiver circuit 3 includes a signal decomposition circuit 4 and an amplifier 5.

The signal transmitted from the driver circuit 2 to the receiver circuit 3 is temporally divided by the signal decomposition circuit 4 and sent to the signal wirings 6 and 7. For example, when the driver circuit 2 generates a signal that alternately repeats the reference potential and the information potential according to the input signal IN, the signal decomposition circuit 4 decomposes the signal at the reference potential of the signal and the information. It is set so as to be synchronized with the timing at which the potential changes. As a result, the reference potential can be transmitted to the signal wiring 6 and the information potential can be transmitted to the signal wiring 7. The minute potential difference between the reference potential appearing on the signal wiring 6 and the information potential appearing on the signal wiring 7 is amplified to full level data by the amplifier 5. In this way, full level data is transmitted to the next stage. This means that the reference potential and the information potential (that is, complementary data having a small potential amplitude) can be transmitted by one signal wiring.

Hereinafter, the element circuits included in the signal transmission circuit 100 according to the present invention will be described in detail with reference to the drawings.

FIG. 3A shows the configuration of the driver circuit 2 in the signal transmission circuit 100. The driver circuit 2 includes a clocked inverter 20 controlled by the clock CLK1 and a transistor 21 for transmitting the reference potential Vref to the output node D0 of the driver circuit 2. Voltages Vh and Vl are supplied to the power source of the clocked inverter 20, and the potential difference between the voltage Vh and the voltage Vl is set to be sufficiently small.

The driver circuit 2 outputs either one of the voltage Vh and the voltage Vl according to the input signal IN when the clock CLK1 is at the low level. When the clock CLK1 goes from low level to high level, the output of the clocked inverter 20 goes into a high impedance state and the transistor 21 goes into an on state. As a result, the reference potential Vref is supplied to the output node D0 of the driver circuit 2.

FIG. 3B shows the waveforms of the clock CLK1 and the input signal IN input to the driver circuit 2 and the waveform of the signal at the output node D0 of the driver circuit 2. Hereinafter, the signal at the output node D0 of the driver circuit 2 is referred to as the signal D0.

During the period when the input signal IN is at high level,
The clock CLK1 is set so as to include a period in which it is at a low level. In this way, the signal having the amplitude (Vh-Vl), which alternately repeats the reference potential and the information potential in synchronization with the clock CLK1, is output to the driver circuit 2.
Is output from the output node D0.

FIG. 4A shows another configuration of the driver circuit 2. The driver circuit 2 shown in FIG. 4A includes an inverter 22 to which voltages Vh and Vl are supplied as a power source.
And the output node IO of the inverter 22 and the driver circuit 2
Of the transistor 23 whose gate is controlled by the clock CLK1.
And the reference potential Vref to the output node D of the driver circuit 2.
And a transistor 24 transmitting to zero.

The inverter 22 outputs either the voltage Vh or the voltage Vl according to the input signal IN. When the clock CLK1 is at the high level, the output node IO of the inverter 22 and the output node D0 of the driver circuit 2 are electrically disconnected by the transistor 23. As a result, at the output node D0 of the driver circuit 2,
The reference potential Vref is output through the transistor 24. When the clock CLK1 transitions from the high level to the low level, the transistor 24 is turned off and the transistor 23 is turned on. As a result, the reference potential Vref is disconnected from the output node D0 of the driver circuit 2, and the output of the inverter 22 is transmitted to the output node D0 as the output of the driver circuit 2.

FIG. 4B shows the waveforms of the clock CLK1 and the input signal IN input to the driver circuit 2, the waveform of the signal at the output node IO of the inverter 22, and the waveform of the signal at the output node D0 of the driver circuit 2. Indicates.

While the input signal IN is at high level,
The clock CLK1 is set so as to include a period in which it is at a low level. In this way, the signal having the amplitude (Vh-Vl), which alternately repeats the reference potential and the information potential in synchronization with the clock CLK1, is output to the driver circuit 2.
Is output from the output node D0.

FIG. 5 shows the configuration of the receiver circuit 3 of the signal transmission circuit 100. The receiver circuit 3 is a signal decomposition circuit 4
And amplifier 5 are included. The signal decomposition circuit 4 is connected to the signal wiring 1 that transmits a signal at the output node D0 of the driver circuit 2.

The signal decomposition circuit 4 includes signal wirings 6 and 7.
And a switch 31 electrically connecting the signal wiring 1 and the signal wiring 6 and controlled by the clock CLK, and a switch electrically connecting the signal wiring 1 and the signal wiring 7 and controlled by an inverted signal of the clock CLK. 32 and 32 are included. Each of the switches 31 and 32 may be a MOS transistor. In FIG. 5, 8 indicates the capacitance of the signal wiring 1, 9 indicates the capacitance of the signal wiring 6, and 10 indicates the capacitance of the signal wiring 7.

FIG. 6 is a time chart showing the operation of the receiver circuit 3 shown in FIG. The operation of the receiver circuit 3 will be described below with reference to FIG. Here, the signal D0 sent through the signal line 1 has a reference potential in the first period and has an information potential which is high or low in the second period. The first period and the second period are alternately repeated.

The switches 31 and 32 have a clock CL.
It is controlled by K. One of the signal wirings 6 and 7 is connected to the signal wiring 1 according to the level of the clock CLK. The clock CLK is synchronized with the signal D0. For example, during the first period, the MOS transistor switch 32 is turned on and the signal wiring 7 is connected to the signal wiring 1. As a result, the potential D of the signal wiring 7
2 is the reference potential. During the second period, the MOS transistor switch 31 is turned on, and the signal wiring 6 becomes the signal wiring 1.
Connected to As a result, the potential D1 of the signal wiring 6 becomes the information potential which is high or low.

The potential D2 of the signal wiring 7 in the first period
(Reference potential) is the capacitance 10 of the signal wiring 7 in the second period.
Kept by. This is because the MOS transistor switch 32 is turned off in the second period. Similarly, the second
The potential D1 (information potential) of the signal wiring 6 in the period of
In the first period, it is maintained by the capacitance 9 of the signal wiring 6.
This is because the MOS transistor switch 31 is turned off in the first period.

As described above, the reference potential and the information potential, which are alternately sent through the signal line 1 with a time difference between the first period and the second period, are supplied to the signal line 6 and the signal line 7, respectively. It is transmitted at the same time. This means that the reference potential and the information potential (that is, complementary data) can be transmitted using only one signal wiring.

The shorter the length of the signal wiring 6 and the length of the signal wiring 7 than the length of the signal wiring 1, the smaller the layout area of the signal transmission circuit 100. However, MOS
The capacitance 9 of the signal wiring 6 and the capacitance 10 of the signal wiring 7 have a certain level of capacitance so that a stable potential can be held in the signal wiring 6 or 7 while the transistor switch 31 or 32 is off. It is preferable to have a value. Of course, it is also possible to increase the capacitance value of the signal wirings 6 and 7 by using the gate capacitance or the like while keeping the lengths of the signal wirings 6 and 7 short.

The signal D0 at the output node D0 of the driver circuit 2 and the MOS transistor switch 31,
It suffices that the clock CLK controlling 32 be synchronized, and the edge timing of the signal D0 and the edge timing of the clock CLK do not have to be the same. Signal wiring 6
And signal wiring 7 at the same time, as long as a potential difference of a certain level or more is obtained, the edge timing of signal D0 and clock C
It does not matter if the edge timing of LK deviates.
Of course, the larger the potential difference between the potential of the signal wiring 6 and the potential of the signal wiring 7, the better.

Next, the effects of the signal transmission circuit 100 according to the present invention will be described with reference to FIGS.

FIG. 7A shows the structure of the receiver circuit (simple inverter circuit) in the conventional signal transmission circuit shown in FIG. 1B. In the conventional signal transmission circuit shown in FIG. 1B, since the signal amplitude transmitted through the signal wiring is set to a small potential difference, the fluctuation of the signal potential due to noise from the outside is relative to the signal level. Grows to. Therefore, in the conventional receiver circuit shown in FIG. 7A, the noise level easily exceeds the logical threshold potential of the inverter circuit and malfunctions easily (see FIG. 7B).

On the other hand, in the receiver circuit 3 (FIG. 5) according to the present invention, since the MOS transistor 32 and the capacitor 10 are present in the signal transmission path from the signal wiring 1 to the signal wiring 7, transmission delay occurs. That is, even if noise is introduced during the transmission of the reference potential to the signal wiring 7, the MOS transistor 31 and the capacitor 9 function as a filter, so that the variation amount of the potential D2 held in the signal wiring 7 from the reference potential is It is smaller than the noise level (see FIG. 7 (c)).

Similarly, the influence of noise on the potential D1 appearing on the signal wiring 6 as the information potential is alleviated. Signal D
Even if noise is input to 0, if the potential D1 of the signal wiring 6 at the time of activation of the amplifier is on the information potential side of the potential D2 (reference potential) held in the signal wiring 7, the amplifier 5 corrects it. It is possible to output data (see FIG. 7 (c)). Therefore, according to the present invention,
Since the influence of noise is mitigated by the above-described filter effect, the margin for noise is expanded.

The noise margin described so far relates to the noise appearing on the signal wiring 1. The influence of noise appearing on the signal wiring 6 or 7 can be ignored. This is because the two signal wirings 6 and 7 can be arranged in the immediate vicinity, so that the potential fluctuation amounts due to noise are basically equal. Therefore, data is stored in the signal wirings 6 and 7 regardless of the noise level.

There is a correlation between the time when noise is input to the signal wiring 1 and the noise margin of the signal transmission circuit 100. If noise enters immediately before the MOS transistor 32 transitions to the off state, the potential D2 held in the signal wiring 7 largely deviates from the reference potential. In addition, if noise enters immediately before the amplifier 5 is activated, the deviation of the potential D1 appearing on the signal wiring 6 from the information potential also increases.
Therefore, when the timing of noise generation is synchronized with the signal transmission, the influence of noise is influenced by changing the timing of transitioning the MOS transistor 32 from on to off or the timing of activating the amplifier 5. It can be further mitigated.

Thus, the signal transmission circuit 1 according to the present invention
00 has an advantage that noise resistance is high and a noise margin can be secured. Further, since the reference potential and the signal potential (that is, complementary data) can be transmitted using only one signal wiring, there is an advantage that the layout area of the signal transmission circuit 100 can be reduced. Furthermore, since the amplitude of the signal transmitted through one signal wiring is small, the signal transmission circuit 1
00 has the advantage of low power consumption.

As described above, the signal transmission circuit 100 according to the present invention has three characteristics of low power consumption, small layout area, and high noise resistance at the same time. It is superior to the conventional signal transmission circuits shown in a) to (c) (see Table 1).

(Second Embodiment) FIG. 8 shows a configuration of a signal transmission circuit 110 according to the present invention. Signal transmission circuit 110
Includes a signal wiring 1, a driver circuit 12, and a receiver circuit 3. The same components as those of the signal transmission circuit 100 shown in FIG. 2 are designated by the same reference numerals.

FIG. 9A shows the configuration of the driver circuit 12 of the signal transmission circuit 110. In the driver circuit 12, the voltage Vh is connected to the high potential power source side and the voltage Vh is connected to the low potential power source side.
It has an inverter to which l is connected. The driver circuit 12 converts the amplitude of the input signal IN into (Vh-Vl) and outputs it. Of course, the power supply potential V supplied to the chip
The values of the voltages Vh and Vl are set so that the value of (Vh-Vl) is smaller than the potential difference between cc and the ground potential Vss. With this configuration, the driver circuit 12 transfers a small amplitude signal in which the information potential is continuous to the receiver circuit 3.

FIG. 9B shows the waveform of the input signal IN input to the driver circuit 12 and the waveform of the signal at the output node D0 of the driver circuit 12.

The structure of the receiver circuit 3 is as shown in FIG. The receiver circuit 3 receives a signal having a small amplitude via one signal line and converts the signal into a full-level signal. The signal so transformed is
It is transmitted as data to the circuit in the next stage.

FIG. 10 is a time chart showing the operation of the receiver circuit 3. The operation of the receiver circuit 3 will be described below with reference to FIG.

The signal at the output node D0 of the driver 12 is a signal having a continuous information potential. That is, the signal D0 has an information potential which is high or low in one cycle.

The clock CLK is input to the signal decomposition circuit 4 (FIG. 5). The clock CLK is synchronized with the signal D0 that is doubled. The clock CLK alternately repeats the first period and the second period.

The signal D0 in the first period is taken into the signal decomposition circuit 4 as the information potential D1 by the clock CLK. As a result, the information potential D1 appears on the signal wiring 6 (FIG. 5). The information potential D1 is held in the signal wiring 6 during the second period following the first period. The signal D0 in the second period is taken into the signal decomposition circuit 4 as the information potential D2 by the clock CLK. as a result,
The information potential D2 appears on the signal wiring 7 (FIG. 5). The information potential D2 is held in the signal wiring 7 during the first period following the second period.

The operation of the receiver circuit 3 when the potential of the signal D0 in the previous cycle and the potential of the signal D0 in the current cycle are different will be described below. Assume that the signal D0 in the previous cycle is high (Vh) and the signal D0 in the current cycle is low (Vl). In this case, the signal D0 (high) in the second period of the previous cycle
Is taken into the signal decomposition circuit 4 as the information potential D2, and the information potential (high) is held in the signal wiring 7 during the first period of the current cycle. The signal D0 (low) in the first period of the current cycle is used as the information potential D1 in the signal decomposition circuit 4
Is taken into.

The differential amplifier 5 (FIG. 5) amplifies the potential difference between the information potential D1 and the information potential D2 in the first period of the current cycle, and thereby the information potential D2 in the second period of the previous cycle. Is used as a reference potential to determine whether the information potential D1 in the first period of the current cycle is higher or lower than the reference potential. The differential amplifier 5 outputs the output signal OUT according to the determination result.

In this way, the data corresponding to the signal D0 in the current cycle is output from the receiver circuit 3.

However, when the potential of the signal D0 in the previous cycle and the potential of the signal D0 in the current cycle are equal, the information potential D1 in the first period of the current cycle.
And the information potential D2 become equal. Therefore, in this case, the information potential D in the first period of the current cycle is
By amplifying the potential difference between 1 and the information potential D2,
The data corresponding to the signal D0 in the current cycle cannot be specified. Such a problem is solved by using an amplifier having a latch function.

FIG. 11A shows the structure of the differential amplifier 15 having a latch function. The differential amplifier 15 is connected to the signal wirings 6 and 7 of the signal decomposition circuit 4, respectively. The information potential D1 appears on the signal line 6, and the information potential D2 appears on the signal line 7.

When the potential difference between the information potential D1 and the information potential D2 becomes a predetermined potential difference or more, the differential amplifier 15 latches the amplification result in a static differential amplifier which automatically amplifies the potential difference. It is a function added.

The differential amplifier 15 includes PMOS transistors 37 and 38 which are current sources of the differential amplifier 15, NMOS transistors 39 and 40 which serve as input transistors, and NMOS transistors 41 and 42 which latch the output of the differential amplifier 15. Includes and. The gate of the input transistor 39 is connected to the signal wiring 6, and the gate of the input transistor 40 is connected to the signal wiring 7.

11B and 11C show the differential amplifier 1
6 is a time chart showing the operation of FIG.

FIG. 11B shows the operation of the differential amplifier 15 when the potential of the signal D0 always changes in each cycle (for example, when the signal D0 is a clock signal).

In this case, in the first period of each cycle,
A potential difference corresponding to data appears between the information potential D1 and the information potential D2. Therefore, the differential amplifier 15 operates normally by amplifying the potential difference between the information potential D1 and the information potential D2 in the first period of each cycle.
That is, the differential amplifier 15 outputs the output signal OUT corresponding to the signal D0.

FIG. 11C shows the operation of the differential amplifier 15 when the potential of the signal D0 in the first cycle and the potential of the signal D0 in the second cycle following the first cycle are equal.

In this case, the potential difference between the information potential D1 and the information potential D2 is zero in the second cycle, and the differential amplifier 15 is in the self-equalizing state.
In this state, the normal differential amplifier does not operate normally. However, as described above, the differential amplifier 15 having the latch function has the function of holding the data determined in the previous cycle as it is in the current cycle. As a result, even when the potential of the signal D0 of the current cycle does not change from the potential of the signal D0 of the previous cycle and no potential difference occurs between the information potential D1 and the information potential D2,
The differential amplifier 15 can output the output signal OUT according to the signal D0.

The operation of the differential amplifier 15 will be specifically described below.

The constant currents from the PMOS transistors 37 and 38, which are current sources, flow through the NMOS transistors 39 and 40. The gate of the NMOS transistor 39 is supplied with the information potential D1, and the gate of the NMOS transistor 40 is supplied with the information potential D2. When a potential difference occurs between the information potential D1 and the information potential D2, the impedance of the NMOS transistor 39 and N
A difference occurs with the impedance of the MOS transistor 40. This causes a difference between the amount of voltage drop due to the NMOS transistor 39 and the amount of voltage drop due to the NMOS transistor 40. This voltage difference is the output voltage OU
Appears as a difference between T and the output voltage / OUT.

The output voltage OUT and the output voltage / OUT are input to the NMOS transistors 41 and 42 connected to the cross couple, respectively. That is, the output voltage / OUT is input to the gate of the NMOS transistor 41, and the output voltage OUT is input to the gate of the NMOS transistor 42.

For example, as shown in FIG. 11C, the first
If the signal D0 is low throughout the cycle of 1 and the second cycle, the NMOS transistor 41 is off and the NMOS transistor 42 is on. There is no potential difference between the information potential D1 and the information potential D2, and the NMO
Even if there is no difference in the amount of current drawn between the S transistors 39 and 40, the difference between the amounts of drawn current in the NMOS transistors 41 and 42 causes the difference between the output voltage OUT and the output voltage / OU.
The potential difference with T is retained.

The polarities of the power supply and the MOS transistor in the differential amplifier 15 may be completely opposite to the polarities described above. Even in this case, the differential amplifier 15
It is possible to perform the same operation as that described above.

Further, in the example shown in FIG. 11A, the MOS transistors 41 and 42 for latching data are inserted in parallel with the MOS transistors 39 and 40 which receive the differential input. A MOS transistor for latching data may be inserted in series with a MOS transistor that receives a differential input.

The differential amplifier 15 shown in FIG. 11 (a) is not suitable for dynamic operation by controlling the power supply. If the power consumption of the differential amplifier 15 is reduced by turning off the power, the output voltage OU
This is because T and / OUT become undefined, and the latched data is also erased.

To solve this problem, a latch circuit for latching the output voltages OUT and / OUT of the differential amplifier is provided independently of the differential amplifier, and the output of this latch circuit is fed back to the differential amplifier. Good. This enables the dynamic operation of the differential amplifier.

FIG. 12A shows the configuration of the differential amplifier 16 and the latch circuit 55 which can be operated dynamically. The configuration of the differential amplifier 16 is an NMO for dynamic operation.
The configuration is the same as that of the differential amplifier 15 except that S transistors 53 and 54 are added.

The NMOS transistor 53 is inserted between the current source of the differential amplifier 16 and the power supply line. NMO
The S transistor 54 is inserted between the source node and the ground line.

The activation signal / SAE is input to the gate of the NMOS transistor 53. The activation signal SAE is input to the gate of the NMOS transistor 54.

When the activation signal SAE becomes high level,
Both the NMOS transistors 53 and 54 are turned on. As a result, the differential amplifier 16 is activated. The differential amplifier 16 outputs the output voltages OUT and / OUT according to the potential difference between the information potential D1 and the information potential D2 (see FIG. 12B).

When the activation signal SAE transits from the high level to the low level, the MOS transistors 53 and 54.
Changes from the on state to the off state. In this case, the output data is held by the latch circuit 55. as a result,
The potentials of the gates of MOS transistors 41 and 42 are fixed. Therefore, in the second cycle, the MOS
Even if the transistors 53 and 54 are turned on again and no potential difference is generated between the information potential D1 and the information potential D2, the differential amplifier 16 operates in the MOS transistor 41.
Correct data is output according to the potential difference between the gates of and 42 (see FIG. 12C).

The MOS transistors 41 and 42
Without the differential amplifier 15 (or differential amplifier 16)
Can basically output the data corresponding to the signal D0. However, considering that the MOS transistor has a larger current difference in the gate potential difference than the drain potential difference and the offset voltage of the differential amplifier by the MOS transistors 39 and 40, the MOS transistors 41 and 42 are provided. Preferably.

Further, in the present embodiment, it has been described that when a signal having a small amplitude in which the information potential is continuous is transferred to the receiver circuit, a differential amplifier having a latch function can be applied to the receiver circuit. . For the same reason, when transferring a signal having a small amplitude in which the reference potential and the information potential are alternately repeated to the receiver circuit, the differential amplifier having the latch function can be applied to the receiver circuit.

(Third Embodiment) FIG. 13A shows the structure of a receiver circuit 13 according to the present invention. Receiver circuit 1
3 includes a signal decomposition circuit 14 that temporally divides the signal D0 transmitted through the signal wiring 1 and an amplifier 5 that amplifies the output of the signal decomposition circuit 14.

The signal decomposition circuit 14 includes a signal wiring 6, a signal wiring 7, and a delay circuit 60. The signal wiring 1 branches into a signal wiring 6 and a signal wiring 7 in the signal decomposition circuit 14. The signal wiring 6 is directly connected to the signal wiring 1, and the signal wiring 7 is connected to the signal wiring 1 via the delay circuit 60. The delay circuit 60 delays the signal D0 from the signal wiring 1 and transmits the delayed signal D0 to the signal wiring 7. The delay circuit 60 includes, for example, a resistor 63 and a capacitor 64.
And In FIG. 13, 8 indicates the capacitance of the signal wiring 1.

The receiver circuit 13 operates normally when it receives the signal D0 in which the reference potential and the information potential are alternately repeated via the signal wiring 1 (see FIG. 13B). Further, the receiver circuit 13 outputs the signal D0 in which the information potential is continuous.
Even when the signal is received via the signal wiring 1, it operates normally (see FIG. 13C). The signal D0 in which the reference potential and the information potential are alternately repeated is generated by the driver circuit 2 shown in FIG. 3A (or FIG. 4A), for example. A signal D0 having a continuous information potential is, for example, as shown in FIG.
It is generated by the driver circuit 12 shown in FIG.

The operation of the receiver circuit 13 will be described below.

When the potential of the signal D0 changes from high to low (or from low to high), the potential D1 of the signal wiring 6
Changes from high to low (or from low to high) almost at the same time as the potential of the signal D0. On the other hand, the potential D2 of the signal wiring 7 transits from high to low (or from low to high) after a delay of a predetermined time by the delay circuit 60 from the time when the potential of the signal D0 transits. Therefore, for a while after the potential of the signal D0 changes, the signal wiring 6
A potential difference occurs between the potential D1 of the signal line D1 and the potential D2 of the signal line 7.

The differential amplifier 5 uses the potential D2 of the signal wiring 7 as a reference potential, and the potential D of the signal wiring 6 from the reference potential.
Determine if 1 is high or low. The differential amplifier 5 outputs the output signal OUT according to the determination result. As a result, the data corresponding to the signal D0 can be transmitted.

In the example shown in FIG. 13A, the delay circuit 60 includes the resistor 63 and the capacitor 64. However, the configuration of the delay circuit 60 is not limited to this. As long as it has the function of delaying the transmission of signals,
The delay circuit 60 may have any configuration.

The use of the receiver circuit 13 is especially effective when transmitting a clock signal. This is because the receiver circuit 13 does not need the clock CLK as shown in FIG. This means
It eliminates the contradiction of requiring the clock CLK to transmit the clock signal.

Signal decomposition circuit 1 in receiver circuit 13
According to 4, the accuracy of signal transmission is improved as the phase difference between the information potential D1 and the information potential D2 (the period in which the potential difference is held) is larger. However, if the phase difference is too large, the information potential D1 and the information potential D will be increased before the next cycle starts.
The self-equalization of 2 does not end. As a result, the signal decomposition circuit 14 may malfunction.

Delay time in the signal decomposition circuit 14 (that is, the phase difference between the information potential D1 and the information potential D2)
Is constant regardless of the operating frequency. Therefore, if the operating frequency is extremely faster or slower than the set operating frequency, signal transmission cannot be performed accurately.

FIG. 14A shows the configuration of a signal decomposition circuit 14 'which is an improvement of the signal decomposition circuit 14. Signal decomposition circuit 1
4'is for solving the above-mentioned subject.

The signal decomposition circuit 14 'includes a delay circuit 70 for delaying the signal D0 from the signal wiring 1 and an external clock C.
An adjusting circuit 76 for adjusting the delay time of the delay circuit 70 according to the frequency of LK is included.

The adjusting circuit 76 is used for adjusting the operating speed according to the frequency of the external clock CLK. As the adjusting circuit 76, for example, a VCO circuit that changes the output voltage according to the frequency of the external clock CLK is used. The VCO circuit may be one generally used in a PLL circuit or the like. In the following description, the adjustment circuit 76 is V
It is assumed that the circuit is a CO circuit.

The delay circuit 70 includes a capacitor 74 and an NMOS transistor 75. NMOS transistor 7
The output voltage of the VCO circuit 76 is input to the gate of 5. When the VCO circuit 76 is configured such that the higher the frequency of the clock CLK, the higher the output voltage,
The higher the frequency of the clock CLK, the higher the gate voltage Vg of the NMOS transistor 75. As a result, NMO
The resistance of the channel of the S transistor 75 becomes low. That is, as the frequency of the clock CLK is higher, the delay circuit 7
At 0, the resistance component that causes the delay becomes small. As a result, the phase difference between the information potential D1 and the information potential D2 becomes small.

FIG. 14B shows the operation of the signal decomposition circuit 14 'when the operation cycle is relatively long. FIG.
(C) shows the operation of the signal decomposition circuit 14 'when the operation cycle is relatively short. According to the signal decomposition circuit 14 ',
In either case, while the phase difference between the information potential D1 and the information potential D2 is sufficiently maintained, the potential of the information potential D2 sufficiently transitions by the end of one cycle and does not affect the next cycle. Can be level. This means that optimum signal decomposition according to the operating frequency is possible.

The resistance component of the delay circuit 70 is NMOS.
It is not limited to the on resistance of the transistor 75. The NMOS transistor 75 is used as the resistance component of the delay circuit 70.
An element having a resistance may be inserted in series or in parallel with.

In place of the NMOS transistor 75, an element whose resistance value and / or capacitance value changes according to the operating frequency is used as a component for adjusting the delay time of the delay circuit 70 according to the operating frequency. May be.

[0115]

The signal transmission circuit according to the present invention has the advantage of being highly resistant to noise and ensuring a noise margin. Further, since the reference potential and the signal potential (that is, complementary data) can be transmitted using only one signal wiring, there is an advantage that the layout area of the signal transmission circuit can be reduced. Further, since the amplitude of the signal transmitted through one signal wiring is small, there is an advantage that the power consumption of the signal transmission circuit is small.

As described above, the signal transmission circuit according to the present invention is more advantageous than the conventional signal transmission circuit in that it simultaneously realizes the three characteristics of low power consumption, small layout area, and high noise resistance. Are better.

[Brief description of drawings]

1A to 1C are diagrams showing a configuration of a conventional signal transmission circuit.

FIG. 2 is a diagram showing a configuration of a signal transmission circuit 100 according to the present invention.

3A is a diagram showing a configuration of a driver circuit 2 in the signal transmission circuit 100, and FIG. 3B is a diagram showing waveforms of signals in the driver circuit 2.

FIG. 4A is a diagram showing another configuration of the driver circuit 2,
(B) is a diagram showing a waveform of a signal in the driver circuit 2.

5 is a diagram showing a configuration of a receiver circuit 3 in the signal transmission circuit 100. FIG.

FIG. 6 is a time chart showing the operation of the receiver circuit 3.

FIG. 7A is a diagram showing a configuration of a conventional receiver circuit,
(B) is a time chart showing the operation of the conventional receiver circuit, and (c) is a time chart showing the operation of the receiver circuit 3.

FIG. 8 is a diagram showing a configuration of a signal transmission circuit 110 according to the present invention.

9A is a diagram showing a configuration of a driver circuit 12 in the signal transmission circuit 110, and FIG. 9B is a diagram showing waveforms of signals in the driver circuit 12.

FIG. 10 is a time chart showing the operation of the receiver circuit 3.

FIG. 11A is a differential amplifier 15 having a latch function.
Of the differential amplifier 15 shown in FIGS.
3 is a time chart showing the operation of FIG.

12A is a diagram showing a configuration of a differential amplifier 16 and a latch circuit 55 capable of dynamic operation, and FIGS. 12B and 12C are time charts showing the operation of the differential amplifier 16 and the latch circuit 55. is there.

13A is a diagram showing a configuration of a receiver circuit 13, FIG.
(B) and (c) are time charts showing the operation of the receiver circuit 13.

14A is a diagram showing a configuration of a signal decomposition circuit 14 ′, and FIGS. 14B and 14C are time charts showing the operation of the signal decomposition circuit 14 ′.

[Explanation of symbols]

 1 signal wiring 2 driver circuit 3 receiver circuit 4 signal decomposition circuit 5 amplifier 6 signal wiring 7 signal wiring 8 capacity 9 capacity 10 capacity 12 driver circuit 13 receiver circuit 14 signal decomposition circuit 14 'signal decomposition circuit 15 differential amplifier 16 differential amplifier 31 switch 32 switch 100 signal transmission circuit 110 signal transmission circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisakazu Otani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Akira Matsuzawa, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Shoichiro Tada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (18)

[Claims] 1. A driver circuit for driving a signal line, comprising: a first output section that outputs a reference potential to the signal line during a first period; and a first output section that responds to an input signal during a second period. And a second output portion for outputting one of the second information potential and the second information potential to the signal wiring. 2. The driver circuit according to claim 1, wherein the first period and the second period are alternately repeated. 3. The driver circuit according to claim 1, wherein each of the first output section and the second output section is controlled by a clock signal. 4. A receiver circuit for receiving a signal transmitted through a first signal wire, comprising: a second signal wire having a predetermined capacity; a third signal wire having a predetermined capacity; And a control unit that connects the first signal wiring and the second signal wiring in the first period and connects the first signal wiring and the third signal wiring in the second period. Receiver circuit. 5. The control unit connects a first switch that connects the first signal wire and the second signal wire, and connects the first signal wire and the third signal wire. A second switch, the first switch and the second switch being controlled by a clock signal,
The receiver circuit according to claim 4. 6. The receiver circuit according to claim 5, wherein the clock signal is synchronized with the signal transmitted via the first signal line. 7. The receiver circuit further includes an amplifier that amplifies a potential difference between a potential of the second signal wiring and a potential of the third signal wiring.
The receiver circuit according to claim 4. 8. The receiver circuit according to claim 7, wherein the amplifier includes a holding circuit that holds an output of the amplifier. 9. A receiver circuit for receiving a signal transmitted through a first signal wire, the receiver circuit comprising a second signal wire, a third signal wire, and the first signal wire. A delay circuit for delaying the potential of the signal transmitted through the third signal line by a predetermined delay time, and transmitting the potential to the third signal line, wherein the second signal line is the first signal line. The receiver circuit is directly connected to the third signal line, and the third signal line is connected to the first signal line via the delay circuit. 10. The receiver circuit according to claim 9, wherein the receiver circuit further includes an adjustment circuit that adjusts the delay period according to a clock signal. 11. The receiver circuit further includes an amplifier that amplifies a potential difference between a potential of the second signal wiring and a potential of the third signal wiring.
The receiver circuit according to claim 9. 12. The receiver circuit according to claim 11, wherein the amplifier includes a holding circuit that holds an output of the amplifier. 13. A signal transmission circuit comprising: a first signal wiring; a driver circuit for driving the first signal wiring; and a receiver circuit for receiving a signal transmitted through the first signal wiring. In the first period, the driver circuit outputs the reference potential to the first signal line, and in the second period, the driver circuit outputs the first information potential and the second information potential according to the input signal. And a second output section for outputting one of the information potentials to the first signal wiring, and the receiver circuit has a second signal wiring having a predetermined capacitance and a second capacitance having a predetermined capacitance. The third signal wiring which it has, the first signal wiring and the second signal wiring are connected in the third period, and the first signal wiring and the third signal wiring are connected in the fourth period. And a control unit for connecting
Signal transmission circuit. 14. The signal transmission circuit according to claim 13, wherein the signal transmitted via the first signal line is synchronized with a timing at which the third period and the fourth period are switched. 15. A signal transmission circuit including a first signal wiring, a driver circuit for driving the first signal wiring, and a receiver circuit for receiving a signal transmitted through the first signal wiring. The driver circuit outputs one of the first information potential and the second information potential to the first signal line according to the input signal, and the receiver circuit outputs the second information potential having a predetermined capacitance. Signal wiring, a third signal wiring having a predetermined capacity, the first signal wiring and the second signal wiring are connected in the first period, and the first signal is connected in the second period. A control unit that connects the wiring and the third signal wiring,
Signal transmission circuit. 16. The signal transmission circuit according to claim 15, wherein the signal transmitted via the first signal line is synchronized with a timing at which the first period and the second period are switched. 17. A signal transmission circuit including a first signal wiring, a driver circuit for driving the first signal wiring, and a receiver circuit for receiving a signal transmitted through the first signal wiring. In the first period, the driver circuit outputs the reference potential to the first signal line, and in the second period, the driver circuit outputs the first information potential and the second information potential according to the input signal. A second output section for outputting one of the information potentials to the first signal line, the receiver circuit including a second signal line, a third signal line, and a second signal line. A delay circuit for delaying the potential of the signal transmitted through the first signal wiring by a predetermined delay time and transmitting the delayed signal to the third signal wiring, wherein the second signal wiring is 1 is directly connected to the signal line, and the third signal line is connected via the delay circuit. It is connected to the first signal line, the signal transmission circuit. 18. A signal transmission circuit comprising: a first signal wiring; a driver circuit for driving the first signal wiring; and a receiver circuit for receiving a signal transmitted through the first signal wiring. The driver circuit outputs one of the first information potential and the second information potential to the first signal wiring in response to the input signal, and the receiver circuit outputs the second signal wiring to the first signal wiring. And a delay circuit for delaying the potential of the signal transmitted through the first signal wiring by a predetermined delay time and transmitting the delayed signal to the third signal wiring. The second signal wiring is directly connected to the first signal wiring, and the third signal wiring is connected to the first signal wiring via the delay circuit.