JPH0982944A - Strained silicon field effect transistor and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A high electric field characteristic of a buried strained silicon field effect transistor is improved. [Structure] A SiGe buffer layer (13, 14), a strained silicon active layer (15), and Si on a silicon substrate (11).
An intermediate layer (16) having a compound semiconductor intermediate layer (16)
Is provided with a gate structure (19, 20). The buffer layer (14) contacts the silicon active layer with lattice relaxation, and the intermediate layer (16) has a thickness smaller than the spread of the electron wave function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Silicon is used in various applications such as IC, LSI and V because of its high reliability and adaptability to planar technology.
Further progress is being made in LSI and ULSI. On the other hand, judging only from the electrical characteristics of the semiconductor material itself, the compound semiconductor is more attractive than Si in terms of light effective electronic mass and relatively easy band engineering due to the heterostructure. However, due to recent advances in thin film crystal growth techniques such as molecular beam epitaxial growth (MBE), low pressure chemical vapor deposition (LP-CVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), etc. Heterostructures such as Si / Si _1-x Ge _x can be produced even with a system material, and high-performance silicon heterodevices are being realized together with the understanding of the physical properties of silicon-based heteromaterials.

A characteristic of the Si / Si _1-x Ge _x heteroepitaxial structure is that it contains strain due to lattice mismatch. For this reason, the thin film in which strain occurs varies depending on the structure of the laminated film, and the energy band structure at the heterojunction changes accordingly. A system that is particularly interesting in terms of physical properties is a strained silicon thin film that is epitaxially grown on strain-relaxed Si _1-x Ge _x and is strained by tensile stress. It is known that in-plane mobility of electrons is increased in this system (for example, Volgelsang (Volge).
L. Sang) and Hoffmann, App.
lied Physics Letters, Vol.
63 (1993) p. 186). This is for the following reason.

That is, FIG. 7A shows the Fermi surface of bulk silicon. Bulk silicon has six equivalent valleys in the conduction band, and electrons are distributed in an equal number to each valley. Therefore, if the two valleys on the (001) axis shown in black in FIG. 7A are represented by Δ ₂ and the remaining 4 valleys located on the xy plane are represented by Δ ₄ , the bulk silicon is In Δ2, 1/3 of the total number of electrons is occupied. Further, each valley has a spheroidal shape rather than a spherical shape, and the effective mass differs depending on the direction in which electrons move. For example, (00
Taking the valley in the 1) direction as an example, the mass in the (001) direction is heavy and m _l = 0.92m ₀ (m ₀ is the electron mass in vacuum)
And a light mass m _t = 0.19 m _{0 in} the direction perpendicular to this (in the xy plane). Now, strain relaxation Si
_In strained Si epitaxially grown on _1-x Ge _x ,
The energy levels of Δ ₂ and Δ ₄ are split, and Δ ₂ is lower in energy in proportion to the composition x of Ge than Δ ₄ (see FIG. 7B. For example, people (IEEE Jo
internal of Quantum Electronics
cs, Vol. QE-22 (1986) p. 1696)
Reported by. ). For this reason, if the value of x is made large enough that thermal excitation between Δ ₂ and Δ ₄ is not a problem (usually x> 0.2), most of the electrons will be Δ ₂
Will be occupied.

Based on the above, the electric current is parallel to the layers (xy).
Consider the mobility when it is flown in the plane. However, in this case, the temperature is sufficiently high, and the quantum size effect due to the mass difference is ignored because it is simple. Further, it is assumed that the x value is sufficiently large and that all electrons exist in Δ2 in strained Si. Now, the mobility is proportional to the effective mass. In unstrained silicon, both a heavy mass component and a light mass component contribute, whereas in strained silicon, only a light mass component contributes, so the effective mass that acts on the mobility becomes lighter, and the mobility increases. Enhancement factor of mobility due to the mass _{effect, (1 / m t) /} ((4 /
6) (1 / m _t ) + (2/6) (1 / m _l )) + 3 /
(2+ (m _t / m _l )) = 1.36. Furthermore, the energy separation of the valley into Δ ₂ and Δ ₄ causes suppression of valley scattering. Especially, in the vicinity of room temperature, many acoustic phonons exist, and the contribution of this valley scattering is large. Therefore, it is predicted in the above-mentioned paper by Borgersang et al. There is.

FIG. 8 shows the structure and energy band diagram of a field effect transistor using strained silicon (Welser et al., IEEE Electron D).
device Letters, Vol. 15 (199
4) p. 100). In the transistor shown in FIG. 8A, the structure of the interface where two-dimensional electrons are induced is strained Si / Si.
It is O ₂ and is called a strained silicon MOS-FET. On the other hand, the transistor shown in FIG. 8B has strained Si / S.
i _0.7 Ge _0.3 / SiO ₂ , which is called an embedded strained SiMOS-FET, and is intended to accumulate two-dimensional electrons at the interface between the strained Si and the Si _0.7 Ge _0.3 intermediate layer. . In both structures, the SiGe buffer layer is first grown on the substrate Si. The SiGe buffer layer comprises a 1.5 μm thick concentration-graded buffer layer in which the Ge composition is gradually changed from 5% to 30% and a 0.25 μm lattice-relaxed Si _0.7 Ge layer formed on the buffer layer.
It is formed by _0.3 layers. The effect of the buffer layer with concentration gradient is that Fitzgerald (Fitzgeral)
d) et al. Applied Physics Letter
rs, Vol. 59 have been reported in (1991) 811, the lattice constant of the lattice relaxed Si _0.7 Ge _0.3 layers completely relaxed to its original Si _0.7 Ge _0.3 layer and threading dislocations can be suppressed. Therefore, the lattice constant of the Si layer grown on the SiGe buffer layer is distorted. Further, since the thickness of this strained Si layer is as thin as about 10 nm, which is smaller than the critical film thickness, a good quality crystal without misfit dislocations is grown (for the critical film thickness, for example, the above-mentioned people As described in the paper).

Si shown in each of FIGS. 8A and 8B
The O ₂ film is obtained by thermal oxidation (gate oxidation) of an epitaxial wafer that has grown to a strained Si crystal.
Therefore, in the structure of FIG. 8A, the film thickness of the strained Si on the surface was 16 nm as it was grown, but 10 nm was consumed by the gate oxidation and 12 nm of SiO
_Two films are formed. Further, in the structure of FIG. 8B, a strained Si layer having a film thickness of 10 nm was grown on the surface of the structure as it was grown, but all was consumed by gate oxidation. It is generally known that the oxide film of SiGe forms an interface trap level and adversely affects the characteristics such as the mobility of the device. The buried strained SiMOS shown in FIG.
In -FET, it is necessary to completely consume the strained Si cap layer on the surface due to gate oxidation.

FIG. 9 shows the characteristics of the device by Wesler et al. In comparison with a normal silicon MOS-FET. In FIG. 9A, the mobility is shown as an effective electric field in the direction perpendicular to the layer at the position where the two-dimensional electron system exists. When the effective electric field is small (<0.1 MV / cm), the mobility of the strained silicon MOS-FET is 1.8 times that of the normal one, and the mobility of the buried strained silicon MOS-FET is 2.
A 9-fold improvement is seen. Thus, the buried strained silicon MOS-FET is more improved, because the Si / SiO ₂ interface has a larger electron scattering at the interface than the Si / SiGe hetero interface. However, the buried strained silicon MOS-FET has the structure shown in FIG.
As seen in (a), the mobility is drastically reduced at a high effective electric field. This is because electrons are SiO ₂ / S in a high electric field.
This is because they start to accumulate at the i _0.7 Ge _0.3 interface. SiO
_{It is considered that the 2} / Si _0.7 Ge _0.3 interface is rougher than the Si / SiO ₂ interface, and the mobility of Si _0.7 Ge _0.3 is smaller than that of Si. Such a drastic decrease in mobility of the buried strained silicon MOS-FET at a high electric field is as shown in FIG. 9 (b).
This causes a sharp decrease in transconductance in this device.

[0009]

As described above, since the conventional buried strained silicon MOS-FET utilizes the good quality Si / Si _1-y Ge _y interface,
A low electric field has a larger mobility than a normal silicon MOS-FET, but a high electric field causes a rapid decrease in mobility and a decrease in mutual conductance resulting from this, and no practical device has been obtained. Is the current situation.

Further, embedded strained silicon MOS-FE
At T, it is necessary to make the thickness of the strained silicon cap layer on the surface consumed by gate oxidation equal to the thickness of the strained silicon layer in epitaxial growth, and the device yield is reduced due to the instability of the oxidation process and growth film thickness control. There was also the problem of becoming low.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an embedded strained silicon field effect transistor which does not cause a decrease in mobility in a high electric field and a method for manufacturing the same. is there.

[0012]

According to the present invention, firstly, a lattice relaxation buffer layer, a silicon active layer, and a Si-based compound semiconductor intermediate layer are provided on a silicon substrate, and the intermediate layer is provided with a gate structure. In the buried strained silicon field effect transistor, the buffer layer contacts the silicon active layer with lattice relaxation, the active layer has internal strain, and the intermediate layer has a thickness smaller than the spread of the electron wave function. Provided is a buried strained silicon field effect transistor having a thickness.

The buffer layer is usually made of a SiGe compound and has a composition of Si _1-x Ge _x (where 0 <x ≦ 1), and the intermediate layer is Si _1-y Ge _y (where x is x). ≦ y ≦ 1)
Can have a composition of Further, the buffer layer preferably has a concentration gradient with respect to Ge. Other forms of the buffer layer include II-VI group compound semiconductor ZnSSe and III-V.
It is also possible to use the group compound semiconductor InGaP.

Secondly, the present invention is a method for manufacturing the above-mentioned buried strained silicon field effect transistor, which comprises a lattice relaxation buffer layer, a silicon active layer, and
Provided is a method of growing an Si-based compound semiconductor intermediate layer and a gate structure without exposing to the atmosphere.

Usually, the lattice relaxation buffer layer, the silicon active layer, and the Si-based compound semiconductor intermediate layer are continuously formed by epitaxial growth, and the gate structure is also formed by the apparatus in which the epitaxial growth is performed, or by using the epitaxial apparatus and high vacuum. The gate structure is continuously formed by the connected insulating film forming apparatus.

The buried strained silicon FET of the present invention is
The silicon-based compound semiconductor intermediate layer (eg, Si _1-y Ge _y ) layer formed between the strained silicon layer and the gate structure has a thickness smaller than the spread of the electron wave function (about 5 nm). And

According to the present invention, since the spread of the electron wave function is smaller than the film thickness of the intermediate layer, the existence probability of electrons in the intermediate layer can be greatly reduced even in a high electric field.
Si / 2-dimensional electron intermediate layer interface is prevented from escaping to the SiO ₂ / intermediate layer interface, also becomes small decrease in mobility and transconductance at high electric field.

More specifically, the thickness of the intermediate layer is 0.5.
Especially preferred is nm to 5 nm. The gate structure is not limited to the insulating layer / conductive layer laminated structure, but may be the Schottky barrier structure in which a conductive layer such as a metal is directly formed on the intermediate layer.

Further, according to the manufacturing method of the present invention, since the gate oxidation step is unnecessary and each layer is grown without being exposed to the atmosphere, there is no fear that the intermediate layer is oxidized, and therefore the buried strain is generated. It is possible to form the SiO ₂ / intermediate layer interface of the SiMOS-FET with high quality and good controllability.

[0020]

Embodiments of the present invention will be described below. FIG. 1 shows a MOS-FET according to the first embodiment.
The schematic sectional drawing of is shown. As shown in FIG. 1, p is added to the surface area.
The first buffer layer 13 made of Si _1-x Ge _x is formed on the p ⁻ type silicon substrate 11 on which the ⁺ type region 12 is formed.
It is formed to a thickness of μm. This first buffer layer 1
Si _1-x Ge _x forming _No. 3 has a concentration gradient in which the composition ratio x of Ge continuously changes from 0 to 0.3 from the bottom surface to the surface. On the first buffer layer 13,
The second buffer layer 14 is formed to have a thickness of 100 nm. The second buffer layer 14 is made of Si _0.7 Ge _0.3.
And the lattice constant is relaxed on the buffer layer 14. A strained silicon layer 15 having a thickness of 15 nm is formed on the second buffer layer 14, and a thickness of 4 nm is formed on the strained silicon layer 15.
nm of Si _1-y Ge _y intermediate layer 16 is deposited. In the Si _1-y Ge _y forming the intermediate layer 16, the Ge composition ratio y is, for example, 0.3. The two-dimensional electron is the intermediate layer 16
Is induced near the interface between the strained silicon layer 15 and the strained silicon layer 15. Middle layer 1
A source region 17 and a drain region 18 defined by an insulating layer 21 are formed from 6 to the second buffer layer 14. The layers 13, 14, 15, 16 are p-type and are doped with an impurity concentration of, for example, 1 × 10 ¹⁶ cm ⁻³ . A silicon oxide film 19 and n are formed on the intermediate layer 16.
⁺ A polysilicon gate 20 is stacked to form a buried strained silicon element.

FIG. 2 illustrates the effect of the present invention using an energy band diagram at the conduction band edge and a wave function.
2A shows a band diagram corresponding to the first embodiment in which the film thickness d of the Si _0.7 Ge _0.3 intermediate layer 16 is 4 nm, and FIG. 2B shows a conventional example in which d = 9 nm. In both cases, the magnitude of the effective electric field is approximately 0.3 MV / cm. In the conventional example, the wave function 51 ′ is the Si _0.7 Ge _0.3 intermediate layer 1
It has a large amplitude at 6 '. That is, electrons are occupied in the SiGe intermediate layer, which causes a decrease in mobility.
On the other hand, in the present invention, as shown in FIG.
Since the thickness of the intermediate layer 16 is 4 nm, which is smaller than the spread of the wave function (about 5 nm), the wave function 51 is
6 has no amplitude and mobility does not deteriorate.

FIG. 3 illustrates the effect of the present invention on the mobility of SiGe as a function of the effective electric field at the interface of layers 15 and 16.
It is plotted when the film thickness d of the intermediate layer is 9 nm, 6 nm, and 4 nm. When the thickness d of the intermediate layer is reduced from 9 nm to 6 nm, the mobility increases under the same effective electric field. This is because under the same effective electric field, the potential difference between both end faces of the intermediate layer becomes smaller in proportion to the film thickness. However, when the effective electric field is high, a sharp decrease in mobility is observed in both cases. This is because electrons are distributed in the SiGe intermediate layer as shown in FIG.
On the other hand, when the thickness of the intermediate layer is 4 nm, the mobility is hardly deteriorated due to the above-mentioned effect even when the effective electric field is high.

The MOS-FET shown in FIG.
HV-CVD method, LP-CVD method, MBE method, etc. can be used for continuous epitaxial growth without exposing to the atmosphere. For example, first, prior to the growth, boron is selectively ion-implanted into the substrate 11 to form the p ⁺ -Si region 12. After that, the surface is thermally oxidized and then subjected to high temperature heat treatment to recover the damage due to the ion implantation. In addition, the above process is c-MO.
It corresponds to S well separation and can be omitted in some cases. After removing the oxide film on the surface with buffered hydrofluoric acid,
The substrate is mounted on a UHV-CVD apparatus, disilane and germane are used as source gases, and the gas flow rate of germane is gradually changed to grow the first buffer layer 13 with a concentration gradient. After that, the second buffer layer 14, the strained silicon layer 15, and the intermediate layer 16 are sequentially grown by controlling the flow rate of germane. Diborane can be used as a source gas for p-type impurities in these layers. Si
After growing the Ge intermediate layer 16, disilane and oxygen gas are simultaneously introduced to form a SiO ₂ film 19. Note that S
For forming the iO ₂ film, it is also possible to simultaneously introduce monosilane and H ₂ O ₂ gas. CVD on oxide usually results in polysilicon rather than crystals. Therefore, the n ⁺ type polysilicon layer 20 can be easily formed in the UHV-CVD chamber by using, for example, arsine as the impurity raw material. In the above growth flow, the SiGe buffer layer 13 to the polysilicon layer 20 are grown in the same growth chamber. When the growth apparatus does not have an oxygen gas line, the wafer is formed into 1 × 10 ⁻⁴ To after forming the intermediate layer 16.
It is transferred to other CVD equipment etc. by high vacuum of rr or less and Si
The O ₂ layer 19 and the polysilicon layer 20 can be formed. Insulating layer 1 by transportation under high vacuum that is not exposed to the atmosphere
The interface between 9 and the intermediate layer 16 can be kept clean.

The structure of FIG. 1 can also be made by conventional methods. In this case, a silicon cap layer having a thickness of 10 nm is laminated on the SiGe intermediate layer 16, and thermal oxidation is performed.
It is necessary to completely consume the silicon cap layer.

In the first embodiment described above, Si
The Ge composition y of the _1-y Ge _y intermediate layer was 0.3, which was the same as x of the SiGe buffer layer, but y can be larger than x (x ≦ y ≦ 1).

(Second Embodiment) FIG. 4 shows a schematic sectional view of an FET according to a second embodiment. In the embodiment shown in FIG. 4, a strained silicon layer 32 similar to the strained silicon layer 15 in the embodiment shown in FIG. 1 has a thickness of 9 nm on a substrate (not shown) similar to the substrate 11 shown in FIG. 1 on the SiGe buffer layer 31. Is formed. An Si _1-y Ge _y intermediate layer 33 is formed on the strained silicon layer 32, and a CaF insulating layer 36 having a thickness of 15 nm and n ⁺ are formed thereon.
A polysilicon layer 37 is formed. Further, a source region 34 and a drain region 35 similar to the source region 17 and the drain region 18 in the embodiment of FIG. 1 and an insulating layer 38 similar to the insulating layer 21 are also formed.

In the first embodiment, the Ge composition ratio y of the Si _1-y Ge _y intermediate layer 16 has a constant value, but the composition ratio y is changed to change the electric field applied to the intermediate layer 33. It can be mitigated. An electric field applied to the intermediate layer in order to effectively reduce, as shown in FIG. 5 (a), Si 1- y
From the interface between the Ge _y intermediate layer 33 and the strained silicon layer 32, S
The Ge composition y may be increased toward the interface between the i _1-y Ge _y intermediate layer 33 and the insulating film 36. Also, FIG.
As shown in (b), this increase in y may be gradual. As described above, when the Ge composition y of the intermediate layer is changed, even if the thickness of the intermediate layer 33 is larger than 5 nm, the electric field relaxation effect does not deteriorate the mobility up to an electric field larger than that in the conventional example. However, the thickness of the intermediate layer 33 is 5 nm.
If the electron occupancy in the intermediate layer is suppressed quantum mechanically, the mobility will not be deteriorated even at a higher electric field. This is essentially the same as described with respect to FIG.

In the second embodiment, the CaF layer 36 is used as the insulating film 36 instead of the SiO ₂ film. Other fluorides such as BaSrF can be used instead of CaF. The fluoride insulating film such as CaF or BaSrF can be formed by MBE, for example. Furthermore, SiG
As the e buffer layer 31, in addition to the combination of the concentration-gradient buffer layer 13 and the Si _0.7 Ge _0.3 buffer layer 14 shown in FIG. 1, a superlattice buffer (for example, Ismail et al., Applied Physi) is used.
cs Letters, Vol. 58 (1991) 21
17)).

(Third Embodiment) FIG. 6 is a schematic sectional view of an FET according to the third embodiment. This FET
Is the same as the structure shown in FIG. 1 except that the gate structure does not depend on the silicon oxide film 19 and the polysilicon film 20, but a metal layer 41 is deposited to form a Schottky structure.
Therefore, the same parts as those in FIG.

In the above embodiments, Si is used as the intermediate layer.
_Although it has been described using _1-y Ge _y , Si _1-yz Ge _y C _z
It may be a mixed crystal. The strained Si active layer is the intermediate layer G
The strained SiGe active layer may have a Ge composition smaller than the minimum e composition. Besides, various modifications can be made without departing from the scope of the present invention.

[0031]

As described above, according to the present invention, in a buried strained silicon FET utilizing a high quality Si / SiGe interface, mobility and mutual conductance are not deteriorated even in a high effective electric field. You can get the device.

[Brief description of drawings]

FIG. 1 is a sectional view of a buried strained silicon MOS-FET according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating suppression of electron occupancy in a SiGe intermediate layer.

FIG. 3 is a diagram showing mobilities of SiGe intermediate layers having various thicknesses for comparison.

FIG. 4 is a sectional view of an embedded strained silicon MOS-FET according to a second embodiment of the present invention.

FIG. 5 is a graph showing a Ge composition gradient of a SiGe intermediate layer in a buried strained silicon MOS-FET according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a buried strained silicon FET according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a Fermi surface of unstrained silicon and valley energy splitting due to strain.

FIG. 8 is a sectional view showing a conventional strained silicon MOS-FET structure.

FIG. 9 is a graph diagram showing a comparison of special features of a conventional strained silicon MOS-FET structure.

[Explanation of symbols]

11 ... Substrate, 13, 14, 31 ... Buffer layer, 15, 3
2 ... Strained silicon layer, 16, 33 ... Intermediate layer, 17 ... Source region, 18 ... Drain region, 19, 36 ... Insulating layer, 2
0, 37 ... Polysilicon layer, 41 ... Schottky barrier layer.

Claims (4)

[Claims] 1. A buried strained silicon field effect transistor having a lattice relaxation buffer layer, a silicon active layer, and a Si-based compound semiconductor intermediate layer on a silicon substrate, wherein the intermediate layer is provided with a gate structure. The layer is in contact with the silicon active layer with lattice relaxation, the active layer has internal strain, and the intermediate layer has a thickness smaller than the spread of the wave function of electrons, embedded strained silicon. Field effect transistor. 2. The buffer layer is Si _1-x Ge _x (wherein
0 <x ≦ 1) and the intermediate layer is Si _1-y Ge _y
The transistor according to claim 1, having a composition (where x ≦ y ≦ 1). 3. The transistor according to claim 2, wherein the buffer layer has a concentration gradient with respect to Ge. 4. The method for manufacturing a buried strained silicon field effect transistor according to claim 1, wherein the lattice relaxation buffer layer, the silicon active layer, the Si-based compound semiconductor intermediate layer and the gate structure are exposed to the atmosphere on a silicon substrate. A method of manufacturing a buried strained silicon field effect transistor, which is characterized by growing without exposing.