JPH0981367A - Pattern detection circuit - Google Patents

Abstract

(57) Abstract: A circuit size of a circuit for detecting an alternating pattern in which 1 and 0 alternately appear by the same number is reduced. A first counter 10 counts a clock having a frequency equal to the bit rate of an input digital signal. The digital signal is input to one terminal of the XOR circuit 20. The XOR circuit 20 calculates the exclusive OR of the input digital signal and the QC output of the first counter 10. XOR
The output of the circuit 20 is input to the reset terminal of the first counter 10. While the input digital signal matches the 8-bit alternating pattern to be detected, QC of the first counter 10
The output is an inverted pattern of the input digital signal, so X
The output of the OR circuit 20 becomes 1, and the first counter 10 continues counting without being reset. When the input digital signal matches the alternating pattern over 8 bits, carry occurs in the first counter 10. This first counter 10
The carry signal of is used as the detection signal of the alternating pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern detection circuit for detecting a predetermined pattern from a digital signal.

[0002]

2. Description of the Related Art An alternating pattern means a signal pattern in which 1 and 0 alternately appear every n bits (n is an integer). For example, the pattern “1111000011110000 ...” is an alternating pattern in which 1 and 0 alternately appear in 4 bits. In a broad sense, a signal pattern in which a specific pattern and its inverted pattern alternate n times each may be called an alternating pattern. In this case, for example, "1
The pattern "110111000010001 ..."
This is an alternating pattern in which "1110" and its inverse "0001" appear alternately twice.

A signal having such an alternating pattern is used for transmitting control information (such as an alarm signal) between digital communication devices because of the small number of erroneous detections due to bit errors and the ease of clock extraction. Often used.

Generally, a digital communication device is provided with a control signal detection circuit for detecting a control signal having such an alternating pattern.

As a conventional example of such a control signal detecting circuit, an alarm detecting circuit for detecting an alarm signal between digital communication devices will be described. FIG. 7 is a diagram showing a conventional example of such an alarm detection circuit. This circuit has an 8-bit alternating pattern "11110" in which 1 and 0 appear alternately in 4 bits.
This circuit detects "000" (hereinafter referred to as "alternating pattern A") and outputs an alarm when the alternating pattern A is continuously input 16 times.

This conventional circuit comprises a pattern detecting section 100 and a continuous coincidence detecting section 120.

The pattern detecting section 100 is a section for detecting an alternating pattern A from an input digital signal, and is composed of an 8-bit serial-in / parallel-out type shift register 102 and an 8-input AND circuit 104. ing. The 8-bit digital signal input to the shift register 102 is output in parallel to the AND circuit 104. Here, the value of each bit of the first half of the shift register 102 is directly input to the four inputs of the first half of the AND circuit 104, and the inverted value of each bit of the second half of the shift register 102 is input to the four inputs of the second half of the AND circuit 104. Is entered.
Therefore, when the 8-bit signal input to the shift register 102 matches the alternating pattern A, AND
The output of the circuit 104 becomes 1. The output of the AND circuit 104 is input to the continuous match detection unit 120. Although not shown in FIG. 7, the pattern detection unit 100 includes
A circuit is provided which holds the output of the AND circuit 104 until the next 8 bits are input when the output of the AND circuit 104 becomes 1.

On the other hand, the continuous coincidence detecting section 120 includes an 8-bit serial-in / parallel-out type shift register 1
22, 8-input AND circuit 124, 4-input negative logic AN
It is composed of a D circuit 126 and an RS flip-flop 128.

The output of the AND circuit 104 is input to the shift register 122, and the shift register 122 is driven by a shift pulse having a cycle eight times the bit cycle of the input digital signal. The parallel outputs of the shift register 122 are input to the AND circuit 124 and the negative logic AND circuit 126, respectively.

The AND circuit 124 is a circuit for detecting that the input digital signal coincides with the alternating pattern A eight times in succession, and has a logical value of 1 when all 8 outputs of the shift register 122 become 1. Is output. On the other hand, the negative logic AND circuit 126 is a circuit for detecting that an alternating pattern and a non-matching pattern have continued four times in the input digital signal, and is logical when all the four tail outputs of the shift register 122 become zero. The value 1 is output. And
The outputs of the AND circuit 124 and the negative logic AND circuit 126 are input to the S terminal and the R terminal of the RS flip-flop 128, respectively.

The RS flip-flop 128 is a circuit for detecting and canceling an alarm. When the Q output is 0, the alarm is not detected, and when the Q output is 1, the alarm is detected. The Q output is transmitted to the control unit of the digital communication device, and the control unit performs a predetermined process such as displaying an error message according to the state of the Q output.

That is, when the output of the AND circuit 124 becomes 1, that is, when the alternating pattern A is continuously input eight times, the Q output of the RS flip-flop 128 becomes 1. Then, once the Q output becomes 1, the alarm detection state is maintained until the output of the negative logic AND circuit 126 becomes 1, that is, until a bit string that does not match the alternating pattern A is input four times in a row, and the alarm detection state is maintained. If is repeated four times, the alarm status is released.

As described above, the conventional control signal detection circuit is
The shift register is used to detect the alternating pattern and the pattern continuity.

[0014]

However, since the conventional circuit configuration for detecting the alternating pattern described above uses the shift register, the circuit scale tends to be large,
There is a problem in that it is difficult to accommodate in a PLD (Programmable Logic Device) or the like.

That is, in the case of a configuration using a shift register, an m-digit shift register is required to detect an m-bit alternating pattern, and m flip-flops are required to configure such a shift register. Becomes Therefore, if the number of bits of the alternating pattern to be detected becomes large, the number of flip-flops becomes large, and the circuit scale remarkably increases.

The present invention has been made to solve such a problem, and an object thereof is to provide a pattern detection circuit having a small number of flip-flops and a small circuit scale.

[0017]

In order to achieve the above-mentioned object, the first configuration of the pattern detection circuit according to the present invention is
A pattern detection circuit for detecting a predetermined alternating pattern in which 1 and 0 alternately appear every n bits from an input digital signal, counting a clock having a predetermined synchronization relationship with the input digital signal, A counter that outputs a reference signal having a pattern corresponding to the predetermined alternating pattern, the reference signal and the input digital signal are input, and whether the input digital signal matches the predetermined alternating pattern by comparing the two A reset signal generator that detects whether or not the input digital signal does not match the predetermined alternating pattern and supplies a reset signal to the counter; and the count value of the counter is a bit of the input digital signal. 2 per cycle
and a pattern detection signal generation unit that outputs a pattern detection signal when it becomes n. In this specification, n represents an integer of 1 or more.

In the first configuration, it is determined by comparing the reference signal and the input digital signal whether each bit of the input digital signal matches the predetermined alternating pattern. The reference signal is generated so as to have a pattern corresponding to the predetermined alternating pattern. As this reference signal, for example, 1 (until the first half n bits of the predetermined alternating pattern are detected, that is, until the count value of the counter becomes n (when converted to the bit period unit of the input digital signal; the same applies below)) In 0), the value is inverted with the count value becoming n as a trigger, and 0 is displayed until the count value reaches 2n.
A pattern such as (1) can be used. Such a reference signal can be generated by using the state value of each flip-flop in the counter. The reset signal generator compares such a reference signal with the input digital signal to determine whether the input digital signal matches the predetermined alternating pattern. The reference signal and the input digital signal can be compared, for example, by taking an exclusive OR or an inclusive AND of the two.

The reset signal generator supplies a reset signal to the counter when the input digital signal and the predetermined alternating pattern do not match. The count value of the counter is returned to 0 when the reset signal is input. That is, in this configuration, the counter continues to count up while the input digital signal and the predetermined alternating pattern match, and when the two do not match, the counter is reset.

Therefore, the counter starts counting up the clock when the input digital signal starts to match the value 1 (0) in the first half of the predetermined alternating pattern (because the input digital signal is in the first half of the predetermined alternating pattern). Until the values match, the two do not match and the counter is reset.) While the two match, counting continues. Then, when the count value of the counter becomes 2n in the bit cycle unit of the input digital signal, it means that the input digital signal matches the predetermined alternating pattern over 2n bits. This means that the 2n-bit input digital signal completely matches the predetermined alternating pattern. The pattern detection signal generator outputs a pattern detection signal when it detects a match of 2n bits between the input digital signal and the predetermined alternating pattern based on the count value of the counter.

According to such a configuration, the number of flip-flops required to detect the alternating pattern having the same number of bits can be far reduced as compared with the configuration using the conventional shift register. In the conventional configuration, N flip-flops are required to detect an N-bit alternating pattern. However, in order to detect the same alternating pattern, in the first configuration of the present invention, the number of log ₂ N order is required. The number of flip-flops is enough. Therefore, according to this configuration,
The circuit scale of the pattern detection circuit can be reduced, and P
It becomes easy to store in the LD.

Also, in the second configuration of the present invention, in the first configuration, when the count value of the counter reaches n in the bit cycle unit of the input digital signal, the first half n of the predetermined alternating pattern is obtained. A pattern first half detection unit that outputs a first half detection signal indicating that a bit has been detected,
The input digital signal and the first half detection signal are input,
A count stop signal generation unit that outputs a count stop signal to the counter while the digital signal having the logical value of the first half is still input after the first half detection signal is input. However, the counter temporarily stops the counting operation while holding the count value while the count stop signal is input.

The second structure is a structure for preventing omission of detection due to the influence of the signal immediately before the alternating pattern.

In the second configuration, when the signal having the logical value of the first half of the predetermined alternating pattern is detected for n bits and then the signal having the same logical value continues, the counter value is held while the count value is held. Pause the operation,
The operation of the counter is restarted when a signal having the logical value of the latter half is input. According to this configuration, even when the alternating pattern is input subsequent to the signal having the first half value of the alternating pattern in the input digital signal, the alternating pattern can be detected.

A third structure of the present invention is a pattern detection circuit for detecting a predetermined 2n-bit alternating pattern in which the same number of unit patterns and inverted patterns thereof alternately appear from the input digital signal. , A counter that counts clocks having a predetermined synchronization relationship with the input digital signal and outputs a reference signal having a pattern in which 1 and 0 alternately appear every n bits, and the reference signal and the input digital signal are input A pattern conversion unit that converts the input digital signal into repetitions of the unit pattern and outputs the input digital signal while the input digital signal matches the predetermined alternating pattern by obtaining the exclusive OR of the two signals; The output of the pattern conversion unit is compared with the repetition of the unit pattern, and when the two do not match, the counter A reset signal generating unit for supplying a reset signal, and a pattern detection signal generator outputting a pattern detection signal when the count value of the counter becomes 2n in the bit cycle unit of the input digital signal.

The third structure is for detecting a predetermined alternating pattern of 2n bits in which the same number of unit patterns and their inverted patterns are alternately appeared. The target alternating pattern here is, for example, “110111101001.
This is a pattern such as 00010 ", which is a 16-bit (n = 8) alternating pattern in which the unit pattern" 1101 "and its inverted pattern" 0010 "appear twice each.

In the third configuration, as in the first configuration, while the input digital signal matches the predetermined alternating pattern,
The clock synchronized with the input digital signal is counted by the counter, and when the count value becomes 2n in the bit period unit of the input digital signal, it is determined that the predetermined alternating pattern is detected.

In the third configuration, the unit pattern and 0 (1)
It is used that both the exclusive OR of and the exclusive OR of the inversion pattern and 1 (0) become a unit pattern (or inversion pattern). That is, in the example of the alternating pattern, the unit patterns “1101” and “000” are used.
The exclusive OR with "0" is "1101", but the exclusive OR with the inversions "0010" and "1111" of the unit pattern is also "1101".

Therefore, if a reference signal in which 1 and 0 alternately appear every n bits is generated on the basis of the internal state of the counter, and the pattern conversion section takes an exclusive OR of the reference signal and the input digital signal. , While the input digital signal matches the predetermined alternating pattern, the output of the pattern conversion unit is the unit pattern (or its inverted pattern).
Will be repeated. Therefore, in the reset signal generator,
The output signal of the pattern conversion unit is compared with the unit pattern (or inverted pattern), and when the two do not match, a reset signal is issued to the counter.

With this configuration, it is possible to detect an alternating pattern in which the same number of unit patterns and their inverted patterns alternately appear with a small circuit scale.

A fourth structure of the present invention is a pattern detecting circuit for detecting a predetermined pattern in which first and second patterns of n bits alternately appear from an input digital signal. When a digital signal is input and the first pattern is detected from the input digital signal, a signal of logical value 1 (0) is continuously output for n bits,
When a second pattern is detected from the input digital signal, a preprocessing circuit that continuously outputs a signal having a logical value 0 (1) for n bits and a clock having a predetermined synchronization relationship with the input digital signal are counted. However, a counter that outputs an output pattern in which 1 and 0 alternately appear every n bits, a reference signal based on the output pattern, and an output signal of the preprocessing circuit are input, and when the two do not match, A reset signal generator that supplies a reset signal to a counter, and a pattern that outputs a pattern detection signal indicating that the predetermined pattern has been detected when the count value of the counter becomes 2n in a bit cycle unit of the input digital signal. And a detection signal generation unit.

In this configuration, the preprocessing circuit converts the first pattern and the second pattern into n-bit 1 (0) and 0 (1), respectively. Therefore, when the input digital signal has a predetermined pattern in which the first and second patterns of n bits alternately appear, the output signal of the preprocessing circuit is an alternating pattern in which 1 and 0 alternately appear every n bits. Become. Then, a predetermined pattern is detected by detecting this alternating pattern according to the same principle as the first configuration.

The fifth constitution of the present invention is the first to the above.
In the fourth configuration, a second counter that is further connected to the outputs of the pattern detection signal generation unit and the reset signal generation unit, counts the pattern detection signal, and clears the count value when the reset signal is input. And a continuous coincidence signal generation unit that outputs a continuous coincidence signal when the count value of the second counter reaches a predetermined set value.

According to the fifth configuration, by counting the pattern detection signal by the second counter, it is possible to detect that the predetermined alternating pattern has continued a predetermined number of times in the input digital signal.

Further, a sixth structure of the present invention is characterized in that, in the above-mentioned fifth structure, a coincidence consecutive number set value varying means for varying the set value in the consecutive coincidence signal generating section is further provided. .

According to the sixth structure, it is possible to change the number of times of alternating pattern continuation, which is a condition for issuing the continuous coincidence signal.

A seventh configuration of the present invention is the clock according to the fifth or sixth configuration, which is further connected to the pattern detection signal generating section and has a predetermined synchronization relationship with the input digital signal. And the count value is cleared when the pattern detection signal is input.
A pattern for outputting a pattern mismatch signal indicating that the input digital signal does not match the predetermined alternating pattern when the count value of the counter and the third counter becomes 2n in the bit cycle unit of the input digital signal. A non-coincidence signal generation unit, a fourth counter connected to the pattern detection signal generation unit and the pattern non-coincidence signal generation unit, for counting the pattern non-coincidence signal, and for clearing the count value when the pattern detection signal is input; Connected to the continuous mismatch signal generation unit that outputs a continuous mismatch signal when the count value of the fourth counter reaches a predetermined set value, and the continuous mismatch signal generation unit and the continuous mismatch signal generation unit, An alarm detection signal is output when a match signal is input, and an alarm detection signal is output until the continuous disagreement signal is input. Having an alarm detector to continue, the.

In the seventh structure, the alarm detection signal is issued when the predetermined pattern continues for a predetermined number of times or more in the input digital signal, and the warning detection signal is released when the bit string which is not the predetermined pattern continues for the predetermined number of times or more.

In the seventh configuration, the third counter detects that the input digital signal does not match the predetermined pattern. The third counter counts clocks having a predetermined synchronous relationship with the input digital signal, and the count value is cleared when the pattern detection signal is input.
Therefore, when the third counter is not cleared and its count value becomes 2n, it means that the 2n-bit digital signal input so far does not match the predetermined pattern. Therefore, the pattern mismatch signal generation unit
It detects that the count value of the third counter has reached 2n and outputs a pattern mismatch signal.

The fourth counter counts this pattern mismatch signal. Then, the continuous disagreement signal generation unit outputs the continuous disagreement signal when the count value of the fourth counter reaches a predetermined set value. The alarm detection unit outputs the alarm detection signal when the continuous coincidence signal is input, and continues to output the alarm detection signal until the continuous disagreement signal is input.

In this configuration, the alarm detection signal is first issued when the predetermined pattern is continuously input a predetermined number of times or more, and the alarm detection signal once issued has a pattern that does not match the predetermined pattern a predetermined number of times or more. If it is not input, the alarm cannot be stopped, so that false alarm detection can be prevented.

An eighth structure of the present invention is characterized in that, in the above-mentioned seventh structure, a mismatch continuous number set value changing means for changing the set value in the continuous mismatch signal generating section is provided.

According to the eighth structure, it is possible to change the number of consecutive alternating pattern pattern mismatches, which is a condition for issuing the continuous mismatch signal.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a pattern detection circuit according to the present invention will be described below with reference to the drawings.

Embodiment 1. FIG. 1 is an explanatory diagram showing a circuit configuration of a first embodiment of a pattern detection circuit according to the present invention. The circuit of FIG. 1 issues an alarm detection signal when an alternating pattern A “111100” in which 1 and 0 alternately appear in 4 bits is input eight times in a row, and an 8 bit different from the alternating pattern A is generated. The circuit configuration for canceling the alarm detection signal when the pattern is input four times in succession is shown.

As shown in the figure, each of the counters 10 to 16 is supplied with a clock (CLK) having a frequency equal to the bit rate of the input digital signal. Counter 1
0 to 16 count this clock. Counter 1
The counting operation of 0 to 16 is controlled by the inputs of the enable terminal E and the reset terminal R. That is, each counter counts clocks while the input of the E terminal is "1" and does not count clocks when the input of the E terminal is 0. When the input to the R terminal is "1", the counter is reset to the initial value at the rising edge of the clock. In this configuration, since the counters 10 and 14 are always in a countable state, the counters 10 and 14 have E in FIG.
Illustration of terminals is omitted.

In this circuit configuration, the XOR circuit 20 and the first
The counter 10 detects the coincidence between the input digital signal and the alternating pattern A to be detected. First, a configuration for detecting this alternating pattern will be described.

The principle of pattern detection in this configuration is as follows.
The input digital signal and the alternating pattern A are compared bit by bit, the coincidence between them is counted by a counter, and when both coincide with each other for 8 consecutive bits, the 8-bit digital signal input up to that time is alternated. It is determined that the pattern A is matched.

In this circuit configuration, the reference signal which is the inverted pattern of the alternating pattern A is generated based on the decoded output of the first counter 10. In this embodiment, the first
The counter 10 is a 3-bit binary counter, and the decode output QC of the most significant bit of the first counter 10 is used as a reference signal. Then, the XOR circuit 20 obtains the exclusive OR of the reference signal and the input digital signal to check whether the input digital signal and the alternating pattern A match each other. The output of the XOR circuit 20 becomes "1" while the input digital signal matches the alternating pattern A, and becomes "0" when they do not match. Therefore, if the output of the XOR circuit 20 is inverted and input to the R terminal of the first counter 10, the first counter 10 counts the clock (CLK) while the alternating pattern matches the input digital signal. Become. Here, since the clock has a frequency equal to the bit rate of the input digital signal, when the count value of the first counter 10 becomes 8, the 8-bit digital signal sequence input up to that time is alternated. It can be determined that the pattern A matches. In this case, since the first counter 10 is a 3-bit counter, a carry occurs when the count value reaches 8. Therefore, this carry signal (CO) is used as a signal indicating that the alternating pattern A is detected (hereinafter referred to as a pattern detection signal).

On the contrary, when the input digital signal does not match the alternating pattern A at a certain bit, the output of the XOR circuit 20 becomes "0" at that time. Then, the first
The R input of the counter 10 becomes "1", and the first counter 10 is reset to the initial state (QA = QB = QC = 0).

The flow of the above processing will be described with reference to FIG.

FIG. 2 is a time chart showing an example of the detection operation of the alternating pattern A by the first counter 10 and the XOR circuit 20. The initial state of the first counter 10 is QA
Since = QB = QC = 0, the reference signal a (= QC) initially has the logical value "0", as shown in FIG. Therefore, the logical value of the input digital signal is "0"
The output b of the XOR circuit 20 is "0" during the period. Therefore, the R input of the first counter 10 becomes "1",
The first counter 10 is reset to the initial state each time the clock (CLK) rises. When the logical value of the input digital signal becomes "1" at time t1, the XOR circuit 20
Output b becomes "1", the R input of the first counter 10 becomes 0, and the first counter 10 clocks (CLK).
Start counting.

In the example of FIG. 2, the input digital signal changes to "11110000" after time t1. From time t1 to t2, the value of the reference signal a is "0" while the value of the input signal is "1". Therefore, the output b of the XOR circuit 20
Becomes "1", and the first counter 10 continues to count up. At time t2, since the first counter 10 has counted 4 clocks by then, the most significant bit QC
Becomes "1", and the value of the reference signal a changes from "0" to "1". From time t2 to t4, the value of the reference signal a is "1" while the value of the input signal is "0". Therefore, the output b of the XOR circuit 20 remains "1", and the first counter 10 Keeps counting up. Then, at the rising edge of the eighth clock at time t3, the CO output (signal c in FIG. 2) becomes "1". This CO output is
The pattern detection signal is supplied to the second counter 12.

At time t4, since QC = 0, the value of the reference signal a also becomes "0". On the other hand, in this example, the input digital signal changes to “110 ...” After time t4. Therefore, the output b of the XOR circuit 20 remains "1" until the time t5, and the first counter 10 performs the count-up operation.

However, at time t5, the input digital signal becomes "0", and the coincidence with the alternating pattern A is broken. Then, since the output b of the XOR circuit 20 becomes "0", the R input of the first counter 10 becomes "1".
Becomes Therefore, the first counter 10 is reset to the initial state in synchronization with the clock.

As described above, according to the circuit configuration shown in FIG. 1, the alternating pattern A can be detected from the input digital signal by the functions of the first counter 10 and the XOR circuit 20. In the conventional pattern detection method using the shift register, eight flip-flops are required to configure the shift register for detecting the 8-bit alternating pattern. According to this configuration, the counter has three flip-flops. Only flip-flops are needed, and the number of flip-flops is greatly reduced. More generally speaking, in the case of detecting a 2 ^m- bit alternating pattern, if the detection circuit is configured by a shift register, 2 ^m flip-flops are required. According to the circuit configuration of this embodiment, ^m number of flip-flops are required. All you need is a flip-flop.

The operation of alternating pattern detection in the first embodiment has been described above. Next, an alarm detection operation based on the detection of the alternating pattern A will be described.

In this embodiment, in order to prevent erroneous detection of an alarm, the alarm detection signal is first issued when the alternating pattern A is continuously input eight times. Therefore, in this embodiment, the second counter 12 counts the number of consecutive alternating patterns A in the input digital signal.

The second counter 12 counts based on the CO output of the first counter 10. The CO output of the first counter 10 is input to the E terminal of the second counter 12.
The second counter 12 can count (enable) only while the CO output of the first counter 10 is "1".
In this state, the clock (CLK) is counted during that time. As described above, the CO output of the first counter 10 becomes the logical value "1" for one clock cycle every time one pattern of the alternating pattern A is detected. Therefore, the count value of the second counter 12 is one pattern of the alternating pattern A. It is incremented by 1 each time it is detected. In this example, the second counter 12 is 3
It is a binary counter of bits. Therefore, if the initial value of the second counter 12 is set to 0, the second counter 1
When the count value of 2 becomes 8, that is, when the alternating pattern A is detected eight times in the input digital signal, the CO output becomes "1".

The CO output of the second counter 12 is input to the alarm detection circuit 30. The alarm detection circuit 30 is composed of an RS flip-flop, and has a second counter 12
CO output of is input to the S terminal. Therefore, when the alternating pattern A is repeated eight times, the Q output of the alarm detection circuit 30 becomes "1". The Q output of this logical value "1" serves as an alarm detection signal. The Q output is transmitted to the control unit of the digital communication device, and the control unit performs a predetermined process such as displaying an error message according to the state of the Q output.

If a mismatch between the input digital signal and the alternating pattern A is detected before the carry of the second counter 12, it is necessary to reset the second counter 12. Therefore, the first embodiment has a configuration in which the inversion of the output of the XOR circuit 20 is input to the reset terminal (R) of the second counter 12.

Next, a configuration for canceling the alarm detection signal generated in this way will be described. In this embodiment, in order to prevent the alarm from being erroneously released due to a bit error or the like, the alarm detection signal is released only when a pattern other than the alternating pattern A is continuously input four times.

Therefore, in the first embodiment, the third counter 14 detects a pattern other than the alternating pattern A (hereinafter referred to as a non-alternating pattern), and the fourth counter detects four consecutive non-alternating patterns. .

Like the first counter 10, the third counter 14 is a 3-bit binary counter and has a clock (CL
K) is counted. At the R terminal of the third counter 14,
The CO output of the first counter 10 is input. Therefore, when the count value of the third counter 14 becomes 8,
This means that the 8-bit digital signal input so far did not match the alternating pattern A. Because
If the input 8-bit digital signal matches the alternating pattern A, the first pattern is detected when the match is detected.
This is because the CO output of the counter 10 becomes "1", which resets the third counter 14.

The CO output of the third counter 14 is the fourth
It is input to the E terminal of the counter 16. 4th counter 16
Counts the number of consecutive non-alternating patterns by the same operation as the second counter 12 described above. Here, the fourth counter 16 is a 2-bit binary counter, and when the count value of the fourth counter 16 becomes 4, that is, when the non-alternating pattern A continues four times in the input digital signal, the CO output is " 1 ”.

The CO output of the fourth counter 16 is input to the R terminal of the alarm detection circuit 30. Therefore, during transmission of the alarm detection signal, when the non-alternating pattern A continues four times in the input digital signal, the Q output of the alarm detection circuit 30 becomes "0" and the alarm detection signal is released.

The input digital signal is an alternating pattern A.
In order to reset the count value of the fourth counter 16 when it coincides with, the CO output of the first counter 10 is input to the R terminal of the fourth counter 16.

The first embodiment of the present invention has been described above. According to the first embodiment, it becomes possible to detect the alternating pattern and set / cancel the alarm detection signal with a circuit scale smaller than the conventional one.

Although the above example is an example of detecting the 8-bit alternating pattern A, the circuit configuration of this embodiment is as follows.
It can be easily extended to the detection of alternating patterns with other numbers of bits. For example, in order to detect a 2 ^m- bit alternating pattern in which 1 and 0 alternately appear every 2 ^m-1 bits, an m-bit binary counter is used as the first counter 10,
The decoded output of the most significant bit of the counter may be input to the XOR circuit 20 as the reference signal a. Also, "1
The configuration of this embodiment is also effective in the case of an alternating pattern in which the number of bits is not 2 ^m , such as 11000 ". In this case, for example, by adding a simple logic circuit to the output of the first counter 10, the counter 10 It is only necessary to generate a reference signal that is inverted when counting up to half of the alternating pattern and use this for comparison with the input digital signal.

Although the circuit configuration of FIG. 1 is for detecting an alternating pattern starting from 1, an alternating pattern starting from 0 (for example, "00001" can be easily changed.
111 ″) can be detected. This can be achieved by changing the XOR circuit 20 to an inclusive AND, for example, and the first counter 10
XOR circuit 2 by inverting the decoding QC of the most significant bit of
It can also be achieved by entering 0.

Further, in the above example, the alarm detection signal is set by repeating the alternating pattern eight times, and the alarm detection signal is set to four times the non-alternating pattern.
Although the alarm detection signal is released by continuous number of times, it is also possible to adopt a configuration in which the number of times of pattern continuation, which is a condition for setting and releasing this alarm detection signal, can be changed. For this purpose, a switch for changing the setting of the initial states of the second counter 12 and the fourth counter 16 may be provided. For example, the switches are used to set the initial state of the second counter 12 to QA = QB = 0 and QC =
When set to 1, the alarm detection signal can be set by four consecutive alternating patterns.

Further, in the above example, each counter is configured to count the clock having the frequency equal to the bit rate of the input digital signal, but the clock is not limited to this, and the clock is not limited to the input digital signal. It only has to have a certain synchronization relationship. In this case, it is needless to say that the number of bits (number of stages) of the counter needs to be adjusted according to the frequency ratio of the input digital signal and the clock.

Embodiment 2. The alternating pattern A "11"
Consider a case where the alternating pattern A is input after "... 01" at the time of detecting 110000 ". From the beginning, the input signal sequence is" ... 01111100 ".
In this case, in the first embodiment, counting starts from the first "1" input, and the output of the XOR circuit outputs "5" when the fifth bit "1" is input. It becomes 0 "and the first counter 10 is reset. Therefore, although the alternating pattern A is included in the input digital signal, the alternating pattern A is not detected.

The second embodiment has a structure for preventing the omission of the alternating pattern due to the influence of the signal immediately before the alternating pattern.

FIG. 3 is an explanatory diagram showing the circuit configuration of the second embodiment. 3, the same components as those of FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In this configuration, when it is detected that the logical value "1" of the first half of the alternating pattern A is input by 4 bits and the signal of the logical value "1" is further input, the first counter 10 The count-up operation is temporarily stopped while maintaining the state (count value) of. Then, when the signal having the logical value "0" in the latter half of the alternating pattern A is input, the count-up operation is restarted from the held state. As a result, the extra signal "1" generated by the signal immediately before the alternating pattern A is skipped, so to speak, and therefore the presence or absence of the alternating pattern A detection is detected by the CO signal of the first counter 10 as in the first embodiment. I can know.

In order to realize such an operation, in the configuration of FIG. 3, the AND circuit 22 first detects the first half “1111” of the alternating pattern A. In the AND circuit 22,
The decoded output (Q output of each flip-flop inside the counter) of each bit of the first counter 10 which is a 3-bit binary counter is input. Where the least significant bit Q
A and the middle bit QB are inverted and input to the AND circuit 22,
The most significant bit QC is directly input to the AND circuit 22. Therefore, the output of the AND circuit 22 has the logical value "1" when the state of the first counter 10 is QC = 1 and QB = QA = 0. At this timing, when the first counter 10 counts four clocks,
That is, it corresponds to the case where the first half “1111” of the alternating pattern A is detected. In this way, it can be determined from the output of the AND circuit 22 whether or not the first half of the alternating pattern A has been detected.

The AND circuit 24 calculates the logical sum of the output of the AND circuit 22 and the input digital signal. The first half “1111” of the alternating pattern A is detected and the AND circuit 22
When the digital signal of the logical value "1" is further input after the output of "1" becomes "1", the output of the AND circuit 24 becomes "1". Then, while the output of the AND circuit 24 is "1", the E input of the first counter 10 is "0", so that the first counter 10 does not count the clock during this period.

During this period, the reference signal a (= QC) is "1" and the input digital signal is "1".
The output of the R circuit 20 becomes "0". Therefore, as in the configuration of FIG.
When input to the R terminal of, the first counter 10 is reset. Therefore, in the circuit configuration of FIG. 3, the logical sum of the output of the XOR circuit 20 and the output of the AND circuit 24 is input to the R terminal of the first counter 10. AND
The circuit 26 is logically equivalent to an OR circuit because the inversion of the output of the XOR circuit 20 and the inversion of the output of the AND circuit 24 are input and the logical product of them is inverted and output.
Therefore, the output of the AND circuit 26 is the output of the XOR circuit 20.
Is "0", the AND circuit 24 outputs "1" if the output is "1". According to this configuration, the first counter 10 is not reset when "1" is further input after the digital signal sequence "1111" is input.

As can be seen from the above description, according to the circuit configuration of FIG. 3, when the "1" signal is further input after "1111", the first counter 10 is not reset. , The counting operation is stopped while keeping the internal state. Therefore, even if the clock is input during that time, the first
Since the internal state of the counter 10 does not change, the output of the AND circuit 22 becomes "1" even at the next timing. Therefore, the state of the first counter 10 does not change while "1" is continuously input after the first half of the alternating pattern A is detected.

However, when the digital signal "0" is input thereafter, the output of the AND circuit 24 becomes "0",
As a result, the E input of the first counter 10 becomes "1", and the first counter 10 can count. At this time, the output of the XOR circuit 20 becomes 1 (since QC = 1 and input = 0), so the output of the AND circuit 26 remains "1", and the first counter 10 is not reset,
The counting operation is restarted from the internal state held until then.

As described above, according to the circuit configuration of FIG. 3, since the first counter 10 skips the extra signal "1" and counts, the CO output of the first counter when the count value reaches eight. "1" is a signal indicating that the alternating pattern A has been detected.

As described above, according to the second embodiment, even when the alternating pattern is input subsequent to the signal having the first half value of the alternating pattern, the alternating pattern can be detected. .

The other components of FIG. 3 are the same as those of FIG. Therefore, according to the circuit of FIG.
As with the circuit of FIG. 1, the alarm detection signal can be set / released.

Embodiment 3. In the first and second embodiments, “11
The object of the present embodiment is to detect an alternating pattern in which the same number of 1's and 0's such as 110000 "appear alternately. On the other hand, in the present embodiment, a certain unit pattern and an inverted pattern of the unit pattern are The purpose is to detect alternating patterns that appear alternately.

FIG. 4 is an explanatory diagram showing the circuit configuration of the third embodiment. 4, the same components as those of FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 4, the output of the XOR circuit 20 is input to the unit pattern detection circuit 40, and the inverted output of the unit pattern detection circuit 40 is input to the R terminal of the first counter 10.

The unit pattern detection circuit 40 sequentially compares the input signal with the unit pattern for each bit, outputs "1" while the input signal matches the unit pattern, and inputs the signal. It is a circuit that outputs "0" when the signal does not match the unit pattern.

The flow of detection of the alternating pattern in the circuit configuration of FIG. 4 is as follows: the unit pattern "1101" and its inverted pattern "0010" appear alternately.
The detection of “010010” (hereinafter referred to as the alternating pattern B) will be described as an example (note that in the present embodiment, “1
There is no essential difference in regard to either 101 "or" 0010 "as a unit pattern).

When digital signals having the alternating pattern B are sequentially input to the circuit of FIG. 4, the decode output QC of the most significant bit of the first counter 10 is "0" at first, so that the XOR circuit 20 sequentially outputs "0". 1101 ″ is output. Since this output pattern matches the unit pattern "1101", the unit pattern detection circuit 40 outputs the logical value "1" during this period. Therefore, the first counter 10 continues to count up during this period. Then, when the first half of the alternating pattern B is input and the count value of the first counter 10 reaches 4, the decode output QC becomes "1". After this, the input digital signal is "0010.
.. ”, the XOR circuit 20 also outputs“ 1101 ”in order. Therefore, in this case as well, the unit pattern detection circuit 40 continues to output“ 1 ”, and the first counter 10 further counts. Therefore, when the CO output of the first counter becomes "1", it means that the input digital signal continuously matches the alternating pattern B for 8 bits, and the CO output "1" becomes the alternating pattern. It becomes the detection signal of B.

If the input digital signal does not match the alternating pattern B during the counting up, the output of the unit pattern detection circuit 40 becomes "0" and the first counter 10 is reset to the initial state. It

The other components of FIG. 4 are the same as those of FIG. Therefore, according to the circuit configuration of FIG. 4, as with the case of FIG. 1, the alarm detection signal can be set / released.

As described above, according to the third embodiment, it is possible to detect the alternating pattern in which the unit pattern and its inverted pattern appear alternately.

The circuit configuration of FIG. 4 can be easily expanded to an alternating pattern in which the same number of unit patterns and their inverted patterns alternately appear. For example, "11011101
00100010 is an alternating pattern in which the unit pattern "1101" and the inverted pattern "0010" appear twice each. To detect this alternating pattern, for example, the first counter 10 is replaced with a 4-bit binary counter, and the X as the reference signal using the high-order bit decoded output QD
The configuration may be such that it is input to the OR circuit 20. in this case,
As the unit pattern detection circuit 40, a circuit that outputs “1” while the input signal matches “1101” can be used as it is.

Embodiment 4. The fourth embodiment aims at detecting a pattern in which two patterns having the same number of bits (hereinafter, referred to as a first pattern and a second pattern) appear alternately.

FIG. 5 is an explanatory diagram showing the circuit configuration of the fourth embodiment. 5, the same components as those of FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The configuration shown in FIG. 5 targets a signal pattern in which a 4-bit first pattern and a second pattern are alternately repeated. In FIG. 5, the input digital signal is first input to the preprocessing circuit 50. The pre-processing circuit 50 outputs 4-bit "1" (that is, "1" is output during a 4-bit period) when the first pattern is detected from the input digital signal, and the pre-processing circuit 50 outputs the first pattern from the input digital signal. When two patterns are detected, 4-bit "0" is output. Therefore, while the first pattern and the second pattern are alternately input, the preprocessing circuit 50 outputs "1".
111 "and" 0000 "are output alternately.
When the pattern of the input digital signal deviates from the repetition of the first pattern and the second pattern, the preprocessing circuit 50
Output deviates from the alternating pattern of “1111” and “0000”. The output of the preprocessing circuit 50 is input to the XOR circuit 20.

As for the circuit configuration after the XOR circuit 20, FIG. 5 has exactly the same configuration as FIG. Therefore, in the configuration of FIG. 5, the first counter 10 and the XOR circuit 2
By detecting the pattern of "11110,000" by the action of 0, the input digital signal becomes the first and second digital signals.
It is possible to detect whether or not the pattern is repeated.

The preprocessing circuit 50 in FIG. 5 can be easily constructed by a simple logic circuit. FIG. 6 shows an example of the preprocessing circuit 50. An example of the preprocessing circuit shown in FIG.
First pattern "0101" and second pattern "1001"
The circuit configuration used to detect a pattern in which and appear alternately is shown.

In FIG. 6, the input digital signal is input to the data input terminal (IN) of the shift register 52. The shift register 52 is a serial-in / parallel-out 4-bit shift register. The shift register 52 shifts data according to a clock (CLK). In addition, this clock (CLK) is
Is the same as that supplied to each of the counters 10 to 16.

The QA to QD outputs of the shift register 52 are
Each of the two branches is input to AND circuits 54 and 56. The AND circuit 54 is a circuit for detecting the pattern "0101", and the AND circuit 56 is a circuit for detecting the pattern "1001".

The output of the AND circuit 54 is input to the S terminal of the RS flip-flop 58, and the output of the AND circuit 56 is input to the R terminal. The Q output of the RS flip-flop 58 becomes the output of the preprocessing circuit 50.

Consider a case where digital signals are input to the shift register 52 in the order of "010111001 ..." In the circuit configuration as described above. This digital signal sequence is sequentially input, and when the last "1" of "0101" is input, the output of the AND circuit 54 becomes "1".
This output sets the RS flip-flop 58 and the Q output becomes "1". Then, the RS flip-flop 58 maintains Q = 1 until "1" is input to the R terminal next time. In the configuration of FIG. 6, RS
By controlling the enable signal of the flip-flop 58, when "0101" or "1001" is detected, the internal state of the RS flip-flop 58 does not change until 4 bits later (4 clocks later). Therefore, R is kept for 4 clocks after "0101" is detected.
"1" is output from the S flip-flop 58.

When four clocks elapse after the detection of "0101", the output of the shift register 52 becomes "1001" and the output of the AND circuit 56 becomes "1". At this time, the RS flip-flop 58 can be operated again by the enable signal, and the AND circuit 5
The state is changed by the output "1" of 6 and the Q output becomes "0".

As can be seen from the above description, while the pattern "0101" and "1001" are alternately repeated in the input digital signal, the output of the preprocessing circuit 50 is "1111" and "0000". It is an alternating pattern that repeats alternately. Therefore, by inputting the output of the pre-processing circuit 50 into the same circuit configuration as that of the first embodiment and detecting the alternating pattern "11110000", "01" is obtained.
A pattern in which "01" and "1001" alternately appear can be detected.

When the input digital signal deviates from the pattern in which "0101" and "1001" appear alternately, the change in the Q output of the RS flip-flop 58 deviates from the 4-bit period, and therefore the preprocessing circuit 50 Output does not match the alternating pattern "1110000". Therefore, the input digital signals are "0101" and "100".
If the pattern of "1" and the pattern appearing alternately, the first counter 10 and the second counter 12 are reset in the configuration of FIG.

As described above, according to the fourth embodiment, it is possible to detect a pattern in which two types of patterns having the same number of bits appear alternately.

The other components in FIG. 5 are the same as those in FIG. Therefore, even with the circuit configuration of FIG.
As in the case of FIG. 1, it is possible to set / cancel the alarm detection signal.

[0109]

As described above, according to the first configuration of the present invention, it is possible to detect an alternating pattern in which 1 and 0 alternately appear every n bits with a circuit scale smaller than that of the conventional configuration.

Further, according to the second configuration of the present invention, even when the alternating pattern is input subsequent to the signal having the first half value of the alternating pattern, the alternating pattern can be detected.

Further, according to the third structure of the present invention, it is possible to detect an alternating pattern in which the same number of unit patterns and their inverted patterns alternately appear in a small circuit scale.

Further, according to the fourth configuration of the present invention, it is possible to detect a predetermined pattern in which the first and second patterns of n bits alternate, with a small circuit scale.

Further, according to the fifth configuration of the present invention, it can be detected that a predetermined (alternating) pattern in the input digital signal is continuous by a predetermined set value.

Further, according to the sixth configuration of the present invention, it becomes possible to change the number of times of alternating pattern continuation, which is a condition for issuing a continuous coincidence signal.

Further, according to the seventh configuration of the present invention, the alarm detection signal is issued only when the predetermined pattern is continuously input a predetermined number of times or more, and the alarm detection signal once issued is the predetermined pattern. If the pattern that does not match with is not input continuously more than a predetermined number of times, it cannot stop.
False alarm detection can be prevented.

According to the eighth configuration of the present invention, it is possible to change the number of consecutive alternating pattern pattern disagreements which is a condition for alarm release.

[Brief description of drawings]

FIG. 1 is a first embodiment of a pattern detection circuit according to the present invention.
FIG. 3 is an explanatory diagram showing a circuit configuration of FIG.

FIG. 2 is a time chart of signals at various points in the first embodiment.

FIG. 3 is a second embodiment of the pattern detection circuit according to the present invention.
FIG. 3 is an explanatory diagram showing a circuit configuration of FIG.

FIG. 4 is a third embodiment of the pattern detection circuit according to the present invention.
FIG. 3 is an explanatory diagram showing a circuit configuration of FIG.

FIG. 5 is a fourth embodiment of the pattern detection circuit according to the present invention.
FIG. 3 is an explanatory diagram showing a circuit configuration of FIG.

FIG. 6 is an explanatory diagram showing an example of a configuration of a preprocessing circuit according to a fourth embodiment.

FIG. 7 is an explanatory diagram showing a configuration of a conventional alarm detection circuit.

[Explanation of symbols]

10 1st counter, 12 2nd counter, 14 3rd
Counter, 16 fourth counter, 20 XOR circuit, 2
2 to 26 AND circuit, 30 alarm detection circuit, 40 unit pattern detection circuit, 50 preprocessing circuit.

Claims (8)

[Claims] 1. A pattern detection circuit for detecting a predetermined alternating pattern in which 1 and 0 alternately appear every n bits from an input digital signal, and having a predetermined synchronization relationship with the input digital signal. A counter that counts clocks and outputs a reference signal having a pattern corresponding to the predetermined alternating pattern, and the reference signal and the input digital signal are input, and the input digital signal is compared with the counter by the predetermined alternating pattern. And a reset signal generator that supplies a reset signal to the counter when the input digital signal does not match the predetermined alternating pattern, and the count value of the counter is Pattern detection that outputs a pattern detection signal when the input digital signal has a bit period of 2n An output signal generation unit, and a pattern detection circuit having: 2. The pattern detection circuit according to claim 1, wherein when the count value of the counter reaches n in a bit cycle unit of the input digital signal, the first half n bits of the predetermined alternating pattern are detected. A pattern front half detection unit that outputs a front half detection signal indicating, and the input digital signal and the front half detection signal are input,
While the digital signal having the logical value of the first half is still input after the first half detection signal is input,
A count stop signal generation unit that outputs a count stop signal to the counter; and the counter temporarily suspends the count operation while holding the count value while the count stop signal is input. A pattern detection circuit characterized by. 3. A unit pattern and its inverted pattern alternately appearing in the same number 2n from an input digital signal.
A pattern detection circuit for detecting a predetermined alternating pattern of bits, wherein a clock having a predetermined synchronous relationship with an input digital signal is counted, and a reference signal having a pattern in which 1 and 0 alternately appear every n bits. A counter for outputting, the reference signal and the input digital signal are input, and the input digital signal is input while the input digital signal matches the predetermined alternating pattern by obtaining an exclusive OR of the two signals. A pattern conversion unit that converts and outputs the repeated unit pattern, and compares the output of the pattern conversion unit with the repeated unit pattern, and generates a reset signal that supplies a reset signal to the counter when the two do not match. And a count value of the counter becomes 2n in a bit cycle unit of the input digital signal. And a pattern detection signal generator that outputs a pattern detection signal when the pattern detection signal is generated. 4. A pattern detection circuit for detecting, from an input digital signal, a predetermined pattern in which first and second patterns of n bits alternately appear, wherein the input digital signal is input to the pattern detection circuit. Logical value 1 (0) when the first pattern is detected from the signal
Signal is continuously output for n bits and a logical value of 0 is output when the second pattern is detected from the input digital signal.
A preprocessing circuit that continuously outputs the signal of (1) for n bits and a clock that has a predetermined synchronization relationship with the input digital signal are counted, and a pattern in which 1 and 0 alternately appear every n bits A counter that outputs a reference signal, a reset signal generation unit that supplies a reset signal to the counter when the reference signal and the output signal of the preprocessing circuit are input, and the two do not match, and the count of the counter A pattern detection circuit, which outputs a pattern detection signal indicating that the predetermined pattern has been detected when the value becomes 2n in a bit cycle unit of the input digital signal. 5. The pattern detection circuit according to claim 1, which is connected to outputs of the pattern detection signal generation unit and the reset signal generation unit and counts the pattern detection signal,
A second counter that clears a count value when the reset signal is input; and a continuous match signal generation unit that outputs a continuous match signal when the count value of the second counter reaches a predetermined set value. A pattern detection circuit having. 6. The pattern detection circuit according to claim 5, further comprising a coincidence consecutive number set value varying means for varying a set value in the consecutive coincidence signal generating section. 7. The pattern detection circuit according to claim 5, wherein the pattern detection signal generator is connected, counts clocks having a predetermined synchronization relationship with the input digital signal, and outputs the pattern detection signal. And a third counter whose count value is cleared when is input, and the input digital signal does not match the predetermined alternating pattern when the count value of the third counter becomes 2n in a bit cycle unit of the input digital signal. The pattern non-matching signal generator that outputs the pattern non-matching signal that indicates that the pattern non-matching signal is connected to the pattern detection signal generator and the pattern non-matching signal generator, and the pattern detection signal is input. And a count value of the fourth counter is cleared. When the set value of the continuous mismatch signal is output, the continuous mismatch signal generation unit is connected to the continuous match signal generation unit and the continuous mismatch signal generation unit, and the alarm detection signal is input when the continuous match signal is input. And a warning detection unit that keeps outputting a warning detection signal until the continuous disagreement signal is input. 8. The pattern detection circuit according to claim 7, further comprising: discontinuity consecutive number set value varying means for varying a set value in the consecutive disagreement signal generation unit.