JPH098137A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH098137A JPH098137A JP17662695A JP17662695A JPH098137A JP H098137 A JPH098137 A JP H098137A JP 17662695 A JP17662695 A JP 17662695A JP 17662695 A JP17662695 A JP 17662695A JP H098137 A JPH098137 A JP H098137A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- semiconductor device
- wiring layer
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】
【目的】層間絶縁膜に用いられるSOG膜から装置内部
に水分が拡散して素子特性を劣化させることを防止す
る。
【構成】金属配線13の上に形成したCVD酸化膜14
の上に非晶質シリコン又は多結晶シリコンからなる絶縁
膜15を形成する。その上に、段差軽減のためのSOG
膜16を塗布形成し、更にその上にCVD酸化膜17を
形成して、多層構造の層間絶縁膜を形成する。
【効果】非晶質シリコン又は多結晶シリコンからなる絶
縁膜15が水分のバリア膜となって、SOG膜16から
の水分が装置内部に拡散することを防止する。
(57) [Abstract] [Purpose] To prevent deterioration of element characteristics due to diffusion of water from the SOG film used as an interlayer insulating film into the inside of the device. [Structure] CVD oxide film 14 formed on metal wiring 13
An insulating film 15 made of amorphous silicon or polycrystalline silicon is formed on the above. On top of that, SOG for step reduction
A film 16 is formed by coating, and a CVD oxide film 17 is further formed thereon to form an interlayer insulating film having a multilayer structure. [Effect] The insulating film 15 made of amorphous silicon or polycrystalline silicon serves as a moisture barrier film, and prevents moisture from the SOG film 16 from diffusing into the inside of the device.
Description
【0001】[0001]
【産業上の利用分野】本発明は、配線層とその配線層の
上に形成された層間絶縁膜とを有する半導体装置及びそ
の製造方法に関し、例えば、多層配線構造の半導体装置
及びその製造方法に適用して特に好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wiring layer and an interlayer insulating film formed on the wiring layer and a method for manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same. It is particularly suitable for application.
【0002】[0002]
【従来の技術】従来、半導体装置における多層配線間の
層間絶縁膜には、TEOS(tetraethyl orthosilicat
e) を原料とするプラズマCVD法による膜と、段差を
緩和するためのSOG(spin-on-glass)等の液体塗布膜
とが用いられている。2. Description of the Related Art Conventionally, TEOS (tetraethyl orthosilicat
A film formed by plasma CVD using e) as a raw material, and a liquid coating film such as SOG (spin-on-glass) for alleviating a step difference are used.
【0003】図2に、従来の半導体装置の製造方法を示
す。FIG. 2 shows a conventional method of manufacturing a semiconductor device.
【0004】図2(a)に示すように、半導体基板21
上に常圧CVD法等で酸化膜22を形成した後、金属膜
23をスパッタ法で成膜する。その後、フォトリソ技術
及びドライエッチングにより金属膜23をパターニング
して、配線層23を形成する。その後、TEOSを用い
たプラズマCVD法により絶縁膜24を形成する。As shown in FIG. 2A, the semiconductor substrate 21
After the oxide film 22 is formed thereon by the atmospheric pressure CVD method or the like, the metal film 23 is formed by the sputtering method. Then, the metal film 23 is patterned by photolithography and dry etching to form the wiring layer 23. After that, the insulating film 24 is formed by the plasma CVD method using TEOS.
【0005】このプラズマCVD法により形成した絶縁
膜24は段差被覆率が悪いために、その上に直接次の配
線層を形成すると、その配線層のフォトリソでの焦点深
度が足りなくなったり、ドライエッチング時に段差低部
で配線がショートすることがあるため、段差を緩和する
必要がある。Since the insulating film 24 formed by this plasma CVD method has a poor step coverage, if the next wiring layer is formed directly thereon, the depth of focus of the wiring layer by photolithography becomes insufficient, or dry etching is performed. Sometimes the wiring is short-circuited at the lower part of the step, so it is necessary to reduce the step.
【0006】そこで、図2(b)に示すように、絶縁膜
24上にSOG等の液体塗布膜25を回転塗布すること
で形成し、段差を緩和する。その後、液体塗布膜25を
アニールし、更に、必要に応じて、余分な液体塗布膜2
5をエッチバックする。その後、TEOSを用いたプラ
ズマCVD法により絶縁膜26を形成して、絶縁膜2
4、液体塗布膜25及び絶縁膜26からなる層間絶縁膜
を形成する。Therefore, as shown in FIG. 2B, a liquid coating film 25 of SOG or the like is formed on the insulating film 24 by spin coating to alleviate the step. After that, the liquid coating film 25 is annealed and, if necessary, an extra liquid coating film 2 is added.
Etch back 5. After that, the insulating film 26 is formed by the plasma CVD method using TEOS, and the insulating film 2 is formed.
4. An interlayer insulating film including the liquid coating film 25 and the insulating film 26 is formed.
【0007】その後、図2(c)に示すように、金属膜
27をスパッタ法で成膜し、それをフォトリソ技術及び
ドライエッチングによりパターニングして、配線層27
を形成する。その後、必要に応じて、保護膜28をPS
G(phospho-silicate glass) 、プラズマSiN等で形
成する。After that, as shown in FIG. 2C, a metal film 27 is formed by a sputtering method, and the metal film 27 is patterned by a photolithography technique and dry etching to form a wiring layer 27.
To form After that, if necessary, the protective film 28 is covered with PS.
It is formed of G (phospho-silicate glass), plasma SiN, or the like.
【0008】[0008]
【発明が解決しようとする課題】しかしながら、上述し
た従来の構成では、液体塗布膜25自体が水分を含んだ
膜であるため、液体塗布膜25を形成した後に実施され
る各種熱処理工程や、或いは半導体装置の動作時に、液
体塗布膜25中の水分が半導体装置内部に拡散し、例え
ば、トランジスタ特性を劣化させて、信頼性の低い半導
体装置になるという問題があった。However, in the above-mentioned conventional structure, since the liquid coating film 25 itself is a film containing water, various heat treatment steps performed after the liquid coating film 25 is formed, or During operation of the semiconductor device, there is a problem that water in the liquid coating film 25 diffuses inside the semiconductor device and deteriorates, for example, transistor characteristics, resulting in a semiconductor device having low reliability.
【0009】液体塗布膜25は、一般に、700℃程度
の高温を加えれば膜中の水分はなくなるが、多層配線構
造の殆どはAlによる配線であるため、そのような高温
処理を実施することは困難であった。The liquid coating film 25 generally loses water content when a high temperature of about 700 ° C. is applied, but since most of the multilayer wiring structure is wiring made of Al, such high temperature treatment is not possible. It was difficult.
【0010】そこで、本発明の目的は、液体塗布膜中の
水分が半導体装置内に拡散することを防止できる信頼性
の高い半導体装置及びその製造方法を提供することであ
る。Therefore, an object of the present invention is to provide a highly reliable semiconductor device capable of preventing moisture in a liquid coating film from diffusing into the semiconductor device and a method for manufacturing the same.
【0011】[0011]
【課題を解決するための手段】上述した課題を解決する
ために、本発明の半導体装置の製造方法は、配線層を備
えた半導体基板上に層間絶縁膜を形成する半導体装置の
製造方法において、前記配線層の上に第1の絶縁膜を形
成する工程と、前記第1の絶縁膜の上に、非晶質シリコ
ン又は多結晶シリコンからなる第2の絶縁膜を形成する
工程と、前記第2の絶縁膜の上に、液体原料を塗布して
第3の絶縁膜を形成する工程と、前記第3の絶縁膜の上
に第4の絶縁膜を形成する工程とを有する。In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which an interlayer insulating film is formed on a semiconductor substrate having a wiring layer, Forming a first insulating film on the wiring layer; forming a second insulating film made of amorphous silicon or polycrystalline silicon on the first insulating film; The method includes a step of applying a liquid material on the second insulating film to form a third insulating film, and a step of forming a fourth insulating film on the third insulating film.
【0012】また、本発明の半導体装置は、配線層とそ
の配線層の上に形成された層間絶縁膜とを有する半導体
装置において、前記層間絶縁膜が、少なくとも、塗布形
成による第1の絶縁膜層と、前記第1の絶縁膜層と前記
配線層との間に非晶質シリコン又は多結晶シリコンから
なる第2の絶縁膜層とを有する。The semiconductor device of the present invention is a semiconductor device having a wiring layer and an interlayer insulating film formed on the wiring layer, wherein the interlayer insulating film is at least a first insulating film formed by coating. A layer, and a second insulating film layer made of amorphous silicon or polycrystalline silicon between the first insulating film layer and the wiring layer.
【0013】[0013]
【作用】本発明においては、段差を緩和するために層間
絶縁膜に用いられる塗布形成膜とその下の配線層との間
に非晶質シリコン又は多結晶シリコンからなる絶縁膜を
設けて、塗布形成膜からの水分が装置内部に拡散するこ
とを防止する。In the present invention, an insulating film made of amorphous silicon or polycrystalline silicon is provided between the coating forming film used for the interlayer insulating film and the wiring layer thereunder in order to reduce the step, and the coating is performed. It prevents the moisture from the formed film from diffusing into the inside of the device.
【0014】[0014]
【実施例】以下、本発明を一実施例につき図1を参照し
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will be described below with reference to FIG.
【0015】まず、図1(a)に示すように、シリコン
半導体基板11上に常圧CVD法によりシリコン酸化膜
12を厚さ500〜1000nm形成した後、Al又は
Al合金からなる金属膜13をスパッタ法で厚さ400
〜600nm成膜する。その後、フォトリソ技術及びド
ライエッチングにより金属膜13をパターニングして、
配線層13を形成する。その後、TEOSを用いたプラ
ズマCVD法により絶縁膜14を200〜400nmの
厚さに形成する。First, as shown in FIG. 1A, a silicon oxide film 12 having a thickness of 500 to 1000 nm is formed on a silicon semiconductor substrate 11 by an atmospheric pressure CVD method, and then a metal film 13 made of Al or an Al alloy is formed. Thickness 400 by sputtering method
A film is formed up to 600 nm. After that, the metal film 13 is patterned by photolithography and dry etching,
The wiring layer 13 is formed. After that, the insulating film 14 is formed to a thickness of 200 to 400 nm by the plasma CVD method using TEOS.
【0016】次に、図1(b)に示すように、スパッタ
法で非晶質シリコン膜15を50〜150nm成膜す
る。Next, as shown in FIG. 1B, an amorphous silicon film 15 is formed to a thickness of 50 to 150 nm by a sputtering method.
【0017】次に、図1(c)に示すように、非晶質シ
リコン膜15の上にSOG等の液体塗布膜16を回転塗
布することで100〜1000nmの膜厚に形成し、段
差を緩和する。その後、液体塗布膜16を400〜45
0℃でアニールし、更に、必要に応じて、余分な液体塗
布膜16をエッチバックする。その後、TEOSを用い
たプラズマCVD法により絶縁膜17を400〜600
nmの膜厚に形成して、CVD絶縁膜14、非晶質シリ
コン膜15、液体塗布膜16及びCVD絶縁膜17の積
層構造からなる層間絶縁膜を形成する。Next, as shown in FIG. 1C, a liquid coating film 16 such as SOG is spin-coated on the amorphous silicon film 15 to form a film having a thickness of 100 to 1000 nm, and a step is formed. ease. Then, the liquid coating film 16 is set to 400 to 45.
Annealing is performed at 0 ° C., and excess liquid coating film 16 is etched back if necessary. After that, the insulating film 17 is formed by the plasma CVD method using TEOS at 400 to 600.
An interlayer insulating film having a laminated structure of the CVD insulating film 14, the amorphous silicon film 15, the liquid coating film 16 and the CVD insulating film 17 is formed to a film thickness of nm.
【0018】その後、図1(d)に示すように、Al又
はAl合金からなる金属膜18をスパッタ法で600〜
900nm成膜し、それをフォトリソ技術及びドライエ
ッチングによりパターニングして、配線層18を形成す
る。その後、必要に応じて、保護膜28をPSG又はプ
ラズマSiNで400〜1500nmの膜厚に形成す
る。Thereafter, as shown in FIG. 1D, a metal film 18 made of Al or an Al alloy is formed by sputtering to a thickness of 600 to 600 nm.
A film having a thickness of 900 nm is formed and patterned by a photolithography technique and dry etching to form the wiring layer 18. After that, the protective film 28 is formed with PSG or plasma SiN to a film thickness of 400 to 1500 nm, if necessary.
【0019】以上に説明したように、本実施例の構成で
は、液体塗布膜16の下に、水分のバリア膜として非晶
質シリコン膜15を形成しているので、後の各種熱処理
時又は装置の動作時に、液体塗布膜16からの水分が装
置内部に拡散することが効果的に防止され、その結果、
トランジスタ特性の劣化等を招かないので、半導体装置
の信頼性が向上する。As described above, in the structure of this embodiment, since the amorphous silicon film 15 is formed as the moisture barrier film under the liquid coating film 16, it is used in various heat treatments or in the subsequent apparatus. The water from the liquid coating film 16 is effectively prevented from diffusing into the inside of the device during the operation of, and as a result,
Since the transistor characteristics are not deteriorated, the reliability of the semiconductor device is improved.
【0020】なお、水分のバリア膜としては、上述した
実施例の非晶質シリコン膜15の代わりに多結晶シリコ
ン膜を用いることもできる。As the moisture barrier film, a polycrystalline silicon film may be used instead of the amorphous silicon film 15 of the above-mentioned embodiment.
【0021】[0021]
【発明の効果】本発明によれば、段差軽減のために層間
絶縁膜に用いられる液体塗布膜からの水分が装置内部に
拡散することが効果的に防止されるので、その拡散した
水分による素子特性の劣化が防止されて、半導体装置の
信頼性が向上する。According to the present invention, it is possible to effectively prevent the moisture from the liquid coating film used for the interlayer insulating film from diffusing into the inside of the device in order to reduce the step. The deterioration of the characteristics is prevented, and the reliability of the semiconductor device is improved.
【図1】本発明の一実施例による半導体装置の製造方法
を工程順に示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【図2】従来の半導体装置の製造方法を工程順に示す概
略断面図である。FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.
11 シリコン半導体基板 12 絶縁膜 13 配線層 14 絶縁膜 15 非晶質シリコン膜 16 液体塗布膜 17 絶縁膜 18 配線層 19 保護膜 11 Silicon Semiconductor Substrate 12 Insulating Film 13 Wiring Layer 14 Insulating Film 15 Amorphous Silicon Film 16 Liquid Coating Film 17 Insulating Film 18 Wiring Layer 19 Protective Film
Claims (2)
膜を形成する半導体装置の製造方法において、 前記配線層の上に第1の絶縁膜を形成する工程と、 前記第1の絶縁膜の上に、非晶質シリコン又は多結晶シ
リコンからなる第2の絶縁膜を形成する工程と、 前記第2の絶縁膜の上に、液体原料を塗布して第3の絶
縁膜を形成する工程と、 前記第3の絶縁膜の上に第4の絶縁膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which an interlayer insulating film is formed on a semiconductor substrate having a wiring layer, the method comprising: forming a first insulating film on the wiring layer; A step of forming a second insulating film made of amorphous silicon or polycrystalline silicon on the first insulating film, and a step of forming a third insulating film by applying a liquid material on the second insulating film And a step of forming a fourth insulating film on the third insulating film, the method of manufacturing a semiconductor device.
間絶縁膜とを有する半導体装置において、 前記層間絶縁膜が、少なくとも、塗布形成による第1の
絶縁膜層と、前記第1の絶縁膜層と前記配線層との間に
非晶質シリコン又は多結晶シリコンからなる第2の絶縁
膜層とを有することを特徴とする半導体装置。2. A semiconductor device having a wiring layer and an interlayer insulating film formed on the wiring layer, wherein the interlayer insulating film is at least a first insulating film layer formed by coating and the first insulating film layer. A semiconductor device having a second insulating film layer made of amorphous silicon or polycrystalline silicon between the insulating film layer and the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17662695A JPH098137A (en) | 1995-06-20 | 1995-06-20 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17662695A JPH098137A (en) | 1995-06-20 | 1995-06-20 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH098137A true JPH098137A (en) | 1997-01-10 |
Family
ID=16016877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17662695A Withdrawn JPH098137A (en) | 1995-06-20 | 1995-06-20 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH098137A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6317242B1 (en) | 1998-01-09 | 2001-11-13 | Fuji Xerox Co., Ltd. | Optical bus system and signal processor |
| US6366375B1 (en) | 1997-11-10 | 2002-04-02 | Fuji Xerox Co., Ltd. | Optical-signal transmission apparatus and method, and signal processing apparatus |
-
1995
- 1995-06-20 JP JP17662695A patent/JPH098137A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366375B1 (en) | 1997-11-10 | 2002-04-02 | Fuji Xerox Co., Ltd. | Optical-signal transmission apparatus and method, and signal processing apparatus |
| US6317242B1 (en) | 1998-01-09 | 2001-11-13 | Fuji Xerox Co., Ltd. | Optical bus system and signal processor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020903 |