JPH0980121A - Device and method for diagnosing failure of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To estimate the causes of a failure by listing up the failure which may actually occur, performing a circuit simulation assuming the failure, and comparing the simulated result with actually measured value. SOLUTION: A failure list creating unit 6 consists of a layout information unit 1, a process information unit 2, and a failure knowledge database unit 3, thus listing up a failure which is assumed to occur in a possible failure region. One assumed failure is selected from the elements of a failure list 7, circuit information when the assumed failure occurs is created from equivalent circuit information 5, a circuit operation for a possible failure region obtained from circuit operation information 11 is simulated by a circuit simulation 8, and the simulated result is outputted as simulation data 12. A comparison unit 13 compares the circuit operation information 11 with the simulation data 12 and assumes that the assumed failure actually occurs in a failed device 9 when both agree.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit failure diagnosis apparatus and failure diagnosis method, and more particularly to an integrated circuit failure diagnosis apparatus and method for estimating a failure location and failure cause of an integrated circuit by analog circuit simulation using a computer. Regarding

[0002]

2. Description of the Related Art Conventionally, this kind of integrated circuit failure diagnosing device has been used for the purpose of identifying the failure location in order to investigate the cause of failure of the failed integrated circuit.

As a conventional failure diagnosis device, for example, Japanese Patent Laid-Open No.
In the 5-45423 publication, in a failure analysis method for an integrated circuit using an electron beam tester, a certain test pattern is temporarily held and the potential contrast is kept longer than the other test pattern input time. By acquiring the potential contrast image of the integrated circuit at high speed,
There has been proposed a configuration that avoids deterioration of potential contrast due to charge accumulation. In other words, this conventional technique uses an LSI tester to drive an integrated circuit,
The potential contrast image is obtained in synchronism with the driving timing, and at that time, the potential contrast image is obtained while temporarily holding the application state of the test pattern for obtaining the potential contrast image.

[0004]

Further, as a conventional fault diagnosis method based on simulation using a computer, the fault expressed on the logic level circuit is located and its fault such as stuck-at fault or short-circuit fault. Although some contents are estimated, a specific method for estimating the physical location of the failure in the actual device and the physical cause of the failure has not been proposed yet.

On the other hand, in the conventional fault diagnosing method for an integrated circuit described in the above publication, the fault diagnosing is performed only on the basis of physical observation that the wiring potential of the integrated circuit is measured using an electron beam. Recent miniaturization of integrated circuits,
Due to the increase in the number of layers and the increase in density, there is a problem that it becomes difficult to measure a target wiring potential and it becomes impossible to specify a failure location.

Therefore, the present invention solves the above-mentioned problems of the prior art, and provides a failure diagnosis apparatus and method capable of effectively estimating the physical position and the physical cause of the failure in an integrated circuit. The purpose is to do.

[0007]

To achieve the above object, the present invention provides a layout information storage means for storing and holding layout information of a faulty integrated circuit under normal conditions, and an electrical property of the faulty integrated circuit under normal conditions. Process information storage means for storing and holding process information for determining the information, a failure knowledge database part for storing knowledge information about a failure occurring in an integrated circuit in a predetermined database form, and the layout from the layout information storage means. From the information and the process information from the process information storage means,
Circuit extraction means for extracting an equivalent circuit of the faulty integrated circuit when the faulty integrated circuit is normal, and associating the equivalent circuit with a predetermined element when the faulty integrated circuit is normal, the layout information, and the process information. And the knowledge information about the failure in the failure knowledge database unit, a failure candidate group (also referred to as a "failure list") is searched for a failure that may occur in the circuit in the normal state of the failure integrated circuit.
A failure list creating means, a signal measuring means for creating circuit operation information by measuring an electric signal at a predetermined measurement point of the failure integrated circuit, and selecting and assuming a failure from the failure candidate group. A simulation means for simulating a circuit operation when the contingency is present in the equivalent circuit based on the circuit operation information, and a simulation result by the simulation means And a comparison means for comparing the circuit operation information with the circuit operation information.

Further, according to the present invention, (a) an equivalent circuit of the suspected failure area is extracted from layout data of the suspected failure area on the semiconductor integrated circuit device and process information of the semiconductor integrated circuit device, b) Referring to a failure knowledge database that stores knowledge about failures, create failure candidate groups that may occur in the suspected failure area, and (c) assume failure candidates selected from the failure candidate groups. Inserted in the equivalent circuit of the suspected failure area as a failure, (d) in the semiconductor integrated circuit device, based on the actual observation data obtained by the signal measuring means a signal at a predetermined measurement point in the suspected failure area, the Simulate the circuit operation of the equivalent circuit when it is assumed that there is a contingency by a predetermined circuit simulator, (e) the simulation result, and the actual observation data Collating, when the simulation result and the actual observation data match, the contingency is output as a failure in the suspected failure area, (f) if the simulation result and the actual observation data do not match, A failure diagnosis method for a semiconductor integrated circuit device, comprising: selecting another failure candidate from the failure candidate group and performing the steps (c) to (e) again as a contingency failure, including the steps described above. provide.

In the semiconductor integrated circuit device failure diagnosing method of the present invention, preferably, the signal measuring means includes an electron beam probing device for measuring a wiring potential of the semiconductor integrated circuit device by an electron beam. To do.

[0010]

The integrated circuit failure diagnosis apparatus according to the present invention includes layout data of a suspected failure area determined to be defective by a test apparatus (electron beam tester, LSI tester, etc.) on the integrated circuit, and a circuit of the integrated circuit. Process information that determines the electrical properties of the circuit, such as the device value of each device and wiring, the parasitic effect, and the circuit information at the transistor level in the suspected failure region under normal conditions (consisting of transistors, resistors, capacitors, etc.). Information as an electric circuit to be generated) is extracted by the circuit extracting unit.

Further, layout information of the suspected failure area,
Failures that may occur in this suspected failure area from process information and a failure knowledge database that stores knowledge about failures such as what failures have occurred in the past and under what conditions they are likely to occur The failure list (fault list) is created by listing the failure locations and the failure causes.

Then, a fault is selected from the fault list and a transistor-level circuit is assumed when the fault is assumed to exist.

On the other hand, in the actual failure device, a signal or the like of a predetermined node (for example, a wiring section) in the suspected failure area is acquired by a signal acquisition device (signal measuring device).

Based on the acquired data (actual observation data), the circuit operation of a transistor-level equivalent circuit assuming a failure is simulated by an analog circuit simulator (for example, "SPICE" as a classic circuit simulator).

This simulation result is collated with the actual observation data of the circuit operation in the suspected failure area in the actual failure device.

As a result, if the simulation result and the actual observation data match each other, it is estimated that the assumed failure has occurred in the actual failure device, and if different, another failure is selected from the failure list. Assuming a new failure, repeat the simulation and comparison processing.

According to the present invention, since the assumed failure includes information on the failure location and the failure cause, it is possible to estimate the failure location and its form (hence the failure cause) in the suspected failure area.

Further, a plurality of circuit simulators are provided, and an equivalent circuit is roughly simulated to compare with actual observation data at a measurement point in the suspected failure region. If they match, the circuit simulator with higher accuracy is used to make a mismatch. In this case, by configuring another failure candidate from the failure list, the waste (loss) of performing a long-time circuit simulation for an inappropriate (unrealistic) failure is avoided, and the failure diagnosis Achieved high speed and efficiency.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a failure diagnosis device according to an embodiment of the present invention.

Referring to FIG. 1, layout information unit 1 includes layout data of a suspected failure area in failure device 9. Further, the process information unit 2 includes device structural data (element parameters, wiring information, parasitic effects, etc.) that determines the electrical properties of the failed device 9.

The failure knowledge database unit 3 stores knowledge information (including empirical rules) regarding failures, such as what kind of failure occurs in the failure of the integrated circuit and what kind of failure is likely to occur. It is a knowledge database.

The circuit extraction unit 4 inputs data from the layout information unit 1 and the process information unit 2, and extracts from transistors, resistors, capacitors, etc., which describe the normal electrical operation of the suspected failure region in the failure device 9. A so-called transistor-level equivalent circuit that is configured is created, and equivalent circuit information 5 including connection information (netlist) and element value information (including device parameters for circuit simulation) is output.

The failure list creating unit 6 refers to the data of the layout information unit 1, the process information unit 2 and the failure knowledge database unit 3 to identify the failure predicted in the suspected failure area as the physical position of the failure on the layout. , And the physical cause of the failure, the position of the failure in the equivalent circuit of the suspected failure area, and the failure form, and a failure list 7 is created.

The signal measuring unit 10, based on the normal equivalent circuit information 5 of the suspected failure area in the failed device 9, outputs an input signal and an output signal for the equivalent circuit.
The signal at a predetermined node in the equivalent circuit is acquired by actually operating the faulty device 9 to obtain the circuit operation information 11.

Here, one failure is selected from the failure list 7 and is set as a contingency failure (referred to as "processing step A").

From this contingency, the equivalent circuit information 5, and the input signal to the equivalent circuit of the circuit operation information 11, the behavior of the failure device 9 when the contingency is assumed to exist (be
Haviour) is obtained by the circuit simulator 8 to obtain simulation data 12 (referred to as "processing step B").

The comparison unit 13 inputs the circuit operation information 11 and the simulation data 12 and compares them, and outputs a contingency if they match and outputs no information if they do not match. It is good (it is called "processing step C").

Then, the processing steps A, B and C are repeated for all the elements of the failure list 7 or a part of them (when a failure is detected, when the processing is stopped, etc.).

The operation of this embodiment will be described in detail below with reference to FIG.

The circuit extraction unit 4 includes, for example, a layout information unit 1 and a process information unit 2,
(a) Arrangement information of each wiring in the suspected failure area, (b) wiring connection information by through holes, (c) wiring length and wiring width, (d) transistor size, (e) transistor and wiring Connection status, (f) positional relationship between wirings, (g) three-dimensional layout information of each element, (h) wiring resistance value, (i) transistor parameters, (j) wiring capacitance, (k) ) Calculate the element value etc. of each element and express the normal electric circuit formed in the suspected failure area with an equivalent circuit consisting of each element such as transistor, resistance, capacitance, etc. to create equivalent circuit information 5. To do.

Further, a correspondence table is created for each wiring and each element formed in the suspected failure area and each wiring (node) and each element in the normal circuit of the suspected failure area. Then, they are also output to the equivalent circuit information 5.

The failure list creation unit 6 lists the failures expected to occur in the suspected failure area from the layout information unit 1, the process information unit 2 and the failure knowledge database unit 3. This is based on the failure knowledge in the failure knowledge database unit 3, for example, the knowledge that a short-circuit failure is likely to occur between adjacent wirings, and a list of places where a short-circuit failure may occur from a predetermined threshold value. .

Further, generally, based on the knowledge that disconnection is likely to occur in the through hole portion, the through hole portion is extracted from the layout data of the suspected failure area, and what kind of failure is caused by the occurrence of the disconnection is set as a failure candidate. List up.

The failure knowledge database unit 3 stores failure knowledge obtained from knowledge information about failures such as failures in wiring systems, transistor systems, and both of them in a database.

On the basis of the fault knowledge stored in the fault knowledge database unit 3, the fault list produced by the fault list creating unit 6 is composed of the faults that are expected to occur, and each element of the fault list is It includes information on the failure position on the layout, the cause of the failure, the failure position on the equivalent circuit, and the failure mode.

The signal of each part in the suspected failure area in the failure device 9 is observed by the signal measuring unit 10.
At this time, the signal to be observed is instructed in advance as described later. The measured signals of the respective parts of the circuit are recorded and stored as circuit operation information 11 in a predetermined storage area.

One assumed fault (conjecture fault) is selected from the elements of the fault list 7 (processing step A), circuit information when a conjecture fault occurs in the suspected fault area is created from the equivalent circuit information 5, and this circuit is created. Then, the circuit simulator 8 simulates the circuit operation when the input signal to the suspected failure area obtained from the circuit operation information 11 is given, and is output as simulation data 12 (processing step B).

The comparison unit 13 compares the circuit operation information 11, which is the actual observation data of the faulty device 9, with the simulation data 12, and if the two coincide with each other, the contingency actually occurs in the faulty device 9. And output a contingency. On the contrary, if they do not match, it is determined that the contingency has not occurred in the failed device 9 (processing step C).

As mentioned above, process steps A, B, and C
Is performed for all or some of the elements of the fault list 7.

FIG. 2 is a block diagram for explaining an example of the configuration of the failure list creating unit 6 according to the embodiment of the present invention.

Referring to FIG. 2, the physical failure creation unit 20
Determines where (position) and what (form) failure is likely to occur in the suspected failure area of the failure device 9 based on knowledge information from the failure knowledge database unit 3 (see FIG. 1), A physical failure list 21 is created by using the failure location and failure cause as elements of the physical failure list.

Next, in the failure translation unit 22, where (position) and which position the physical failure output by the physical failure creation unit 20 is in the normal equivalent circuit (for example, in the netlist) for the suspected failure area. This is expressed (fault model) as a fault element, and a combination of the fault position, fault form, and physical fault information is output as a fault element to the fault list 7.

FIG. 3 is a block diagram for explaining an example of the configuration of the signal measuring unit 10 according to the embodiment of the present invention.

Referring to FIG. 3, from equivalent circuit information 5 and layout information unit 1, failing device 9 (see FIG. 1)
The input section and the output section for the equivalent circuit of the suspected failure area of are selected by the measurement point instruction unit 30, the physical positions of the wiring of the input section and the output section for the suspected failure area of the failure device 9 are determined, and the measurement point list 31 Output to.

From the information in the measurement point list 31, the signal measuring device 32 observes each actual signal in the faulty device 9.

FIG. 4 is a block diagram for explaining another form of the signal measuring unit 10 according to the embodiment of the present invention.

Referring to FIG. 4, the electron beam prober 40
Acquires position information of a wiring for measuring a signal from the measurement point list 31 and measures a signal potential of the instructed wiring.

FIG. 5 is a block diagram for explaining still another mode of the signal measuring unit 10 according to the embodiment of the present invention.

With reference to FIG. 5, the prober 50 obtains position information of the wiring for measuring a signal from the measurement point list 31, sets a probe for the designated wiring, and Measure the signal potential.

FIG. 6 is a block diagram for explaining another embodiment of the present invention. FIG. 6 shows an example of the configuration of the circuit simulator 8 in the embodiment shown in FIG. In FIG. 6, the layout information unit 1, the process information unit 2, the failure knowledge database unit 3, the circuit extraction unit 4, the failure list creation unit 6, the failure device 9, the signal measurement unit 10 and the like shown in FIG. 1 are omitted. Has been done.

Referring to FIG. 6, the circuit simulator 8 is
It has a first circuit simulator A60 and a second circuit simulator B61.

The first circuit simulator A60 is a simulator which operates at high speed but is not highly accurate. Using this simulator A60, equivalent circuit information 5 and failure list 7
The circuit including the contingencies is simulated and the result is output as simulation data A61 (referred to as "simulation A").

The simulation data A61 and the circuit operation information 11 are compared by the comparison unit 13 ("comparison A").
If the two match, then the second circuit simulator B62 with high simulation accuracy simulates the circuit operation of the equivalent circuit in the same manner as the simulation A (referred to as "simulation B"), and the comparison A Similarly, the circuit operation information 11 and the simulation data B63 are compared (referred to as "comparison B").

In the above comparisons A and B, the circuit operation information 11
And the simulation data do not match, the contingency is estimated to have not occurred in the failure device 9, and another failure is selected from the failure list 7 to be the contingency.

The above-mentioned simulation and comparison processing steps are executed a plurality of times to finally estimate the fault occurring in the faulty device 9.

As described above, the circuit operation of the equivalent circuit assuming a failure is simulated in advance by a circuit simulator having a rough simulation accuracy, and the simulation result and the actual observation data are compared. If another fault is selected from the above, and if they match, the estimation of the fault is made efficient by simulating the equivalent circuit with a circuit simulator with higher accuracy (unrealistic fault). The candidates are immediately rejected according to the results of the high-speed circuit simulator).

[0057]

As described above, the fault diagnosing device for an integrated circuit according to the present invention lists up the faults that may actually occur from the layout information, the process information and the fault knowledge, and lists them up. It is possible to point out where an actual failure has occurred in the integrated circuit by estimating the failure that has occurred in the failed device by performing circuit simulation assuming that failure and comparing it with actual observation data. It is possible and the cause of the failure can be estimated.

According to the present invention, the layout information,
By performing the failure diagnosis based on the process information and the failure knowledge, it is possible to avoid the assumption of an unrealistic failure and to shorten the failure diagnosis time.

Further, with the high integration of semiconductor devices, it is becoming difficult to estimate the failure by the conventional failure diagnosing method based on the physical observation. According to the present invention, the diagnosis can be performed by the simulation from the layout information and the process information. Therefore, there is an effect that it is possible to perform the failure diagnosis without being directly affected by the high integration of the integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a failure diagnostic device for an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a failure list creation unit according to an embodiment of the present invention.

FIG. 3 is a block diagram for explaining an example of a configuration of a signal measurement unit according to the embodiment of the present invention.

FIG. 4 is a block diagram for explaining another configuration example of the signal measurement unit according to the embodiment of the present invention.

FIG. 5 is a block diagram for explaining still another configuration example of the signal measurement unit according to the embodiment of the present invention.

FIG. 6 is a block diagram for explaining another configuration example of the circuit simulator according to the embodiment of the present invention.

[Explanation of symbols]

 1 Layout Information Unit 2 Process Information Unit 3 Fault Knowledge Database Unit 4 Circuit Extraction Unit 5 Equivalent Circuit Information 6 Fault List Creation Unit 7 Fault List 8 Circuit Simulator 9 Fault Device 10 Signal Measuring Unit 11 Circuit Operation Information 12 Simulation Data 13 Comparison Unit 20 Physical failure creation unit 21 Physical failure list 22 Failure translation unit 30 Measuring point instruction unit 31 Measuring point list 32 Signal measuring instrument 40 Electron beam prober 50 Prober 60 Circuit simulator A 61 Simulation data A 62 Circuit simulator B 63 Simulation data B

Claims (13)

[Claims] 1. A layout information storage means for storing and holding normal layout information of a faulty integrated circuit, and a process information storage means for storing and holding process information for determining the normal electrical properties of the faulty integrated circuit. A failure knowledge database unit that stores knowledge information about a failure that occurs in an integrated circuit in a predetermined database form; the layout information from the layout information storage unit; and the process information from the process information storage unit, A circuit extracting means for extracting an equivalent circuit of the faulty integrated circuit under normal conditions, and associating the equivalent circuit with a predetermined element for normal operation of the faulty integrated circuit; the layout information; From the process information and the knowledge information about the failure in the failure knowledge database unit, the normal state of the failure integrated circuit is determined. Failure list creating means for creating a failure candidate group (also referred to as "fault list") by searching for a failure that may occur in the circuit, and measuring an electric signal at a predetermined measurement point of the failure integrated circuit. Signal measuring means for creating circuit operation information, selecting a failure from the failure candidate group as a contingency failure, reflecting the contingency failure in the equivalent circuit, and based on the circuit operation information, the conjecture A simulation means for simulating a circuit operation when a fault exists in the equivalent circuit; and a comparison means for comparing the simulation result by the simulation means with the circuit operation information. Fault diagnosis device. 2. As a result of the comparison by the comparison means, when the simulation result and the actual observation data included in the circuit operation information match each other, the contingency fault is output as an estimated fault, and in the case of non-coincidence , A new fault is newly selected from the fault candidate group as a contingency fault,
2. The integrated circuit according to claim 1, wherein the simulation means performs a simulation of a circuit operation based on the contingency and controls the simulation result to be compared with the actual observation data by the comparison means. Fault diagnosis device. 3. The fault diagnosing device for an integrated circuit according to claim 1, wherein the circuit extracting means generates a transistor-level equivalent circuit for the faulty integrated circuit. 4. The failure list creating means creates a physical failure list by determining an actual failure (physical failure) occurrence position and a form of the physical failure in the normal integrated circuit of the failed integrated circuit. 2. The fault diagnosis device for an integrated circuit according to claim 1, further comprising: a physical fault list creating means; and a fault translating means for converting the physical fault as a fault in the equivalent circuit. 5. The means for measuring the signal from the equivalent circuit and the layout information to determine the measurement point in the layout of the faulty integrated circuit (referred to as "measurement point instruction means"), and the measurement point instruction. 2. The fault diagnostic device for an integrated circuit according to claim 1, further comprising: a signal acquisition unit that observes and measures a signal at a predetermined measurement point of the faulty integrated circuit based on information from the unit. 6. The fault diagnosing device for an integrated circuit according to claim 5, wherein the signal acquiring means includes an electron beam probing device for measuring a wiring potential of the integrated circuit by an electron beam. 7. The integrated circuit according to claim 5, wherein the signal acquisition means includes a prober device for bringing a probe into contact with the integrated circuit and measuring a signal at a predetermined measurement point of the integrated circuit. Fault diagnosis device. 8. The fault diagnosing device for an integrated circuit according to claim 1, wherein the simulation means includes a circuit simulator for simulating a circuit operation of an analog circuit. 9. The failure diagnosing device for an integrated circuit according to claim 8, wherein the simulation means includes a plurality of circuit simulators having different simulation accuracy. 10. The simulation means first simulates the circuit operation of the equivalent circuit with a first circuit simulator having a rough simulation accuracy, and actually observes the simulation result and the circuit operation information by the first circuit simulator. When the data and the data match each other, the equivalent circuit is simulated by another circuit simulator having a higher simulation accuracy than the first circuit simulator, and the matching with the actual observation data is collated based on the simulation result. 10. The fault diagnosis device for an integrated circuit according to claim 9. 11. An equivalent circuit of the suspected failure region is extracted from (a) layout data of the suspected failure region on the semiconductor integrated circuit device and process information of the semiconductor integrated circuit device, and (b) relating to the failure. A fault candidate database that may occur in the suspected fault area is created by referring to a fault knowledge database that stores knowledge, and (c) the suspected fault candidate is a suspected fault selected from the fault candidate group. Inserted in the equivalent circuit of the failure area, (d) in the semiconductor integrated circuit device, based on the actual observation data obtained by the signal measuring means the signal at a predetermined measurement point in the suspected failure area, the contingency exists Simulate the circuit operation of the equivalent circuit when it is supposed to be performed by a predetermined circuit simulator, (e) collate the simulation result and the actual observation data, When the simulation result and the actual observation data match, the contingency is output as a failure in the suspected failure area, (f) if the simulation result and the actual observation data do not match, the failure candidate group A method of diagnosing a failure in a semiconductor integrated circuit device, comprising: selecting another failure candidate from among the above and performing the steps (c) to (e) again as a contingency failure. 12. The method of diagnosing a failure in a semiconductor integrated circuit device according to claim 11, wherein the signal measuring means includes an electron beam probing device for measuring a wiring potential of the semiconductor integrated circuit device by an electron beam. 13. Each element of the failure candidate group generated in the step (b) has a physical position of a failure on a layout of the suspected failure area and a physical cause of the failure, and the equivalence of the suspected failure area. 12. The method for diagnosing a failure in a semiconductor integrated circuit device according to claim 11, further comprising the position of the failure in the circuit and the failure form.