JPH0969064A - External memory system - Google Patents

Abstract

(57) [Abstract] [Purpose] The flash memory can be applied even when a CPU in which the program area and the data area are separated. [Structure] A flash memory 10 in which a program is written, a CPU 20 that writes and reads a program to and from the flash memory 10, and executes the program, and an address latch circuit 30 that holds an address signal output from the CPU 20. In the CPU 20, ports P00 to P07 and ports P10 to P17 which are program ports for program input / output connected to the flash memory 10 and the address latch circuit 30 and ports P00 to P07 and ports P10 to P17 are included. Switching means for switching the operation is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system using a one-chip CPU.

[0002]

2. Description of the Related Art Conventionally, a program executed under the control of a one-chip CPU is written in a ROM provided inside the CPU or a ROM attached outside the CPU. It was done by replacing the ROM. In recent years, as a memory in which programs are written,
The program can be changed while it is mounted on the board, and a flash memory that can be electrically erased all at once is used.

[0003]

However, in some CPUs, a non-Neumann type CPU which separates a program area and a data area in order to improve the execution speed and performs parallel processing of program processing and data processing. When a non-Neumann CPU is used, it is possible to read and execute a program from the external memory in the program area, but to write a new program to the external memory when changing the program. Therefore, there is a problem that the flash memory cannot be applied. The present invention has been made in view of the problems of the above-described conventional technique, and the flash memory can be applied even when a CPU in which a program area and a data area are separated is used. The purpose is to provide an external memory system that can.

[0004]

In order to achieve the above object, the present invention provides a flash memory capable of writing and erasing a program, a program area for performing a program process, and a program port for inputting and outputting the program. A program comprising a program area written in the flash memory through the program port, and the program written in the flash memory is read into the CPU through the program port. An external memory system that executes the program in response to a memory access signal from the outside, wherein the CPU performs an output operation for writing the program to the memory at the program port and reading the program from the memory. Characterized in that it has a switching means for switching between operation.

Further, the CPU has a memory access output means for outputting the memory access signal.

[0006]

In the present invention constructed as described above, C
After the program in the program area of the PU is written to the flash memory provided outside the CPU through the program port, the operation of the program port is switched by the switching means inside the CPU, and the program written in the flash memory is It is read into the CPU via the program port. After that, when the memory access signal is input to the CPU, the program is executed in the CPU. In this way, the program is written to and read from the flash memory by switching the operation of the program port.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an external memory system of the present invention. Note that unnecessary signal lines are omitted in the figure. In the present embodiment, as shown in FIG. 1, a flash memory 10 in which a program is written, a CPU 20 that writes and reads a program to and from the flash memory 10, and a program, and a CP.
An address latch circuit 30 that holds an address signal output from U20 is provided. In the CPU 20, a flash memory 10 and an address latch circuit 3 are provided.
Ports P00 to P07 and ports P10 to P17 which are program ports for program input / output connected to 0
, Ports P20 to P27 and ports P30 to P37 which are data ports, and a / PSEN signal for reading a program in the flash memory 10,
The port P40 connected to the / OE terminal of the flash memory 10 and the address latch circuit 30,
A port P41 that outputs an ALE signal for latching an address and a signal for writing a program in the flash memory 10 are output.
, A port P42 connected to the / WR terminal, a port / EA to which an external memory access signal is input, and a port P60 which is a memory access output means for inputting a memory access signal to the / EA port.

The external memory system configured as described above will be described below. FIG. 2 is a diagram for explaining the operation of the external memory system shown in FIG. First, the ports P00 to P07 and the port P10
At P17, the address to which the program is written in the flash memory 10 is output (FIG. 2).
). Next, when the output at the port P41 is temporarily set to the H level, the address latch circuit 30 outputs
The addresses output from 00 to P07 and the ports P10 to P17 are held and the addresses in the flash memory 10 are set (FIG. 2).

Next, the ports P00 to P07 and the port P
In 10 to P17, the contents of the program to be written in the flash memory 10 are output (FIG. 2). Then, when the output at the port P42 is set to the L level,
The contents of the program output at the ports P00 to P07 and the ports P10 to P17 are the flash memory 1
It is written to 0 (FIG. 2). Next, ports P00-P
The operation of 07 and the ports P10 to P17 is switched to input by the software switching means in the CPU 20 (FIG. 2). Then, when the output at the port P40 is set to the L level (FIG. 2), the data from the flash memory 10 is transferred to the ports P00 to P07 and the ports P10 to P.
It is read at 17 (FIG. 2). The operation here is confirmation of data written in the flash memory 10 and reading of the status of the flash memory 10.

By repeating the above-described operation, it is possible to write a program in the flash memory 10 and read a program from the flash memory 10 in an operation equivalent to the timing of the bus. After writing the program to the flash memory 10, port P6
When the output at 0 is set to L level, the external memory access signal / EA becomes L level, so that the CPU 20 starts fetching an instruction from the flash memory 10 (FIG. 2). By the series of operations described above, the program in the CPU 20 is written in the flash memory 10 and executed in the CPU 20. The program written in the flash memory 10 is read into the CPU 20 via an I / O of the CPU 20, for example, a serial port.

[0011]

Since the present invention is constructed as described above, it has the following effects. According to the first aspect of the present invention, since the program in the program area is configured to be written to and read from the flash memory by switching the operation of the program port by the switching means in the CPU, The flash memory can be applied even when using a CPU that is separated from the data area. According to another aspect of the present invention, the CPU is provided with a memory access output means for outputting a memory access signal in the CPU.
It is not necessary to provide external means for outputting the memory access signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an external memory system of the present invention.

FIG. 2 is a diagram for explaining the operation of the external memory system shown in FIG.

[Explanation of symbols]

10 flash memory 20 CPU 30 address latch circuit P00 to P07, P10 to P17, P20 to P27, P
30 to P37, P40 to P42, P60 ports

Claims (2)

[Claims] 1. A flash memory capable of writing and erasing a program, a CPU having a program area for performing a program process and a program port for inputting and outputting the program, and storing the program in the program area. An external memory system that writes in the flash memory through the program port, reads the program written in the flash memory into the CPU through the program port, and executes the program by a memory access signal from the outside. Wherein the CPU switches between an output operation for writing the program into the flash memory at the program port and an operation for reading the program from the flash memory External memory system characterized by having steps. 2. The external memory system according to claim 1, wherein the CPU has a memory access output unit that outputs the memory access signal.