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JPH0964101A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Semiconductor integrated circuit device and manufacturing method thereof

Info

Publication number
JPH0964101A
JPH0964101A JP7217115A JP21711595A JPH0964101A JP H0964101 A JPH0964101 A JP H0964101A JP 7217115 A JP7217115 A JP 7217115A JP 21711595 A JP21711595 A JP 21711595A JP H0964101 A JPH0964101 A JP H0964101A
Authority
JP
Japan
Prior art keywords
melting point
semiconductor chip
bump
main surface
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7217115A
Other languages
Japanese (ja)
Inventor
Hiroyuki Takahashi
裕之 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7217115A priority Critical patent/JPH0964101A/en
Publication of JPH0964101A publication Critical patent/JPH0964101A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/13001—Core members of the bump connector
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Abstract

(57)【要約】 【目的】 バンプ電極に加わる機械的応力を緩和して、
接続部の信頼性を向上することが可能な技術を提供す
る。 【構成】 半導体チップ２は一主面の外周部に配置され
た融点の高いＡｕバンプ電極１４および中央部およびこ
の付近に配置された融点の低い半田バンプ電極１６から
なる、融点の異なる２種類のバンプ電極を介して、パッ
ケージ基板１にフェースダウンボンディングされてい
る。特に半導体チップ２の一主面の外周部に融点の高い
Ａｕバンプ電極１４を配置したことにより、Ａｕは柔軟
性に優れているので、機械的応力が加わったとき、Ａｕ
バンプ電極１４はこれを緩和するように作用する。 (57) [Summary] [Purpose] Relaxing the mechanical stress applied to the bump electrode,
Provided is a technique capable of improving the reliability of a connecting portion. The semiconductor chip 2 includes two kinds of different melting points, which are Au bump electrodes 14 having a high melting point arranged on the outer peripheral portion of one main surface and solder bump electrodes 16 having a low melting point arranged at and around the central portion. It is face-down bonded to the package substrate 1 via the bump electrodes. In particular, since the Au bump electrode 14 having a high melting point is arranged on the outer peripheral portion of the one main surface of the semiconductor chip 2, Au is excellent in flexibility.
The bump electrode 14 acts to relieve this.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置お
よびその製造方法に関し、特に、半導体チップを複数の
バンプ電極を介して配線基板にフェースダウンボンディ
ングする半導体集積回路装置に適用して有効な技術に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and is particularly effective when applied to a semiconductor integrated circuit device in which a semiconductor chip is face-down bonded to a wiring board via a plurality of bump electrodes. It is about technology.

【０００２】[0002]

【従来の技術】最近のＬＳＩ（半導体集積回路装置）は
より高度の機能が要求されるようになってきており、こ
れに伴ってその集積度はますます高まる傾向にある。こ
のような高集積度のＬＳＩに適したパッケージの一方式
として、フリップチップ方式が採用されている。2. Description of the Related Art Recent LSIs (semiconductor integrated circuit devices) are required to have higher functions, and the degree of integration tends to increase accordingly. A flip-chip method is adopted as one method of a package suitable for such a highly integrated LSI.

【０００３】このフリップチップ方式は、一主面に全面
的に形成した複数の電極パッドに各々バンプ電極を形成
した半導体チップを用いて、この半導体チップをその複
数のバンプ電極を介して配線基板にフェースダウンボン
ディングする技術である。バンプ電極としては、低融点
での接続性に優れた半田（Ｐｂ−Ｓｎ系合金）が用いら
れる。This flip-chip method uses a semiconductor chip in which bump electrodes are formed on a plurality of electrode pads entirely formed on one main surface, and the semiconductor chip is mounted on a wiring board via the bump electrodes. This is a face-down bonding technology. As the bump electrode, solder (Pb-Sn alloy) having a low melting point and excellent connectivity is used.

【０００４】このフリップチップ方式によれば、配線基
板上の配線を半導体チップのバンプ電極を接続する領域
まで引き延ばして、半導体チップをフェースダウンボン
ディングするので、ワイヤボンディング方式に比較して
信号経路を短縮できるため、高速な信号伝送が可能とな
る。また、このフリップチップ方式によれば、半導体チ
ップの一主面の外周部のみならず中央部およびこの付近
にも電極パッドを配置できるので、比較的小さい面積で
高集積度の半導体チップを実現できるようになり、さら
に電極パッドのピッチに余裕を持たせることができるよ
うになる。According to this flip chip method, the wiring on the wiring substrate is extended to the region where the bump electrode of the semiconductor chip is connected and the semiconductor chip is face down bonded. Therefore, the signal path is shortened as compared with the wire bonding method. Therefore, high-speed signal transmission becomes possible. Further, according to this flip chip method, the electrode pads can be arranged not only on the outer peripheral portion of the one main surface of the semiconductor chip but also on the central portion and in the vicinity thereof, so that a highly integrated semiconductor chip can be realized in a relatively small area. As a result, the pitch of the electrode pads can be increased.

【０００５】このようなフリップチップ方式を採用した
ＬＳＩパッケージは、例えば、特開昭６２−２４９４２
９号公報、あるいは特開昭６３−３１０１３９号公報に
開示されている。An LSI package adopting such a flip chip system is disclosed in, for example, Japanese Patent Laid-Open No. 62-24942.
No. 9 or Japanese Patent Laid-Open No. 63-310139.

【０００６】[0006]

【発明が解決しようとする課題】前記のようなフリップ
チップ方式を採用したＬＳＩパッケージでは、半田で構
成されたバンプ電極を介して半導体チップを配線基板に
フェースダウンボンディングするが、そのバンプ電極と
して用いる半田は機械的応力に対して弱いので、接続部
の信頼性が低下するという問題がある。In the flip-chip type LSI package as described above, the semiconductor chip is face-down bonded to the wiring substrate via the bump electrode formed of solder, and is used as the bump electrode. Since solder is vulnerable to mechanical stress, there is a problem that the reliability of the connection portion is reduced.

【０００７】すなわち、各種電子機器にＬＳＩを組み込
んだ場合、機器の使用環境によって外気温度やＬＳＩの
発熱により、熱膨張が発生し、この結果バンプ電極に対
して機械的応力が加わるようになるので、バンプ電極が
剥離したり、変形して接続不良が起こる。このため、Ｌ
ＳＩの長寿命化を図るのが困難になって、比較的短期間
での不良発生率が高くなるので、顧客の信用を損ねる原
因となる。That is, when an LSI is incorporated in various electronic devices, thermal expansion occurs due to the outside air temperature or heat generation of the LSI depending on the environment in which the device is used, and as a result, mechanical stress is applied to the bump electrodes. The bump electrode may be peeled off or deformed to cause a connection failure. Therefore, L
It becomes difficult to extend the service life of the SI, and the defect occurrence rate becomes relatively high in a relatively short period of time, which causes a loss of customer credibility.

【０００８】本発明の目的は、バンプ電極に加わる機械
的応力を緩和して、接続部の信頼性を向上することが可
能な技術を提供することにある。An object of the present invention is to provide a technique capable of relaxing the mechanical stress applied to the bump electrode and improving the reliability of the connection portion.

【０００９】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【００１０】[0010]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

【００１１】（１）本発明の半導体集積回路装置は、半
導体チップをこの一主面に形成した複数のバンプ電極を
介して配線基板にフェースダウンボンディングする半導
体集積回路装置であって、前記複数のバンプ電極は、融
点の異なる２種類の金属で構成されて各々が半導体チッ
プの異なる位置に配置されている。(1) A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which a semiconductor chip is face-down bonded to a wiring board via a plurality of bump electrodes formed on the one main surface. The bump electrodes are made of two kinds of metals having different melting points and are arranged at different positions on the semiconductor chip.

【００１２】（２）本発明の半導体集積回路装置の製造
方法は、（ａ）一主面に全面的に形成した複数の電極パ
ッドのうち、中央部およびこの付近の電極パッドに融点
の低いバンプ電極を形成した半導体チップを用意する工
程と、（ｂ）前記半導体チップの一主面の外周部の複数
の電極パッドに融点の高いバンプ電極を形成する工程
と、（ｃ）一主面に形成した複数の配線および電極のう
ち、前記半導体チップの融点の低いバンプ電極の位置に
対応した位置の前記電極に融点の低いバンプ電極を形成
するとともに、前記半導体チップの融点の高いバンプ電
極の位置に対応した位置の前記配線に融点の高いバンプ
電極を形成した配線基板を用意する工程と、（ｄ）前記
半導体チップの一主面と前記配線基板の一主面とを対向
させ、対応する融点の低いバンプ電極同士および融点の
高いバンプ電極同士を接続して、半導体チップを配線基
板にフェースダウンボンディングする工程とを含んでい
る。(2) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, (a) among a plurality of electrode pads entirely formed on one main surface, a bump having a low melting point is formed in the central portion and in the vicinity thereof. A step of preparing a semiconductor chip having electrodes formed thereon; (b) a step of forming bump electrodes having a high melting point on a plurality of electrode pads on an outer peripheral portion of one main surface of the semiconductor chip; and (c) forming on one main surface. Forming a low melting point bump electrode on the electrode at a position corresponding to the position of the low melting point bump electrode of the semiconductor chip among the plurality of wirings and electrodes, and at the position of the high melting point bump electrode of the semiconductor chip. A step of preparing a wiring board in which bump electrodes having a high melting point are formed on the wiring at corresponding positions; and (d) one main surface of the semiconductor chip and one main surface of the wiring board are opposed to each other, and the corresponding melting point is set. Connect the low bump electrodes and between a high melting point bump electrodes together, and a step of face-down bonding the semiconductor chip on a wiring board.

【００１３】（３）本発明の半導体集積回路装置の製造
方法は、（ａ）一主面に全面的に形成した複数の電極パ
ッドのうち、中央部およびこの付近の電極パッドに融点
の低いバンプ電極を形成した半導体チップを用意する工
程と、（ｂ）前記半導体チップの一主面の外周部の複数
の電極パッドに融点の高いバンプ電極を形成する工程
と、（ｃ）一主面に形成した複数の配線および電極のう
ち、前記半導体チップの融点の高いバンプ電極の位置に
対応した位置の前記配線に融点の高いバンプ電極を形成
した配線基板を用意する工程と、（ｄ）前記半導体チッ
プの一主面と前記配線基板の一主面とを対向させ、対応
する融点の高いバンプ電極同士を接続すると同時に前記
融点の低いバンプ電極を前記電極に接続して、半導体チ
ップを配線基板にフェースダウンボンディングする工程
とを含んでいる。(3) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, (a) among a plurality of electrode pads entirely formed on one main surface, a bump having a low melting point is formed on the electrode pad in the central portion and in the vicinity thereof. A step of preparing a semiconductor chip having electrodes formed thereon; (b) a step of forming bump electrodes having a high melting point on a plurality of electrode pads on an outer peripheral portion of one main surface of the semiconductor chip; and (c) forming on one main surface. Preparing a wiring substrate having bump electrodes with a high melting point formed on the wirings at positions corresponding to the positions of the bump electrodes with a high melting point of the semiconductor chip among the plurality of wirings and electrodes, and (d) the semiconductor chip. One main surface of the wiring board and one main surface of the wiring board are opposed to each other, and corresponding bump electrodes having a high melting point are connected to each other, and at the same time, the bump electrode having a low melting point is connected to the electrode, and the semiconductor chip is mounted on the wiring board. And a step of over scan down bonding.

【００１４】[0014]

【作用】上述した（１）の手段によれば、本発明の半導
体集積回路装置は、半導体チップを配線基板にフェース
ダウンボンディングする複数のバンプ電極は、融点の異
なる２種類の金属で構成されて各々が半導体チップの異
なる位置に配置されているので、バンプ電極に加わる機
械的応力を緩和して、接続部の信頼性を向上することが
可能となる。According to the above-mentioned means (1), in the semiconductor integrated circuit device of the present invention, the plurality of bump electrodes for face-down bonding the semiconductor chip to the wiring substrate are made of two kinds of metals having different melting points. Since each of them is arranged at a different position of the semiconductor chip, it is possible to reduce the mechanical stress applied to the bump electrode and improve the reliability of the connection portion.

【００１５】上述した（２）の手段によれば、本発明の
半導体集積回路の製造方法は、一主面の中央部およびこ
の付近の電極パッドに融点の低いバンプ電極を形成した
半導体チップを用意して、この一主面の外周部の複数の
電極パッドに融点の高いバンプ電極を形成する。次に、
一主面の前記半導体チップの融点の低いバンプ電極の位
置に対応した位置の電極に融点の低いバンプ電極を形成
するとともに、融点の高いバンプ電極の位置に対応した
位置の配線に融点の高いバンプ電極を形成した配線基板
を用意して、対応する融点の低いバンプ電極同士および
融点の高いバンプ電極同士を接続して、半導体チップを
配線基板にフェースダウンボンディングする。これによ
って、バンプ電極に加わる機械的応力を緩和して、接続
部の信頼性を向上することが可能となる。According to the above-mentioned means (2), the semiconductor integrated circuit manufacturing method of the present invention provides a semiconductor chip in which bump electrodes having a low melting point are formed on the electrode pads at and around the central portion of one main surface. Then, bump electrodes having a high melting point are formed on the plurality of electrode pads on the outer peripheral portion of the one main surface. next,
A bump electrode having a low melting point is formed on an electrode at a position corresponding to a bump electrode having a low melting point on the one main surface, and a bump having a high melting point is formed on a wiring at a position corresponding to a bump electrode having a high melting point. A wiring board having electrodes formed thereon is prepared, corresponding bump electrodes having a low melting point and bump electrodes having a high melting point are connected to each other, and a semiconductor chip is face-down bonded to the wiring board. This makes it possible to reduce the mechanical stress applied to the bump electrode and improve the reliability of the connection portion.

【００１６】上述した（３）の手段によれば、本発明の
半導体集積回路の製造方法は、一主面の中央部およびこ
の付近の電極パッドに融点の低いバンプ電極を形成した
半導体チップを用意して、この一主面の外周部の複数の
電極パッドに融点の高いバンプ電極を形成する。次に、
一主面の前記半導体チップの融点の高いバンプ電極位置
に対応した位置の配線に融点の高いバンプ電極および他
の位置に電極を形成した配線基板を用意して、対応する
融点の高いバンプ電極同士を接続すると同時に融点の低
いバンプ電極を電極に接続して、半導体チップを配線基
板にフェースダウンボンディングする。これによって、
バンプ電極に加わる機械的応力を緩和して、接続部の信
頼性を向上することが可能となる。According to the above-mentioned means (3), the semiconductor integrated circuit manufacturing method of the present invention provides a semiconductor chip in which bump electrodes having a low melting point are formed on the electrode pad in the central portion of one main surface and in the vicinity thereof. Then, bump electrodes having a high melting point are formed on the plurality of electrode pads on the outer peripheral portion of the one main surface. next,
A wiring board having a bump electrode having a high melting point and an electrode formed at another position is formed on the wiring at a position corresponding to the bump electrode position having a high melting point of the semiconductor chip on one main surface, and the corresponding bump electrodes having a high melting point are provided. At the same time, the bump electrode having a low melting point is connected to the electrode, and the semiconductor chip is face-down bonded to the wiring board. by this,
It is possible to reduce the mechanical stress applied to the bump electrode and improve the reliability of the connection portion.

【００１７】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments.

【００１８】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

【００１９】[0019]

【実施例】【Example】

（実施例１）図１は本発明の実施例１による半導体集積
回路装置を示す断面図で、フリップチップ方式を採用し
たＬＳＩパッケージを示している。本実施例の半導体集
積回路装置は、例えばアルミナ、窒化アルミニウムなど
のセラミックで構成され配線基板として働くパッケージ
基板１の一主面上に、後述するような構造のバンプ電極
を介して半導体チップ２をフェースダウンボンディング
して、この半導体チップ２をキャップ３で気密封止した
パッケージ構造を有している。半導体チップ２は例えば
Ｓｉからなり、一例として１６メガビットの記憶容量を
有するメモリチップを用いている。(Embodiment 1) FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention, showing an LSI package adopting a flip chip method. In the semiconductor integrated circuit device of this embodiment, the semiconductor chip 2 is mounted on one main surface of the package substrate 1 which is made of ceramic such as alumina or aluminum nitride and serves as a wiring substrate, via bump electrodes having a structure described later. It has a package structure in which the semiconductor chip 2 is hermetically sealed with a cap 3 by face-down bonding. The semiconductor chip 2 is made of, for example, Si, and uses a memory chip having a storage capacity of 16 megabits as an example.

【００２０】パッケージ基板１の一主面には外周部に複
数の配線４が形成されるとともに、中央部およびこの付
近に複数の電極５が形成され、またその内部にはＧＮＤ
（接地）配線６および電源配線７が形成されている。Ｇ
ＮＤ配線６および電源配線７と電極５は、スルーホール
８を通じて接続されている。これら配線４、電極５、Ｇ
ＮＤ配線６および電源配線７は、パッケージ基板１を構
成するセラミックの製造時に予めスクリーン印刷法によ
って未焼結セラミックシートにＷのような高融点金属を
印刷しておいて、セラミック焼結処理と同時に熱処理さ
れて形成される。配線４および電極５の表面にはコンタ
クト性に優れた金属としてＡｕめっきが施されている。A plurality of wirings 4 are formed on the outer peripheral portion of one main surface of the package substrate 1, and a plurality of electrodes 5 are formed on the central portion and in the vicinity thereof.
(Ground) wiring 6 and power supply wiring 7 are formed. G
The ND wiring 6 and the power supply wiring 7 and the electrode 5 are connected through a through hole 8. These wiring 4, electrode 5, G
The ND wiring 6 and the power supply wiring 7 are printed with a refractory metal such as W on a non-sintered ceramic sheet by a screen printing method in advance at the time of manufacturing the ceramic constituting the package substrate 1, and simultaneously with the ceramic sintering process. It is formed by heat treatment. Au plating is applied to the surfaces of the wiring 4 and the electrode 5 as a metal having excellent contact properties.

【００２１】パッケージ基板１の一主面の外周部には、
例えば４２アロイで知られているＦｅ−Ｎｉ合金、ある
いはコバール（Ｆｅ−Ｎｉ−Ｃｏ合金）などで構成され
た複数のリード９がろう材１０を介して接続されてお
り、各リード９は配線４およびＧＮＤ配線６に接続され
ている。また、パッケージ基板１の裏面には全面的に、
例えばＷのような高融点金属で構成されたＧＮＤメタラ
イズ層１１が形成されていて、このＧＮＤメタライズ層
１１の表面にはコンタクト性に優れた金属としてＡｕめ
っきが施されている。ＧＮＤメタライズ層１１はスルー
ホール８を通じてＧＮＤ配線６に接続されている。On the outer periphery of one main surface of the package substrate 1,
For example, a plurality of leads 9 made of Fe-Ni alloy or Kovar (Fe-Ni-Co alloy) known as 42 alloy are connected via a brazing material 10, and each lead 9 is connected to a wiring 4 And the GND wiring 6. In addition, the entire back surface of the package substrate 1
For example, the GND metallization layer 11 made of a refractory metal such as W is formed, and the surface of the GND metallization layer 11 is plated with Au as a metal having excellent contact properties. The GND metallization layer 11 is connected to the GND wiring 6 through the through hole 8.

【００２２】パッケージ基板１の裏面のＧＮＤメタライ
ズ層１１には、このＧＮＤメタライズ層１１と略同一の
外形寸法を有する例えばＷ−Ｃｕ（１０％）で構成され
た金属ベース１２がろう材１３を介して接続されてい
る。この金属ベース１２は、ＧＮＤ電位の安定化、パッ
ケージの補強およびヒートシンクの役割を兼ねている。On the GND metallization layer 11 on the back surface of the package substrate 1, a metal base 12 made of, for example, W-Cu (10%) and having substantially the same outer dimensions as the GND metallization layer 11 is provided with a brazing material 13 interposed therebetween. Connected. The metal base 12 also functions as stabilizing the GND potential, reinforcing the package, and serving as a heat sink.

【００２３】パッケージ基板１の一主面の外周部に形成
されている複数の配線４のうち、所望部例えば図９に示
すように４隅部に配置されている配線４Ａに対しては、
図２に拡大構造を示すように、予め融点の高いバンプ電
極としての大径のＡｕバンプ電極１４Ａが、例えば２段
に重ねられて形成されている。この大径のＡｕバンプ電
極１４Ａは、後述するような方法で形成され、その表裏
面は平坦化されている。なお、この大径のＡｕバンプ電
極１４Ａは２段に限らず、１段でも良く、あるいは３段
以上であっても良い。Of the plurality of wirings 4 formed on the outer peripheral portion of one main surface of the package substrate 1, for a desired portion, for example, the wiring 4A arranged at the four corners as shown in FIG.
As shown in the enlarged structure in FIG. 2, a large-diameter Au bump electrode 14A serving as a bump electrode having a high melting point is formed in advance in two layers, for example. The large diameter Au bump electrode 14A is formed by a method described later, and the front and back surfaces thereof are flattened. The Au bump electrode 14A having a large diameter is not limited to two steps and may be one step or three or more steps.

【００２４】パッケージ基板１の一主面と対向してい
る、半導体チップ２の一主面には全面的に例えばＡｕ薄
膜からなる複数の電極パッド１５が形成され、これら電
極パッド１５のうち半導体チップ２の一主面の外周部に
配置されたものの所望部に対しては、すなわちパッケー
ジ基板１の図９に示した配線４Ａに対応した位置に配置
されている、図４に示したように外周部の４隅部に配置
されている電極パッド１５Ａに対しては、図２に拡大構
造を示すように、融点の高いバンプ電極としての小径の
Ａｕバンプ電極１４Ｂが、例えば２段に重ねられて接続
されている。A plurality of electrode pads 15 made of, for example, an Au thin film are formed on the entire one main surface of the semiconductor chip 2 facing the one main surface of the package substrate 1. Of these electrode pads 15, the semiconductor chip is formed. 2 is arranged on the outer peripheral portion of one main surface of the main surface 2, but is arranged at a position corresponding to the wiring 4A shown in FIG. 9 of the package substrate 1, as shown in FIG. As shown in an enlarged structure in FIG. 2, small-diameter Au bump electrodes 14B serving as bump electrodes having a high melting point are overlapped on the electrode pads 15A arranged at the four corners of the portion, for example, in two stages. It is connected.

【００２５】そして、対応する融点の高い各Ａｕバンプ
電極１４Ａ、１４Ｂ同士は、後述するような熱圧着法に
よって一体に接続されてＡｕバンプ電極１４を構成して
いる。ここで、各Ａｕバンプ電極１４Ａ、１４Ｂ自身は
溶融することなく一体に接続されている。このようにバ
ンプ電極の一種としてＡｕバンプ電極１４を構成するこ
とにより、Ａｕは柔軟性に優れているので、機械的応力
が加わったときＡｕバンプ電極１４は、これを緩和する
ように作用する。しかも、Ａｕは化学的に安定している
ので、腐食しないため、経時的に安定している。The corresponding Au bump electrodes 14A and 14B having a high melting point are integrally connected to each other by a thermocompression bonding method, which will be described later, to form the Au bump electrode 14. Here, the Au bump electrodes 14A and 14B themselves are integrally connected without melting. By forming the Au bump electrode 14 as a kind of bump electrode in this way, since Au has excellent flexibility, the Au bump electrode 14 acts to relieve mechanical stress when it is applied. Moreover, since Au is chemically stable and does not corrode, it is stable over time.

【００２６】小径のＡｕバンプ電極１４Ｂは、大径のＡ
ｕバンプ電極１４Ａと同様に、後述するような方法で形
成され、その表裏面は平坦化されている。なお、この小
径のＡｕバンプ電極１４Ｂも２段に限らず、１段でも良
く、あるいは３段以上であっても良い。また、大径およ
び小径のＡｕバンプ電極１４Ａ、１４Ｂを形成する対象
は、逆にするようにしても良い。The small-diameter Au bump electrode 14B has a large-diameter A bump electrode 14B.
Similar to the u bump electrode 14A, it is formed by a method described later, and its front and back surfaces are flattened. Note that the Au bump electrodes 14B having a small diameter are not limited to two steps, and may be one step or three or more steps. The targets for forming the large-diameter and small-diameter Au bump electrodes 14A and 14B may be reversed.

【００２７】一方、パッケージ基板１の一主面の電極５
および前記配線４Ａ以外の配線４と、半導体チップ２の
電極パッド１５のうち半導体チップ２の前記外周部の４
隅部の電極パッド１５Ａ以外の中央部およびこの付近に
配置されたものとの間には、すなわちパッケージ基板１
の図９に示した配線４Ａ以外の配線４および電極５に対
応した位置に配置されている電極パッド１５との間に
は、図２に拡大構造を示すように、融点の低いバンプ電
極としての半田（Ｐｂ−Ｓｎ系合金）バンプ電極１６が
接続されている。なお、この半田バンプ電極１６は、後
述するように予めパッケージ基板１側に形成された半田
バンプ電極１６Ａと、予め半導体チップ２の電極パッド
１５側に形成された半田バンプ電極１６Ｂとが、熱圧着
法によって溶融されて半田バンプ電極１６が形成されて
いる。On the other hand, the electrode 5 on one main surface of the package substrate 1
And the wiring 4 other than the wiring 4A and the electrode pads 15 of the semiconductor chip 2 on the outer peripheral portion 4 of the semiconductor chip 2.
Between the central portion other than the electrode pads 15A at the corners and those arranged in the vicinity thereof, that is, the package substrate 1
Between the wiring 4 other than the wiring 4A shown in FIG. 9 and the electrode pad 15 arranged at a position corresponding to the electrode 5, as shown in an enlarged structure in FIG. Solder (Pb-Sn alloy) bump electrodes 16 are connected. The solder bump electrode 16 includes a solder bump electrode 16A formed in advance on the package substrate 1 side and a solder bump electrode 16B formed in advance on the electrode pad 15 side of the semiconductor chip 2 in thermocompression bonding as described later. The solder bump electrode 16 is formed by being melted by the method.

【００２８】ここで、図２からも明らかなように、Ａｕ
バンプ電極１４と半田バンプ電極１６は、パッケージ基
板１の一主面に対して垂直となる方向に形成される。ま
た、パッケージ基板１の一主面と半導体チップ２の一主
面との間隔が一定となるように、２段の大径のＡｕバン
プ電極１４Ａと２段の小径のＡｕバンプ電極１４Ｂとを
重ねたＡｕバンプ電極１６の高さ寸法と、半田バンプ電
極１６との高さ寸法は等しくなるように設定される。Here, as is clear from FIG. 2, Au
The bump electrodes 14 and the solder bump electrodes 16 are formed in a direction perpendicular to one main surface of the package substrate 1. Further, the two-step large-diameter Au bump electrodes 14A and the two-step small-diameter Au bump electrodes 14B are overlapped so that the distance between the one main surface of the package substrate 1 and the one main surface of the semiconductor chip 2 becomes constant. The height dimension of the Au bump electrode 16 and the height dimension of the solder bump electrode 16 are set to be equal.

【００２９】パッケージ基板１の主面の外周部には、例
えばアルミナ、窒化アルミニウムなどのセラミックで構
成されたダム枠１８が配置され、このダム枠１８の表裏
面には例えばＷのような高融点金属で構成されたメタラ
イズ層１９が形成されて、ろう材１７を介して接続され
ている。また、ダム枠１８の上面には、例えばＦｅ−Ｎ
ｉ合金、あるいＦｅ−Ｎｉ−Ｃｏ合金などで構成された
表面にＡｕめっきが施されたキャップ３が、ろう材２０
を介して接続されて、半導体チップ２を気密封止してい
る。A dam frame 18 made of a ceramic such as alumina or aluminum nitride is arranged on the outer periphery of the main surface of the package substrate 1, and a high melting point such as W is formed on the front and back surfaces of the dam frame 18. A metallized layer 19 made of metal is formed and connected via a brazing material 17. Further, on the upper surface of the dam frame 18, for example, Fe-N
The cap 3 having a surface made of an i alloy, an Fe-Ni-Co alloy, or the like and having Au plated thereon is a brazing filler metal 20.
And the semiconductor chip 2 is hermetically sealed.

【００３０】次に、本実施例の半導体集積回路装置の一
つの製造方法を、図４乃至図１２を参照して工程順に説
明する。Next, one method of manufacturing the semiconductor integrated circuit device of this embodiment will be described in the order of steps with reference to FIGS.

【００３１】まず、図４に示すように、一主面に例えば
Ａｕ薄膜からなる複数の電極パッド１５を形成した半導
体チップ２を用意する。この電極パッド１５のうち外周
部の４隅部に配置されている電極パッド１５Ａに対して
は、後程に融点の高い小径のＡｕバンプ電極が形成され
る。First, as shown in FIG. 4, a semiconductor chip 2 having a plurality of electrode pads 15 made of, for example, an Au thin film on one main surface is prepared. For the electrode pads 15A arranged at the four corners of the outer peripheral portion of the electrode pad 15, small-sized Au bump electrodes having a high melting point are formed later.

【００３２】次に、図５に示すように、半導体チップ２
の一主面の外周部の４隅部に配置された電極パッド１５
Ａ以外の、中央部およびこの付近に配置された電極パッ
ド１５に融点の低い半田バンプ電極１６Ｂを形成する。
半導体チップ２の外周部の４隅部に配置された電極パッ
ド１５ＡはＡｕ薄膜が形成されたままになっている。Next, as shown in FIG. 5, the semiconductor chip 2
The electrode pads 15 arranged at the four corners of the outer periphery of the one main surface
A solder bump electrode 16B having a low melting point is formed on the electrode pads 15 other than A and arranged in the central portion and in the vicinity thereof.
The Au thin film remains formed on the electrode pads 15A arranged at the four corners of the outer peripheral portion of the semiconductor chip 2.

【００３３】続いて、図６に示すように、半導体チップ
２の一主面の外周部の４隅部に配置された電極パッド１
５Ａに、融点の高い小径のＡｕバンプ電極１４Ｂを２段
に重ねて形成する。このＡｕバンプ電極１４Ｂは以下の
ようなボールボンディング技術を利用して形成すること
ができる。Subsequently, as shown in FIG. 6, the electrode pads 1 arranged at the four corners of the outer periphery of the one main surface of the semiconductor chip 2.
5A, small-diameter Au bump electrodes 14B having a high melting point are formed in two layers. The Au bump electrode 14B can be formed by using the ball bonding technique described below.

【００３４】まず、図７（ａ）に示すように、ワイヤボ
ンダーに備えられているキャピラリー２１を半導体チッ
プ２上に配置して、キャピラリー２１から引き出したＡ
ｕ線２２の先端をトーチ２３で切断することにより、表
面張力によってＡｕボール２４を形成する。次に、図７
（ｂ）に示すように、キャピラリー２１を下降させてＡ
ｕボール２４を電極パッド１５Ａに熱圧着する。キャピ
ラリー２１は予め数１００℃に加熱されているので、熱
圧着はスムーズに行われる。First, as shown in FIG. 7A, the capillary 21 provided in the wire bonder is arranged on the semiconductor chip 2, and the capillary A drawn from the capillary 21 is placed.
By cutting the tip of the u-line 22 with the torch 23, the Au ball 24 is formed by the surface tension. Next, FIG.
As shown in (b), lower the capillary 21 to A
The u ball 24 is thermocompression bonded to the electrode pad 15A. Since the capillary 21 is preheated to several hundreds of degrees Celsius, the thermocompression bonding is performed smoothly.

【００３５】続いて、図７（ｃ）に示すように、キャピ
ラリー２１を上昇させた後、図７（ｄ）に示すように、
Ａｕ線２２のネック部をトーチ２３で切断する。これに
より、切断されたＡｕ線２２の先端には図７（ａ）と同
様にＡｕボール２４が形成されるとともに、電極パッド
１５Ａ上には小径のＡｕバンプ電極１４Ｂが１段形成さ
れる。図７（ｅ）はＡｕバンプ電極１４Ｂの外形寸法の
一例を示している（単位はμｍ）。なお、Ａｕバンプ電
極１４Ｂの表面には突出したアンカー部２５が形成され
る。Subsequently, as shown in FIG. 7 (c), after raising the capillary 21, as shown in FIG. 7 (d).
The neck portion of the Au wire 22 is cut with the torch 23. As a result, an Au ball 24 is formed at the tip of the cut Au wire 22 as in FIG. 7A, and a small-diameter Au bump electrode 14B is formed on the electrode pad 15A. FIG. 7E shows an example of the external dimensions of the Au bump electrode 14B (unit: μm). A protruding anchor portion 25 is formed on the surface of the Au bump electrode 14B.

【００３６】引き続いて、このようにして形成されたＡ
ｕバンプ電極１４Ｂに対して、図７（ａ）乃至図７
（ｄ）の操作を繰り返して別なＡｕバンプ電極１４Ｂを
形成することにより、２段のＡｕバンプ電極１４Ｂを重
ねることができる。この際、下の段のＡｕバンプ電極１
４Ｂのアンカー部２５を利用して、これに上の段のＡｕ
バンプ電極１４Ｂを食い込ませることにより、下の段の
Ａｕバンプ電極１４Ｂに対して上の段のＡｕバンプ電極
１４Ｂの機械的応力に対する接続部の信頼性向上効果が
得られる。Subsequently, A formed in this way
7A to 7 with respect to the u bump electrode 14B.
By repeating the operation of (d) to form another Au bump electrode 14B, it is possible to stack the Au bump electrodes 14B in two stages. At this time, the lower Au bump electrode 1
Using the anchor portion 25 of 4B, Au on the upper stage
By digging in the bump electrode 14B, an effect of improving the reliability of the connection portion against the mechanical stress of the Au bump electrode 14B in the upper stage with respect to the Au bump electrode 14B in the lower stage can be obtained.

【００３７】次に、図８に示すように、金属ベース１２
およびダム枠１８を接続したパッケージ基板１を用意す
る。続いて、図９に示すように、パッケージ基板１の半
導体チップ２の半田バンプ電極１６Ｂの位置に対応した
位置である配線４Ａ以外の配線４および電極５に、図１
０に示すように、半田バンプ電極１６Ａを形成するとと
もに、半導体チップ２の小径のＡｕバンプ電極１４Ｂの
位置に対応した位置である配線４Ｂに融点の高い大径の
Ａｕバンプ電極１４Ａを２段に重ねて形成する。このＡ
ｕバンプ電極１４Ａは、図７（ａ）乃至図７（ｄ）に示
したような、ボールボンディング技術を利用して形成す
ることができる。また、半田バンプ電極１６Ａの形成は
周知の半田ボール形成技術を利用して、容易に行うこと
ができる。Next, as shown in FIG.
Then, the package substrate 1 to which the dam frame 18 is connected is prepared. Then, as shown in FIG. 9, the wiring 4 and the electrodes 5 other than the wiring 4A, which are the positions corresponding to the positions of the solder bump electrodes 16B of the semiconductor chip 2 of the package substrate 1, are attached to the semiconductor chip 2 of FIG.
As shown in FIG. 0, the solder bump electrode 16A is formed, and the large-diameter Au bump electrode 14A having a high melting point is formed in two steps on the wiring 4B at a position corresponding to the position of the small-diameter Au bump electrode 14B of the semiconductor chip 2. Form by stacking. This A
The u bump electrode 14A can be formed by using the ball bonding technique as shown in FIGS. 7A to 7D. Further, the formation of the solder bump electrode 16A can be easily performed by utilizing a well-known solder ball forming technique.

【００３８】続いて、半導体チップ２をパッケージ基板
１にフェースダウンボンディングする。これは以下のよ
うにして行う。Then, the semiconductor chip 2 is face-down bonded to the package substrate 1. This is done as follows.

【００３９】まず、図１１（ａ）に示すように、ツール
２６によって半導体チップ２を保持して、この半導体チ
ップ２の一主面をパッケージ基板１の一主面に対向さ
せ、両者間にハーフミラー２７を配置した状態で、半導
体チップ２の一主面に配置されているＡｕバンプ電極１
４Ｂおよび半田バンプ電極１６Ｂの位置座標を、ハーフ
ミラー２７を介して画像解析装置２８に入力する。これ
によって、半導体チップ２のバンプ電極のパターンを認
識する。次に、図１１（ｂ）に示すように、ハーフミラ
ー２７を９０度回転して、今度はパッケージ基板１の一
主面に配置されているＡｕバンプ電極１４Ａおよび半田
バンプ電極１６Ａの位置座標を、ハーフミラー２７を介
して画像解析装置２８に入力する。これによって、パッ
ケージ基板１のバンプ電極のパターンを認識する。First, as shown in FIG. 11 (a), the semiconductor chip 2 is held by the tool 26, one main surface of the semiconductor chip 2 is opposed to one main surface of the package substrate 1, and a half is interposed between the two. The Au bump electrode 1 arranged on one main surface of the semiconductor chip 2 with the mirror 27 arranged.
The position coordinates of 4B and the solder bump electrode 16B are input to the image analysis device 28 via the half mirror 27. Thereby, the pattern of the bump electrode of the semiconductor chip 2 is recognized. Next, as shown in FIG. 11B, the half mirror 27 is rotated by 90 degrees, and this time, the position coordinates of the Au bump electrode 14A and the solder bump electrode 16A arranged on one main surface of the package substrate 1 are determined. , To the image analysis device 28 via the half mirror 27. As a result, the pattern of the bump electrodes on the package substrate 1 is recognized.

【００４０】続いて、画像解析装置２８によって半導体
チップ２のバンプ電極のパターンと、これに対応するパ
ッケージ基板１のバンプ電極のパターンとを正確に重ね
合わせるように半導体チップ２あるいはパッケージ基板
１の位置を制御した後、図１１（ｃ）に示すように、ツ
ール２６を下降させる。Subsequently, the position of the semiconductor chip 2 or the package substrate 1 is accurately adjusted so that the pattern of the bump electrode of the semiconductor chip 2 and the corresponding pattern of the bump electrode of the package substrate 1 are accurately overlapped by the image analyzer 28. Then, the tool 26 is lowered as shown in FIG.

【００４１】すなわち、図１２に拡大して示すように、
半導体チップ２を保持したツール２６をパッケージ基板
１に対して下降させ、半導体チップ２を押圧することに
より、対応する各Ａｕバンプ電極１４Ａ、１４Ｂ同士お
よび半田バンプ電極１６Ａ、１６Ｂを同時に熱圧着す
る。これによって、各Ａｕバンプ電極１４Ａ、１４Ｂ同
士は溶融することなく一体に接続されてＡｕバンプ電極
１４が形成される。同時に、各半田バンプ電極１６Ａ、
１６Ｂ同士は溶融して一体化されて半田バンプ電極１６
が形成される。なお、ツール２６およびパッケージ基板
１は半田バンプ電極１６の融点以上で、かつＡｕバンプ
電極１４の融点以下に加熱されているものとする。That is, as shown enlarged in FIG.
By lowering the tool 26 holding the semiconductor chip 2 to the package substrate 1 and pressing the semiconductor chip 2, the corresponding Au bump electrodes 14A, 14B and the solder bump electrodes 16A, 16B are simultaneously thermocompression bonded. As a result, the Au bump electrodes 14A and 14B are integrally connected to each other without melting and the Au bump electrodes 14 are formed. At the same time, each solder bump electrode 16A,
16B are melted and integrated to form solder bump electrode 16
Is formed. It is assumed that the tool 26 and the package substrate 1 are heated above the melting point of the solder bump electrode 16 and below the melting point of the Au bump electrode 14.

【００４２】このように半導体チップ２およびパッケー
ジ基板１のバンプ電極の位置座標を利用して、両者を正
確に重ね合わせることにより、電極パッドの印刷の位置
ずれや、パッケージ基板１の収縮誤差などによって実際
の位置座標が設計座標からずれた場合でも、中心座標同
士を高い精度で一致させることができる。As described above, the position coordinates of the bump electrodes of the semiconductor chip 2 and the package substrate 1 are utilized to accurately overlap the two, so that the printing position of the electrode pads may be misaligned or the package substrate 1 may shrink. Even if the actual position coordinates deviate from the design coordinates, the center coordinates can be matched with each other with high accuracy.

【００４３】続いて、ダム枠１８のメタライズ層１９に
ろう材２０を介してキャップ３を取り付けることによ
り、図１に示したような構造の半導体集積回路装置が完
成する。Subsequently, the cap 3 is attached to the metallized layer 19 of the dam frame 18 with the brazing material 20 interposed therebetween, whereby the semiconductor integrated circuit device having the structure shown in FIG. 1 is completed.

【００４４】このような半導体集積回路装置によれば、
半導体チップ２はこの一主面の外周部に配置された融点
の高いＡｕバンプ電極１４および中央部およびこの付近
に配置された融点の低い半田バンプ電極１６からなる、
融点の異なる２種類のバンプ電極を介して、パッケージ
基板１にフェースダウンボンディングされている。According to such a semiconductor integrated circuit device,
The semiconductor chip 2 is composed of an Au bump electrode 14 having a high melting point arranged on the outer peripheral portion of this one main surface and a solder bump electrode 16 having a low melting point arranged at and around the central portion.
It is face-down bonded to the package substrate 1 via two types of bump electrodes having different melting points.

【００４５】ここで、特に半導体チップ２の一主面の外
周部に配置されるバンプ電極は、機械的応力を受け易く
なっている。一方、中央部およびこの付近に配置されて
いるバンプ電極は、隣接するもの同士で引き合う力が働
くため、機械的応力は受けにくくなっている。Here, particularly, the bump electrodes arranged on the outer peripheral portion of the one main surface of the semiconductor chip 2 are susceptible to mechanical stress. On the other hand, the bump electrodes arranged in the central portion and in the vicinity of the bump electrodes are less susceptible to mechanical stress because the adjacent electrodes exert a pulling force on each other.

【００４６】従って、本実施例のように、特に半導体チ
ップ２の一主面の外周部にＡｕバンプ電極１４を配置し
たことにより、Ａｕは柔軟性に優れているので、機械的
応力が加わったとき、Ａｕバンプ電極１４はこれを緩和
するように作用する。よって、バンプ電極に加わる機械
的応力を緩和して、接続部の信頼性を向上することが可
能となる。Therefore, since the Au bump electrode 14 is arranged on the outer peripheral portion of the one main surface of the semiconductor chip 2 as in the present embodiment, Au is excellent in flexibility and mechanical stress is applied. At this time, the Au bump electrode 14 acts to relieve this. Therefore, it is possible to reduce the mechanical stress applied to the bump electrode and improve the reliability of the connection portion.

【００４７】また、従来ではフェースダウンボンディン
グに用いるバンプ電極は予め半導体チップの一主面に形
成していたが、本実施例では、半導体チップ２の一主面
に予め半田バンプ電極１６ＢおよびＡｕバンプ電極１４
Ｂを形成するとともに、パッケージ基板１の一主面に予
め半田バンプ電極１６ＡおよびＡｕバンプ電極１４Ａを
形成して、各対応するバンプ電極同士を一体化してフェ
ースダウンボンディングに用いるバンプ電極を形成する
ようにしたので、バンプ電極の高さを大きくすることが
でき、従来の略２倍の高さを得ることができる。これに
より、半導体チップ２とパッケージ基板１の熱膨張係数
差に起因した歪みが各バンプ電極１４、１６に加わった
場合でも、高さの大きいバンプ電極が容易に傾くので、
これにより歪みを吸収、緩和することができる。In the past, bump electrodes used for face-down bonding were previously formed on one main surface of the semiconductor chip, but in the present embodiment, solder bump electrodes 16B and Au bumps are previously formed on one main surface of the semiconductor chip 2. Electrode 14
In addition to forming B, the solder bump electrode 16A and the Au bump electrode 14A are previously formed on one main surface of the package substrate 1, and the corresponding bump electrodes are integrated to form a bump electrode used for face-down bonding. Therefore, the height of the bump electrode can be increased, and the height can be about double that of the conventional one. As a result, even when the strain due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the package substrate 1 is applied to the bump electrodes 14 and 16, the bump electrode having a large height easily tilts.
This makes it possible to absorb and relax the strain.

【００４８】図３は、本実施例による半導体集積回路装
置の不良率を従来例と比較して示すグラフで、Ａは本実
施例による結果、Ｂは従来例による結果を示している。
縦軸は累積不良率、横軸は温度サイクル数である。例え
ば、２０％の累積不良率に達する温度サイクル数を比較
すると、従来例では約４０サイクルで達してしまうが、
本実施例では約２００サイクルまで延びている。また、
４０％の累積不良率に達する温度サイクル数は、従来例
では約１００サイクルであるが、本実施例では約７００
サイクルまで延びている。従って、本実施例によれば、
従来よりも約７倍程度に寿命を高めることができること
を示している。FIG. 3 is a graph showing the defect rate of the semiconductor integrated circuit device according to the present embodiment in comparison with the conventional example, where A is the result of the present embodiment and B is the result of the conventional example.
The vertical axis is the cumulative defective rate, and the horizontal axis is the number of temperature cycles. For example, comparing the number of temperature cycles that reach a cumulative defective rate of 20%, the conventional example reaches about 40 cycles,
In this embodiment, it extends to about 200 cycles. Also,
The number of temperature cycles that reaches a cumulative defective rate of 40% is about 100 cycles in the conventional example, but is about 700 in this example.
It extends to the cycle. Therefore, according to this embodiment,
It shows that the life can be extended to about 7 times that of the conventional one.

【００４９】以上のような実施例１によれば次のような
効果が得られる。According to the first embodiment as described above, the following effects can be obtained.

【００５０】半導体チップ２は一主面の外周部に配置さ
れた融点の高いＡｕバンプ電極１４および中央部および
この付近に配置された融点の低い半田バンプ電極１６か
らなる、融点の異なる２種類のバンプ電極を介して、パ
ッケージ基板１にフェースダウンボンディングされてい
るので、バンプ電極に加わる機械的応力を緩和して、接
続部の信頼性を向上することが可能となる。The semiconductor chip 2 has two kinds of different melting points, which are Au bump electrodes 14 having a high melting point arranged on the outer periphery of one main surface and solder bump electrodes 16 having a low melting point arranged at and around the central portion. Since the package substrate 1 is face-down bonded via the bump electrodes, it is possible to reduce the mechanical stress applied to the bump electrodes and improve the reliability of the connection portion.

【００５１】図１３は実施例１の半導体集積回路装置の
他の製造方法を示すもので、融点の低い半田バンプ電極
１６を形成するのに、予め半導体チップ２の一主面のみ
に半田バンプ電極１６Ｂを形成しておくようにした例を
示すものである。この場合、予め形成する半田バンプ電
極１６Ｂはこれ１つで、結果的に融点の高いＡｕバンプ
電極１４と等しい高さ寸法となるように形成される。FIG. 13 shows another method of manufacturing the semiconductor integrated circuit device according to the first embodiment. In order to form the solder bump electrode 16 having a low melting point, the solder bump electrode is previously formed only on one main surface of the semiconductor chip 2. 16B shows an example in which 16B is formed. In this case, only one solder bump electrode 16B is formed in advance, and as a result, the solder bump electrode 16B is formed to have the same height dimension as the Au bump electrode 14 having a high melting point.

【００５２】このような製造方法によれば、パッケージ
基板１に対して半田バンプ電極１６Ａを形成する工程は
不要になるので、この分コストダウンを図ることができ
る。According to such a manufacturing method, the step of forming the solder bump electrodes 16A on the package substrate 1 becomes unnecessary, so that the cost can be reduced accordingly.

【００５３】（実施例２）図１４は本発明の実施例２に
よる半導体集積回路装置を示す概略断面図で、融点の高
いＡｕバンプ電極１４を形成するために、予めＡｕバン
プ電極１４Ｂを形成する際これを半導体チップ２の一主
面の外周部だけでなく、半導体チップ２で最も発熱の多
い位置であるその中央部にも配置するようにした例を示
すものである。(Embodiment 2) FIG. 14 is a schematic sectional view showing a semiconductor integrated circuit device according to Embodiment 2 of the present invention. In order to form the Au bump electrode 14 having a high melting point, the Au bump electrode 14B is previously formed. At this time, this is arranged not only in the outer peripheral portion of one main surface of the semiconductor chip 2 but also in the central portion of the semiconductor chip 2 where heat is most generated.

【００５４】この場合、半導体チップ２の中央部に形成
されたＡｕバンプ電極１４Ｂは信号経路としてだけでな
く放熱体として作用する。すなわち、Ａｕバンプ電極１
４Ｂは半田バンプ電極１６に比べて放熱性に優れている
ので、放熱体として作用させることもできる。In this case, the Au bump electrode 14B formed in the central portion of the semiconductor chip 2 functions not only as a signal path but also as a radiator. That is, the Au bump electrode 1
Since 4B is superior in heat dissipation to the solder bump electrode 16, it can also act as a heat radiator.

【００５５】従って、この実施例２によれば、実施例１
と同様な効果が得られる他に、放熱性を向上できるとい
う効果も得られる。Therefore, according to the second embodiment, the first embodiment
In addition to the effect similar to that obtained, the effect that the heat dissipation can be improved is also obtained.

【００５６】（実施例３）図１５は本発明の実施例３に
よる半導体集積回路装置を示す概略斜視図で、融点の高
いＡｕバンプ電極１４を形成するために、予めＡｕバン
プ電極１４Ｂを形成する際これを半導体チップ２の一主
面の外周部だけでなく、半導体チップ２で最も発熱の多
い位置であるその中央部の近傍として、半導体チップ２
の他の主面の中央部にも配置するようにした例を示すも
のである。(Embodiment 3) FIG. 15 is a schematic perspective view showing a semiconductor integrated circuit device according to Embodiment 3 of the present invention. In order to form the Au bump electrode 14 having a high melting point, the Au bump electrode 14B is previously formed. At this time, not only the outer peripheral portion of the one main surface of the semiconductor chip 2 but also the central portion of the semiconductor chip 2 where the most heat is generated is set as the semiconductor chip 2
It shows an example in which it is arranged also in the central portion of the other main surface.

【００５７】この場合、半導体チップ２の他の主面の中
央部のＡｕバンプ電極１４Ｂを形成する位置には予めＡ
ｕ薄膜を形成しておくようにする。この半導体チップ２
の他の主面に形成されたＡｕバンプ電極１４Ｂは、信号
経路からは独立して、放熱体専用として作用する。In this case, at the position where the Au bump electrode 14B is formed at the center of the other main surface of the semiconductor chip 2, A is previously formed.
Make sure to form a u thin film. This semiconductor chip 2
The Au bump electrode 14B formed on the other main surface acts as a dedicated heat radiator independent of the signal path.

【００５８】従って、この実施例３によれば、実施例１
と同様な効果が得られる他に、実施例２と同様な効果を
得ることができる。しかも、この実施例３では放熱体と
して用いるＡｕバンプ電極１４Ｂは信号経路から独立し
て配置できるので、配置に自由度を持たせることができ
る。Therefore, according to the third embodiment, the first embodiment
In addition to the same effect as the above, the same effect as the second embodiment can be obtained. Moreover, in the third embodiment, since the Au bump electrode 14B used as a heat radiator can be arranged independently of the signal path, the arrangement can be made flexible.

【００５９】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【００６０】例えば、前記実施例では半導体チップの一
主面の外周部に形成する融点の高いＡｕバンプ電極は、
４隅部の電極パッドに対してのみ形成する例で説明した
が、外周部の全部の電極パッドあるいは大部分に対して
形成するようにしても良い。For example, in the above embodiment, the Au bump electrode having a high melting point formed on the outer peripheral portion of the one main surface of the semiconductor chip is
Although the description has been given of the example in which the electrode pads are formed only at the four corners, they may be formed on all or most of the electrode pads on the outer peripheral portion.

【００６１】また、融点の高いＡｕバンプ電極の形成
は、Ａｕ１００％に限らずこれに微量な他の金属を含ま
せたものを用いるようにしても良い。Further, the Au bump electrode having a high melting point is not limited to Au 100%, but a material containing a trace amount of another metal may be used.

【００６２】さらに、本発明は、基板に取り付けた半導
体チップをバンプ電極を介して配線基板に実装するＢＧ
Ａ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージのボ
ール（バンプ）部にも適用することができる。Further, according to the present invention, a semiconductor chip mounted on a board is mounted on a wiring board via bump electrodes.
It can also be applied to a ball (bump) portion of an A (Ball Grid Array) package.

【００６３】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である半導体
集積回路装置の技術に適用した場合について説明した
が、それに限定されるものではない。本発明は、少なく
ともバンプ電極を介して半導体チップを配線基板にボン
ディングする条件のものには適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the technology of the semiconductor integrated circuit device which is the background field of application has been described, but the invention is not limited thereto. The present invention can be applied to the condition that the semiconductor chip is bonded to the wiring board through at least the bump electrode.

【００６４】[0064]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【００６５】半導体チップを配線基板にフェースダウン
ボンディングする複数のバンプ電極は、融点の異なる２
種類の金属で構成されて各々が半導体チップの異なる位
置に配置されているので、バンプ電極に加わる機械的応
力を緩和して、接続部の信頼性を向上することが可能と
なる。The plurality of bump electrodes for face-down bonding the semiconductor chip to the wiring board have different melting points.
Since they are made of different kinds of metals and are arranged at different positions of the semiconductor chip, it is possible to reduce the mechanical stress applied to the bump electrodes and improve the reliability of the connection portion.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１による半導体集積回路装置を
示す断面図である。FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

【図２】図１の主要部の拡大構造を示す断面図である。FIG. 2 is a sectional view showing an enlarged structure of a main part of FIG.

【図３】本発明の実施例１による半導体集積回路装置の
不良率を従来例と比較して示すグラフである。FIG. 3 is a graph showing a defect rate of a semiconductor integrated circuit device according to Example 1 of the present invention in comparison with a conventional example.

【図４】本発明の実施例１による半導体集積回路装置の
一製造方法の一工程を示す斜視図である。FIG. 4 is a perspective view showing one step of a method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図５】本発明の実施例１による半導体集積回路装置の
一製造方法の他の工程を示す斜視図である。FIG. 5 is a perspective view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図６】本発明の実施例１による半導体集積回路装置の
一製造方法のその他の工程を示す斜視図である。FIG. 6 is a perspective view showing another process of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図７】本発明の実施例１による半導体集積回路装置の
一製造方法のその他の工程を示すもので、（ａ）乃至
（ｅ）は断面図である。FIG. 7 shows another step of the method for manufacturing the semiconductor integrated circuit device according to Example 1 of the present invention, in which (a) to (e) are sectional views.

【図８】本発明の実施例１による半導体集積回路装置の
一製造方法のその他の工程を示す断面図である。FIG. 8 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to Example 1 of the present invention.

【図９】本発明の実施例１による半導体集積回路装置の
一製造方法のその他の工程を示す斜視図である。FIG. 9 is a perspective view showing another process of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図１０】本発明の実施例１による半導体集積回路装置
の一製造方法のその他の工程を示す斜視図である。FIG. 10 is a perspective view showing another process of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

【図１１】本発明の実施例１による半導体集積回路装置
の一製造方法のその他の工程を示すもので、（ａ）乃至
（ｃ）は断面図である。FIG. 11 shows another step of the method for manufacturing the semiconductor integrated circuit device according to Example 1 of the present invention, in which (a) to (c) are sectional views.

【図１２】本発明の実施例１による半導体集積回路装置
の一製造方法のその他の工程を示す断面図である。FIG. 12 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to Example 1 of the present invention.

【図１３】本発明の実施例１による半導体集積回路装置
の他の製造方法の一工程を示す断面図である。FIG. 13 is a cross-sectional view showing a step in another method for manufacturing the semiconductor integrated circuit device according to Example 1 of the present invention.

【図１４】本発明の実施例２による半導体集積回路装置
を示す概略断面図である。FIG. 14 is a schematic sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

【図１５】本発明の実施例３による半導体集積回路装置
を示す概略斜視図である。FIG. 15 is a schematic perspective view showing a semiconductor integrated circuit device according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…パッケージ基板、２…半導体チップ、３…キャッ
プ、４、４Ａ…配線、５…電極、６…ＧＮＤ配線、７…
電源配線、８…スルーホール、９…リード、１０、１
３、１７、２０…ろう材、１１…ＧＮＤメタライズ層、
１２…金属ベース、１４…Ａｕバンプ電極、、１４Ａ…
大径のＡｕバンプ電極、１４Ｂ…小径のＡｕバンプ電
極、１５…電極パッド、１６、１６Ａ、１６Ｂ…半田バ
ンプ電極、１８…ダム枠、１９…メタライズ層、２１…
キャピラリー、２２…Ａｕ線、２３…トーチ、２４…Ａ
ｕボール、２５…アンカー部、２６…ツール、２７…ハ
ーフミラー、２８…画像解析装置。1 ... Package substrate, 2 ... Semiconductor chip, 3 ... Cap, 4, 4A ... Wiring, 5 ... Electrode, 6 ... GND wiring, 7 ...
Power wiring, 8 ... through hole, 9 ... lead, 10, 1
3, 17, 20 ... brazing material, 11 ... GND metallization layer,
12 ... Metal base, 14 ... Au bump electrode, 14A ...
Large diameter Au bump electrode, 14B ... Small diameter Au bump electrode, 15 ... Electrode pad, 16, 16A, 16B ... Solder bump electrode, 18 ... Dam frame, 19 ... Metallized layer, 21 ...
Capillary, 22 ... Au wire, 23 ... Torch, 24 ... A
u-ball, 25 ... Anchor part, 26 ... Tool, 27 ... Half mirror, 28 ... Image analysis device.

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップをこの一主面に形成した複
数のバンプ電極を介して配線基板にフェースダウンボン
ディングする半導体集積回路装置であって、前記複数の
バンプ電極は、融点の異なる２種類の金属で構成されて
各々が半導体チップの異なる位置に配置されていること
を特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device in which a semiconductor chip is face-down bonded to a wiring board via a plurality of bump electrodes formed on the one main surface, wherein the plurality of bump electrodes are of two types having different melting points. A semiconductor integrated circuit device comprising a metal and arranged at different positions of a semiconductor chip. 【請求項２】 前記複数のバンプ電極は、融点の高いバ
ンプ電極が半導体チップの一主面の外周部に配置される
とともに、融点の低いバンプ電極が半導体チップの一主
面の中央部およびこの付近に配置されていることを特徴
とする請求項１に記載の半導体集積回路装置。2. The bump electrodes having a high melting point are arranged on an outer peripheral portion of one main surface of the semiconductor chip, and the bump electrodes having a low melting point are provided in a central portion of the one main surface of the semiconductor chip and the bump electrodes having a low melting point. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged in the vicinity. 【請求項３】 前記融点の高いバンプ電極は、半導体チ
ップの少なくとも最も発熱の多い位置の近傍に配置され
ていることを特徴とする請求項１に記載の半導体集積回
路装置。3. The semiconductor integrated circuit device according to claim 1, wherein the bump electrode having a high melting point is arranged at least in the vicinity of a position where most heat is generated on the semiconductor chip. 【請求項４】 前記融点の高いバンプ電極はＡｕあるい
はＡｕを主成分とする金属で構成されるとともに、前記
融点の低いバンプ電極はＰｂ−Ｓｎ系合金で構成される
ことを特徴とする請求項１乃至３のいずれか１項に記載
の半導体集積回路装置。4. The bump electrode having a high melting point is made of Au or a metal containing Au as a main component, and the bump electrode having a low melting point is made of a Pb—Sn alloy. 4. The semiconductor integrated circuit device according to any one of 1 to 3. 【請求項５】 （ａ）一主面に全面的に形成した複数の
電極パッドのうち、中央部およびこの付近の電極パッド
に融点の低いバンプ電極を形成した半導体チップを用意
する工程と、 （ｂ）前記半導体チップの一主面の外周部の複数の電極
パッドに融点の高いバンプ電極を形成する工程と、 （ｃ）一主面に形成した複数の配線および電極のうち、
前記半導体チップの融点の低いバンプ電極の位置に対応
した位置の前記電極に融点の低いバンプ電極を形成する
とともに、前記半導体チップの融点の高いバンプ電極の
位置に対応した位置の前記配線に融点の高いバンプ電極
を形成した配線基板を用意する工程と、 （ｄ）前記半導体チップの一主面と前記配線基板の一主
面とを対向させ、対応する融点の低いバンプ電極同士お
よび融点の高いバンプ電極同士を接続して、半導体チッ
プを配線基板にフェースダウンボンディングする工程
と、 を含むことを特徴とする半導体集積回路装置の製造方
法。5. (a) A step of preparing a semiconductor chip in which bump electrodes having a low melting point are formed on electrode pads in a central portion and in the vicinity thereof among a plurality of electrode pads entirely formed on one main surface; b) a step of forming bump electrodes having a high melting point on a plurality of electrode pads on the outer peripheral portion of the one main surface of the semiconductor chip, and (c) a plurality of wirings and electrodes formed on the one main surface,
A bump electrode having a low melting point is formed on the electrode at a position corresponding to the position of the bump electrode having a low melting point of the semiconductor chip, and a melting point of the wiring at a position corresponding to the position of the bump electrode having a high melting point of the semiconductor chip is formed. A step of preparing a wiring board on which high bump electrodes are formed, and (d) one main surface of the semiconductor chip and one main surface of the wiring board are opposed to each other, corresponding bump electrodes having low melting points and bumps having high melting points A method of manufacturing a semiconductor integrated circuit device, comprising the steps of connecting electrodes to each other and performing face-down bonding of a semiconductor chip to a wiring board. 【請求項６】 （ａ）一主面に全面的に形成した複数の
電極パッドのうち、中央部およびこの付近の電極パッド
に融点の低いバンプ電極を形成した半導体チップを用意
する工程と、 （ｂ）前記半導体チップの一主面の外周部の複数の電極
パッドに融点の高いバンプ電極を形成する工程と、 （ｃ）一主面に形成した複数の配線および電極のうち、
前記半導体チップの融点の高いバンプ電極の位置に対応
した位置の前記配線に融点の高いバンプ電極を形成した
配線基板を用意する工程と、 （ｄ）前記半導体チップの一主面と前記配線基板の一主
面とを対向させ、対応する融点の高いバンプ電極同士を
接続すると同時に前記融点の低いバンプ電極を前記電極
に接続して、半導体チップを配線基板にフェースダウン
ボンディングする工程と、 を含むことを特徴とする半導体集積回路装置の製造方
法。6. (a) A step of preparing a semiconductor chip in which bump electrodes having a low melting point are formed on electrode pads in and around a central portion among a plurality of electrode pads entirely formed on one main surface, b) a step of forming bump electrodes having a high melting point on a plurality of electrode pads on the outer peripheral portion of the one main surface of the semiconductor chip, and (c) a plurality of wirings and electrodes formed on the one main surface,
A step of preparing a wiring board in which bump electrodes having a high melting point are formed on the wiring at positions corresponding to the positions of the bump electrodes having a high melting point of the semiconductor chip; (d) one main surface of the semiconductor chip and the wiring board; Facing the one main surface, connecting corresponding bump electrodes having a high melting point to each other, and simultaneously connecting the bump electrodes having a low melting point to the electrodes, and performing face-down bonding of a semiconductor chip to a wiring board. A method for manufacturing a semiconductor integrated circuit device, comprising: 【請求項７】 前記（ｂ）工程および（ｃ）工程におい
て、融点の高いバンプ電極を複数段にわたって形成する
ことを特徴とする請求項５または６に記載の半導体集積
回路装置の製造方法。7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein bump electrodes having a high melting point are formed in a plurality of stages in the steps (b) and (c). 【請求項８】 前記融点の高い金属としてＡｕあるいは
Ａｕを主成分とする金属を用いるとともに、前記融点の
低い金属としてＰｂ−Ｓｎ系合金を用いることを特徴と
する請求項５乃至７のいずれか１項に記載の半導体集積
回路装置の製造方法。8. The method according to claim 5, wherein Au or a metal containing Au as a main component is used as the metal having a high melting point, and Pb—Sn alloy is used as the metal having a low melting point. 2. A method of manufacturing a semiconductor integrated circuit device according to item 1. 【請求項９】 前記融点の高いバンプ電極をボールボン
ディング法を利用して形成することを特徴とする請求項
５乃至８のいずれか１項に記載の半導体集積回路装置の
製造方法。9. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the bump electrode having a high melting point is formed by using a ball bonding method.
JP7217115A 1995-08-25 1995-08-25 Semiconductor integrated circuit device and manufacturing method thereof Pending JPH0964101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7217115A JPH0964101A (en) 1995-08-25 1995-08-25 Semiconductor integrated circuit device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7217115A JPH0964101A (en) 1995-08-25 1995-08-25 Semiconductor integrated circuit device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH0964101A true JPH0964101A (en) 1997-03-07

Family

ID=16699097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7217115A Pending JPH0964101A (en) 1995-08-25 1995-08-25 Semiconductor integrated circuit device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0964101A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1079601A (en) * 1996-09-02 1998-03-24 Nec Corp Filter
WO2002093638A1 (en) * 2001-05-16 2002-11-21 Fujitsu Limited Mounting structure and mounting method for semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1079601A (en) * 1996-09-02 1998-03-24 Nec Corp Filter
WO2002093638A1 (en) * 2001-05-16 2002-11-21 Fujitsu Limited Mounting structure and mounting method for semiconductor chip

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