JPH096483A - Microcomputer and mobile phone - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce power consumption at power-on reset. [Configuration] When the low power consumption mode designation is determined by the logical state of the external terminal T at the time of power-on reset,
The CPU 11 is put in a sleep state. In this state, the register information in the ROM 17 is transferred to the DMAC 19 under the control of the register information transfer circuit 20.
By performing the initial setting of the peripheral circuits and the like by the DMA transfer based on the register information transferred to 9, the power consumption at the power-on reset is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a technique for reducing power consumption at the time of power-on reset, for example, a technique effectively applied to a mobile phone.

[0002]

2. Description of the Related Art A mobile phone is a voice codec for converting between a voice signal and an electric signal and between an analog signal and a digital signal, generating and checking codes for time division processing and error correction, and transmitting and receiving. A channel codec for assembling and analyzing frames, a modem for modulating and demodulating transmitted and received signals, a CPU (central processing unit) for controlling the operation of each part, a keypad including a numeric keypad, various information Liquid crystal display panel for displaying,
And a liquid crystal drive circuit for driving it. The operating power of each part is supplied by a battery.

In the case of a device including a battery as an operating power source such as the above-mentioned mobile phone, it is extremely important to reduce the power consumption of the LSI in order to make the driving time as long as possible. Therefore, a microcomputer having a sleep mode (low power consumption mode) is applied.

The sleep mode is shifted by the CPU executing a predetermined instruction. In this sleep mode, the clock of the CPU is stopped, so that the power consumption is reduced as compared with the normal operation (both the CPU and the peripheral circuits are operating). Such sleep mode is released by the application of a reset signal or a predetermined interrupt.

As an example of a document describing the sleep mode of a microcomputer, 1989 June
There is "Transistor Technology SPECIAL No7 (page 14)" issued by CQ Publishing Co., Ltd. on March 20.

[0006]

A mobile phone, for example, is
When the power is turned on, it goes into a standby state. It is not necessary to activate all functions in the standby state. It is sufficient to activate only the functions required to detect an incoming call. When it is not necessary to activate all the functions like the standby state,
Naturally, the microcomputer is put into a sleep state.

However, in the conventional system,
In order to shift to the sleep state, in the normal state of the CPU, a command to shift to the sleep mode is issued by the CPU.
You have to do it in. That is, even when the mobile phone enters a standby state when the power is turned on,
Since the built-in registers are initialized by the power-on reset, it is necessary to shift the CPU to the sleep mode by executing the shift mode shift command after the CPU initializes the registers and the like immediately after the power is turned on. . The inventor of the present application examined it, and immediately after power-on, a CP command was issued to enter the sleep mode.
It was found by the inventor of the present application that the CPU must be put into the normal operation mode immediately after the power is turned on in order to be executed by U, and this is a factor that hinders the reduction of the power consumption at the power-on reset. It was

An object of the present invention is to provide a technique for reducing power consumption at the time of power-on reset.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a first means, transfer means (19, 20) capable of controlling data transfer for initial setting of the peripheral circuits (12, 13) immediately after power-on without intervention of the central processing unit (11). ) Is included to form a microcomputer.

Further, as a second means, a judging means (22) for judging that the sleep mode is designated from the logical state of the external terminal immediately after the power is turned on, and the central processing unit based on the judgment result. Without executing the program
A microcomputer is formed by including transfer means (19, 20) for performing data transfer control for initial setting of the peripheral circuits.

At this time, after completion of data transfer for initial setting of the peripheral circuits, a logic circuit (19b) capable of generating an interrupt signal for shifting the central processing unit from the sleep mode to the normal operation mode is provided. Can be provided.

Furthermore, a mobile phone can be formed by including the above microcomputer.

[0015]

According to the above-mentioned first means, the transfer means controls the data transfer for the initialization of the peripheral circuits immediately after the power is turned on without the intervention of the central processing unit. This eliminates the need for program execution by the central processing unit at the time of power-on reset, and achieves reduction in power consumption.

Further, according to the above-mentioned second means, the transfer means transfers the data for initial setting of the peripheral circuit based on the judgment result by the half-hand means without executing the program of the central processing unit. Take control. This puts the central processing unit in the sleep state from the time of power-on reset,
Achieve a reduction in power consumption.

[0017]

FIG. 2 shows a mobile phone which is an embodiment of the present invention.

The mobile phone shown in FIG. 1 is connected to a microphone MP and a speaker SPK, a voice codec 50 for converting between a voice signal and an electric signal and between an analog signal and a digital signal, and time division. A channel codec (T for generating and checking codes for processing and error correction, assembling and analyzing transmitted and received frames, etc.
DMA control circuit) 60, a modem 70 for modulating and demodulating a transmission / reception signal, a microcomputer 213 for controlling operation of each part, a keypad 218 including a numeric keypad, and a liquid crystal for displaying various information. Display panel 217 and liquid crystal drive circuit 216 for driving it
And Further, although not shown, since it is a mobile phone, it has a built-in battery as a power source for operating each unit.

The audio codec 50 is a low-pass filter (LPF) 51 for removing unnecessary high frequency components from the audio signal from the microphone MP, and an A for converting an output signal of the low-pass filter 51 into a digital signal. A / D conversion circuit 53, a compression circuit 55 for compressing the output signal of the A / D conversion circuit 53 and sending it to the channel codec 60 in the subsequent stage, a decompression circuit 56 for decompressing the digital signal from the channel codec 60, A D / A (digital / analog) conversion circuit 54 for converting the output signal of the decompression circuit 56 into an analog signal.
A low-pass filter (LPF) 52 for removing unnecessary high-frequency components from the output signal of the A / A conversion circuit 54, and an output buffer 57 for driving the speaker SPK based on the output signal of the low-pass filter 52 are included. Consists of

Also, the modem 70 has a modulation waveform generating section 75 for generating a modulation waveform based on the output signal from the channel codec 60, and this modulation waveform generating section 7
D / A conversion circuit 73 for converting the output signal of No. 5 into an analog signal, and low pass filter 7 for removing unnecessary high frequency components from the output signal of this D / A conversion circuit 73.
1. A low-pass filter 72 for removing unnecessary high-frequency components from the output signal of the high-frequency unit 80, an A / D conversion circuit 74 for converting the output signal of the low-pass filter 72 into a digital signal, and this A / D And a demodulation circuit 76 for demodulating the output signal of the D conversion circuit 74.

A high-frequency section 80 including a power amplifier for transmission, a synthesizer for generating a carrier signal, an adder for synthesizing the carrier signal with a transmission / reception signal, etc. is coupled to the modem 70, and a transmission / reception antenna 81 is connected. The transmission and reception of a signal at a radio frequency is possible via the.

FIG. 1 shows the microcomputer 213.
Is shown.

The microcomputer 21 shown in FIG.
3 is not particularly limited, but is a CPU 11 for executing a program stored in a ROM (read only memory) 17, a serial I / O (input / output) that enables input / output of signals in a serial format. ) 1
2. A timer 13 for measuring time, a plurality of ports P1 to Pn that enable input and output of various control signals, a RAM (random access memory) 16 used as a work area for arithmetic processing in the CPU 11, and the like, Various information YVA for controlling the operation of each part, ROM 17 in which a program executed by the CPU 11 is stored, a multiplexer (MPX) 18 for switching the data transfer path, and a DMAC (for transferring data without the control of the CPU 11 direct·
Memory access controller) 19, a register information transfer circuit 20 that enables transfer control of register information, and an operation mode determination circuit 22 for operating mode determination. It is formed on one semiconductor substrate such as a substrate. The serial I / O 12, timer 13, ports P1 to Pn, R
The AM 16 and the DMAC 19 are coupled by a system bus BUS so that signals can be exchanged with each other. Further, the ROM 17 has a system bus BU via a multiplexer 18 for switching a transfer path of read information.
S.

The operation mode determination circuit 22 determines the operation mode based on the logical state of the external terminal (external pin) T. The operation modes mentioned here include a normal operation mode (a mode in which the CPU and peripheral circuits operate) and a low power consumption mode (a mode in which the CPU enters a sleep state). For example, when the logic state of the external terminal T is high level, the normal operation mode is designated, and when the logic state of the external terminal T is low level, the low power consumption mode is designated. It That is, depending on the logic state of the external terminal T at the time of power-on reset, the subsequent operation mode is determined as follows.

When the operation mode determination circuit 22 determines that the external terminal T is at the high level immediately after the power supply of the portable telephone of this embodiment is turned on, the operation mode determination circuit 22 outputs the normal operation start signal. S1 is asserted. As a result, the CPU 11 is activated in the normal operation mode by a predetermined power-on reset. In this case, the CPU 11 initializes various registers and the like.

When the logic of the external terminal T is set to the low level and the low power consumption mode is designated, the operation mode determination circuit 22 causes the normal operation start signal S1.
Is not asserted, the CPU 11 is not started by the power-on reset. However, at this time, the hardware (H / W) sleep signal S2 is asserted by logically inverting the output signal of the operation mode determination circuit 22 by the inverter 21, so that the register information transfer circuit 20 outputs the register information. Transfer is controlled. That is, the register information transfer circuit 20 controls the multiplexer 18 to transfer data from the ROM 17 to the DMA.
The transfer path to C19 is formed, and the ROM 17 and the DMA 19 are operation-controlled, so that the ROM 17
The register information stored in advance is transferred to the register in the DMAC 19. The DMAC is not particularly limited.
The register 19 of 19 includes various registers such as a memory address register for designating a memory address at the time of DMA transfer, an address register for designating an address of a transfer destination or a transfer source, a byte count register for designating the number of transfer words, and a mode register. The DMA transfer control is performed based on the setting contents of the register 19a. That is, the DMAC is transferred by register information transfer from the ROM 17.
Register setting in 19 is performed, and based on that, data transfer between the internal memory and the external memory and data transfer between the internal peripheral circuits are enabled. D for DMA transfer
MAC19 occupies the right to use the bus BUS, CP
It is performed without the intervention of U11. By such data transfer, the main peripheral circuits are initialized. For example, the peripheral circuit includes a serial I / O 12 and a timer 13, which are initialized to be in a reception standby state.

When the data transfer is completed,
An interrupt signal INT to the CPU 11 is asserted by the dedicated logic 19b built in the DMAC 19. The CPU 11 is activated by this interrupt, and thereafter the normal operation is performed. That is, as shown in FIG. 3, even if the high-potential-side power supply Vcc is supplied to each unit by turning on the power of the mobile phone of this embodiment, the CPU 1
1 is a state in which the internal clock is stopped (H / W sleep state), and the operation of the peripheral circuit initialized by the data transfer by the DMAC 19 is started. Then, after the initialization of the registers is completed, the interrupt signal INT is asserted by the dedicated logic 19b in the DMAC 19, so that the sleep state of the CPU 11 is released, and the CPU 11 is released.
When the internal clock is generated, the normal operation mode is entered. As described above, in the low power consumption mode, the interrupt signal INT from the DMAC 19 is asserted after the power is turned on, so that the CPU
Since the sleep state of 11 is released, the power consumption at the power-on reset can be suppressed as compared with the normal operation mode in which the CPU 11 is started immediately after the power is turned on. Further, since the low power consumption mode is not realized by the CPU executing a predetermined command immediately after the power is turned on, but is realized immediately after the power is turned on without the intervention of the CPU, a power-on reset is performed. The maximum power consumption value of can be kept low.

According to the above embodiment, the following operational effects can be obtained.

(1) The logic state of the external terminal T designates the low power consumption mode, which is the operation mode determination circuit 2
If it is determined by 2, the register information transfer circuit 2
By the control of 0, the register information of the ROM 17 is DMAC
19, the peripheral circuits and the like are initialized by DMA transfer based on the register information transferred to the DMAC 19, and then the sleep state of the CPU 11 is released by the interrupt signal INT from the dedicated logic 19b. Therefore, the power consumption at the time of power-on reset can be suppressed. The low power consumption mode is a mode that is realized without the intervention of the CPU immediately after the power is turned on, unlike the mode that is realized by the CPU executing a predetermined command after the power is turned on. Can be kept low. This is valid even in the case where a telephone connected to the communication line supplies operating power from the communication line.

(2) Due to the action and effect of the above (1), the life of the battery can be extended in the mobile phone using the battery as the operating power source.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention. Yes.

For example, in the above embodiment, after the data transfer by the DMAC 19 is completed, the dedicated logic 19b is used.
Thus, the interrupt signal INT to the CPU 11 is asserted. However, when the signal is received via the serial I / O 12, the interrupt signal INT can be asserted. In other words, in the low power consumption mode immediately after turning on the power, serial I / O12,
Only the minimum necessary functions are activated in the reception standby state, and when a signal is received via the serial I / O 12 or when transmitting from this mobile phone, the CP
The interrupt signal INT to U11 is asserted.

When a batch rewritable flash memory is used as the ROM 17, on-board writing of programs and register information to the flash memory (information writing in a state where the ROM is mounted on the board) is possible. It is said that On-board writing is usually CP
U11 executes a predetermined program for on-board writing, and this on-board writing is performed by the DMAC.
By passing through 19, it is possible to perform at high speed without the intervention of the CPU 11.

In the above description, the case where the invention made by the present inventor is mainly applied to the mobile phone which is the background field of application has been described, but the present invention is not limited thereto and various microcomputers are used. It can be applied to applied equipment.

The present invention can contribute to the condition that at least the CPU and its peripheral circuits are included.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the CPU after the power-on reset
Since the initialization is performed by transferring the data to the peripheral circuit before the power-on reset, the CPU does not need to intervene in the initialization immediately after the power-on reset, so that the CPU is in the sleep state after the power-on reset. Therefore, it is possible to reduce the power consumption at the time of power-on reset.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a microcomputer applied to a mobile phone which is an embodiment of the present invention.

FIG. 2 is a block diagram of an overall configuration example of the mobile phone.

FIG. 3 is a timing diagram of mode switching in the microcomputer.

[Explanation of symbols]

 11 CPU 12 Serial I / O 13 Timer 16 RAM 17 ROM 18 Multiplexer 19 DMAC 19a Register 19b Dedicated logic 20 Register information transfer circuit 21 Inverter 22 Operation mode determination circuit 50 Voice codec 51, 52, 71, 72 Low-pass filter 53, 74 A / D conversion circuit 55 compression circuit 54,73 D / A conversion circuit 57 output buffer 60 channel codec 70 modem 75 modulation waveform generation unit 76 demodulation circuit 213 microcomputer 216 liquid crystal drive circuit 217 liquid crystal display panel 218 keypad

Claims (4)

[Claims] 1. In a microcomputer including a central processing unit and its peripheral circuits, data transfer for initial setting of the peripheral circuits immediately after power-on can be controlled without intervention of the central processing unit. A microcomputer comprising means. 2. A central processing having a normal operation mode for executing a program in synchronization with an internal clock and a sleep mode by stopping the internal clock, and capable of shifting from the sleep mode to the normal operation mode in response to an interrupt signal. In a microcomputer including a device and its peripheral circuit, a determination means for determining that the sleep mode is specified from a logical state of an external terminal immediately after power-on, and based on a determination result of the determination means A transfer means for performing data transfer control for initial setting of the peripheral circuit without executing a program of the central processing unit. 3. A logic circuit capable of generating an interrupt signal for shifting the central processing unit from the sleep mode to the normal operation mode after data transfer for initial setting of the peripheral circuits is completed. The described microcomputer. 4. A mobile phone comprising the microcomputer according to claim 1 or 2 and a modem whose operation is controlled by the microcomputer.