JPH0962655A - Multiprocessor system - Google Patents

Abstract

(57) [Summary] [Purpose] To start the slave processors early and reduce the synchronization processing between the master and slave processors. [Structure] When started from a scalar processing unit (SPU), a vector processing unit (VPU) has L bits 915.
Is set to enter the instruction execution state. After booting, the SPU
A plurality of initialization data such as the start address of vector data is sequentially sent to the VPU, and the scalar register group 6 in the VPU
01 and set the corresponding V bit 620 to 1. The execution control unit 303 waits until the initialization data required by the vector instruction to be executed next is set up, and the instruction holding unit 33 for the resource that executes the vector instruction, for example, 306.
6 where it controls execution of the instruction. When the last instruction in the vector instruction sequence is issued, L bit 91
5 is reset and the SPU waits for this reset before starting and setting up. After that, the above operation is repeated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a main processor and a slave processor which is started by the main processor and executes a process designated by the main processor based on data transferred from the main processor.

[0002]

2. Description of the Related Art A vector processor is used as a computer that executes at high speed the operation of array data that frequently occurs in conventional scientific and technological calculations. It is also known to configure a vector processor with a scalar processing unit, a vector processing unit, and a main memory shared by them. For example, the document "HITAC Scalar-820" issued by the present applicant
See Processor Manual, 6020-2 ". Here, the vector processing unit operates as a slave processor that pipeline-processes the array data to be continuously processed by the DO loop as vector data, and the scalar processing unit controls activation of the vector processing unit. It operates as a main processor which gives appropriate data to this vector data. More specifically, the scalar processing unit has a main memory address for each of a plurality of vector data to be processed by the vector processing unit, the number of elements of vector data to be processed (vector length), an address of a program to be executed, etc. To the vector processing unit, and the vector processing unit has a plurality of vector registers and a plurality of pipeline arithmetic units, and loads necessary vector data from the main memory into the vector register according to these initialization data, The vector arithmetic operation is performed on these vector data with the pipeline arithmetic unit using the vector register loaded with the vector data, the obtained vector data is stored in the appropriate vector register, and the finally obtained result vector data Is stored in the main memory. Such a series of processing is executed using a series of vector instructions, and this series of vector instructions is equal to the number of vector data elements (vector register length) that can store each vector data to be processed in the vector register. It is divided into an element group made up of a number of elements and repeatedly executed for a plurality of vector data made up of each element group. On the other hand, the scalar processing unit, while the vector processing unit is processing the vector data from any of the element group, as the initial setting data for the vector data consisting of the next element group, data that specifies the next vector data, Specifically, the main storage address for the vector data is calculated, the calculated address is supplied to the vector processing unit, and the unit is activated. Hereinafter, the above operation is repeated until all the element groups to be processed are processed.

The processing speed of such a vector processor is affected by the method of starting the slave processor by the main processor. Specifically, how to give the initial setting data from the main processor to the slave processor, its timing, the activation timing of the slave processor, and the like affect the processing speed.
In particular, it is important to start the slave processor so that the time required for the master processor to boot the slave processor is reduced and the master processor and the slave processor operate in parallel as much as possible.

In Japanese Patent Publication No. 22418/1990 (first prior art), it is devised to reduce the time required to transfer the initialization data from the scalar processing unit to the vector processing unit. That is, before the vector processing unit executes a series of vector instructions, all of the plurality of initialization data for the vector data to be processed thereby are sequentially supplied to the working scalar register group provided in the vector processing unit, By the instruction to start the vector processing unit, after transferring a plurality of initialization data in this scalar register group to the original scalar register group that can be specified by the vector instruction in the vector processing unit, Start the vector processing unit. While the vector processing unit is executing this series of vector instructions, the scalar processing unit calculates the initialization data necessary for the next execution of this series of vector instructions, and stores it in the scalar register group for work. When it is set and it is detected that the execution of the series of vector instructions is completed, the instruction for activating the vector processing unit is executed again. As a result, the second series of vector instructions
In the subsequent executions, the vector processing unit can execute the series of vector instructions again without delay after the execution of the series of vector instructions.

JP-A-62-159268 (second section)
In the prior art), the activation delay at the first execution of the series of vector instructions is reduced. That is, a series of vector instruction sequences to be executed by the vector processing unit is divided into a plurality of partial instruction sequences, and for each divided partial instruction sequence,
A plurality of initialization data required for executing the partial instruction sequence are set up from the scalar processing unit to an appropriate scalar register in the vector processing unit, and then the vector processing unit is activated. After completing the execution of the first partial instruction sequence, the vector processing unit suspends the execution of the instruction until the initialization data for the next partial instruction sequence is supplied from the scalar processing unit. The scalar processing unit, after activating the execution of the first partial instruction sequence, calculates a plurality of initialization data necessary for the execution of the next partial instruction sequence in parallel with the execution of the first partial instruction sequence, It is supplied to another suitable scalar register in the vector processing unit to instruct the vector processing unit to cancel the suspension of instruction execution. In response to the cancellation instruction, the vector processing unit executes the next partial instruction sequence by using the initialization data set at this time. In this way, when a method of executing the partial instruction sequence by the vector processing unit every time a partial initialization data required by each partial instruction sequence is supplied, a series of The vector processing unit can be started before all the initialization data necessary for executing the vector instruction are set up, and the execution start timing of the series of vector instruction sequences can be advanced.

[0006]

As a result of the inventor of the present invention studying the second prior art, the above prior art improves the data transfer time in the data transfer path connecting the scalar processing unit and the vector processing unit. I found that there is something to do. That is, the transfer time of the initialization data from the scalar processing unit to the vector processing unit depends on the length of the transfer path connecting them. The operation clocks of the scalar processing unit and the vector processing unit are shortened, and the processing speed of these processing units tends to be significantly increased. However, it is difficult to significantly reduce the length of the transfer path because the two processing units are mounted on different mounting boards. As a result, the ratio of the transfer time to the processing time of the entire vector processor is increasing as compared with the increase of the speed of the processing unit.

In particular, in the second conventional technique, a series of vector instructions executed by the vector processing unit is divided into a plurality of partial instruction sequences, and each partial instruction sequence is executed between the vector processing unit and the scalar processing unit. It is necessary to synchronize at the end. Specifically, until the vector processing unit executes the vector instruction suspension instruction, the scalar processing unit is kept waiting to execute the instruction execution suspension cancellation instruction for the next partial instruction sequence. This waiting occurs for each partial instruction sequence. Although the second conventional technique does not describe how the scalar processing unit detects that this wait has been resolved, if the ordinary technique is adopted, the scalar processing unit can perform vector processing. It is necessary to read the status information in the unit to determine whether or not this wait has been resolved. In this way, the time required for the scalar processing unit to read the state information in the vector processing unit depends on the length of the data transfer path between them, and as described above, this time depends on the total processing time. The percentage is increasing. Particularly, in the second conventional technique, a series of vector instructions to be executed by the vector processing unit is divided into a plurality of partial instruction sequences, and the above-mentioned check is performed for each partial instruction sequence. That is, the larger the number of partial instruction sequences, the more sets of the above-mentioned instruction execution suspension instruction and instruction suspension suspension cancellation instruction must be executed. Therefore, the total time required for the above checks increases. By the way, in the above-mentioned first conventional technique, this check may be performed once for each execution of a series of vector instructions.

Further, the same problem becomes more noticeable when a scalar processing unit which can supply initialization data only at a speed lower than the operation clock is used. That is, some commercial scalar processors of recent years have a high operation clock, but can supply data to the outside only in a cycle longer than the cycle of the clock. When such a scalar processor is used as the scalar processing unit of the above vector processor, the time required to set up a plurality of initialization data in the vector processing unit is relatively large in the time required to execute the processing of the entire vector processor. Increase to. Therefore, even in the method of setting up the necessary initialization data for each partial instruction sequence as in the second conventional technique, it is necessary to set up a plurality of initialization data for a plurality of instructions included in the partial instruction sequence. Of course, the time required to set up these initial setting data relatively increases due to the decrease in the data transfer cycle of the scalar processing device.

Further, in the vector processor according to the first or second prior art, different vector data sets are sequentially executed by the vector processing unit with the same instruction sequence. Therefore, during execution of this vector instruction sequence, the scalar processing unit sets up the initialization data that specifies a set of vector data to be processed next in the vector processing unit. In the first prior art described above, as described above, two register groups are used, and a plurality of initialization data are sequentially set up in one of them so that this setup can be performed in parallel with the execution of a series of vector instructions. After that, the vector processing unit was activated again, and at the time of this activation, the plurality of initialization data were transferred in parallel to the other register group. This method requires two sets of registers and further a circuit for transferring a plurality of initialization data in parallel between these registers.

The above-mentioned problems may occur in a multiprocessor including a main processor and a slave processor, in addition to the above vector processor. In particular, when the slave processor has a small number of processes to be executed in parallel with the processes executed by the slave processor after the slave processor is activated, the same problem occurs.

Therefore, an object of the present invention is to provide a method for starting a slave processor that can start the slave processor earlier and a multiprocessor for the same.

Another object of the present invention is to permit the start of execution of a vector instruction sequence when a part of the initialization data has been set up in the slave processor, and yet to synchronize the execution of instructions between the main processor and the slave processor. (EN) Provided is a method of starting a slave processor and a multiprocessor therefor, which makes it possible to reduce the time required for the above.

It is still another object of the present invention that, after the current series of processing in the slave processor is completed, the next plurality of initializations necessary for causing the slave processor to re-execute the series of processing for different data. It is an object of the present invention to provide a method for starting a slave processor and a multiprocessor system for the same, in which data can be set up by a simpler circuit before the execution of the current series of processes in the slave processor is completed.

[0014]

To achieve the above object, in a multiprocessor system according to the present invention, a main processor has a starting means for instructing the slave processor to execute a series of instructions and an execution of the series of instructions. A plurality of registers for holding one of the plurality of initialization data, and a means for supplying one of the plurality of initialization data to the slave processor. An instruction executing means for executing the series of instructions in response to the execution instruction, the supplying means supplies the plurality of initial setting data after the slave processor is activated, and the instruction executing means includes: If the next instruction to be executed out of the series of instructions requests the initialization data held in any one of the plurality of registers, the initialization data valid in that one register Instruction execution control means for controlling the execution of the instruction so that the instruction is executed when it has already been written, and when the initialization data has not been written, the instruction is executed after waiting. Have.

As described above, in the present invention, since a plurality of initialization data are supplied to the slave processor after the slave processor is activated, after the initialization data is set up,
Immediately execution of instructions in the slave processor can be started in parallel with the master processor. Moreover, since the slave processor waits for each initialization data to be set up before executing the instruction that uses the initialization data, the synchronization between the initialization data setup by the main processor and the execution of the instruction that uses it is synchronized. Easy to do.

In a more specific embodiment of the multiprocessor system according to the present invention, the main processor comprises a starting means for instructing the slave processor to execute a series of instructions, and a plurality of initial units required for executing the series of instructions. The slave processor sequentially supplies setting data to the slave processor, and the slave processor sequentially outputs the series of instructions in response to the execution instruction from the main processor and a plurality of registers each holding initial setting data. It has an instruction decoding means for decoding and an instruction executing means for executing the processing required by each decoded instruction, and a plurality of instruction executing means for executing any one of a plurality of processings required by different instructions. things and,
Decoding information of at least one instruction that is provided corresponding to the plurality of instruction executing means and that can be executed by the corresponding instruction executing means is held, and the corresponding instruction executing means stores the decoding information based on the held decoding information. A plurality of instruction holding means for executing an instruction and whether or not any instruction decoded by the decoding means is executable, and when it is executable, decoding information of the instruction is used to execute the instruction. An instruction issuing means for sending to an instruction holding means corresponding to the instruction executing means, wherein the instruction issuing means has initialization data in which any one of the decoded instructions is held in any one of the plurality of registers. In the case of requesting reading of the initialization data, the initialization data is read from the one register, and is supplied to one of the plurality of instruction holding means together with the decoding information of the decoded instruction, The slave processor, when a specific instruction located after the plurality of instructions that need to read the plurality of initialization data included in the series of instructions is issued by the instruction issuing means, Further includes means for generating and holding read completion information indicating that the reading of the plurality of initialization data from the plurality of registers by the instruction of is completed, and the main processor is configured to store the series of instructions in a plurality of other instructions. Means for reading the read completion information from the holding means in parallel with the execution of the series of instructions by the slave processor, when the information is stored in the plurality of initialization data. When the read completion is indicated, the slave processor is restarted, and when the read completion information indicates that the read is not completed, this information indicates the read completion. After waiting a to further include a means for restarting the slave processor.

When there is a means for issuing each decoded instruction to any of the plurality of instruction holding means provided in the slave processor as described above, the initialization data required by the instruction at the time of issuing this instruction is stored. Since the data is read from the plurality of registers and sent to any of the command holding means together with the decoding information of the command, the reading of the initial setting data is completed at this sending stage. Even when the instruction is held in the one instruction holding unit and is not yet executed, when a specific instruction indicating the end of the series of instructions included in the series of instructions is executed, All of the preceding commands that require initialization data have been issued, so in response to this specific command,
It can be considered that all the initialization data in the plurality of registers have been read. At this point, the execution of the preceding instruction that has already been issued may not be completed yet. However, in the above embodiment, before the subsequent execution of such a preceding instruction is completed, the plurality of registers Assuming the read is complete, the master processor can restart the slave processor and transfer the initialization data to it in parallel with the execution of the instruction in the slave processor.

As described above, in this multiprocessor system, since the respective initialization data are transferred from the plurality of registers to any of the instruction holding means, the reading of all the initialization data held in these registers is completed. The timing can be earlier than the completion timing of the execution of the instruction utilizing these initialization data. In addition, this is mainly due to the means for transferring the initialization data to the plurality of instruction holding means and the means for generating and holding the information indicating the completion of reading in response to the specific instruction, which is a relatively simple circuit. realizable.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiprocessor system according to the present invention will be described below in more detail with reference to the embodiments shown in the drawings.

<Embodiment 1> The multiprocessor system shown in FIG. 1 is a vector processor comprising a main memory 100, a scalar processing unit (SPU) 200 and a vector processing unit (VPU) 300 connected thereto.
The SPU is a main processor that executes scalar processing and controls activation of the VPU. The VPU is a slave processor that executes vector processing specified by the SPU.

In the SPU, the instruction fetch unit 201
Fetch a series of scalar instructions to be executed from the main memory 100, decode the fetched instructions sequentially by the decode unit 202, and execute the execution control unit 203.
Controls the execution of the instruction according to the instruction of the decoded instruction. For example, if the decoded instruction is an instruction for performing an operation on scalar data, the execution control unit 203 includes a register group (hereinafter, referred to as a general-purpose register (GR) and a floating-point register (FR)).
The GR / FR register group) 204 and the arithmetic unit 205 are appropriately controlled to execute the instruction. When the instruction is an instruction to use the data in the main memory 100 for the calculation, or the data obtained as a result of the calculation is stored in the main memory 10
When it is an instruction to write to 0, the cache 206 is controlled to read or write the data. An instruction for performing such a scalar operation is, for example, an address of a vector instruction string to be executed by the VPU, a base address or a vector length of vector data used by the instruction is read from the main memory 100, or these are calculated. Contains the instructions to calculate.

If the decoded instruction is an instruction for setting initial setting data such as a base address of vector data to be processed by the VPU, the execution control unit 2
03 is a GR for transferring data from the GR / FR register group 204 to the register group control unit 600 in the VPU.
The reading of the / FR register group 204 is controlled. If the instruction decoded by the decode unit 202 is an instruction to activate the VPU, the execution control unit 203
Checks the execution state of the VPU, and when the execution of the vector instruction sequence is completed, the execution control unit 203 uses the signal line 550 to execute vector processing such as vector instruction address and vector length. The VPU is notified of the initial setting data of and the VPU is activated.

The VPU is provided with a vector register group 305, and each vector register holds vector data to be subjected to the operation held in the main memory 100 and is used for supplying to the operation pipeline 305. , Or used to hold the result vector data from it. The VPU has multiple resources, for example:
A calculation pipeline 305 or a load store pipeline 306 is also provided. Arithmetic pipeline 305
Is a circuit that pipeline-wise executes the same operation on a plurality of elements forming vector data. The load / store pipeline 306 is a circuit that pipeline-loads the vector data in the main memory 100 into one of the vector registers, or pipeline-stores the vector data in one of the vector registers into the main memory 100. is there.

The VPU is provided with a sufficient number of operation pipelines 305, which enable vector operations to be executed in parallel on different vector data.
Further, in the VPU, a sufficient number of load / store pipelines 306 are provided so that different vector data can be loaded or stored in parallel. However, in FIG. 1, only one of these operation pipelines or load / store pipelines is shown for simplification.

When the VPU is activated by the SPU, the instruction fetch unit 301 sequentially fetches a series of vector instructions designated by the SPU from the main memory 100, and sequentially decodes the vector instructions fetched by the decode unit 302. The execution control unit 303 determines whether the decoded vector instruction can be issued. That is, it is determined whether the resource required by the instruction, for example, the arithmetic pipeline 305 or the load store pipeline 305 is available, and if the resource is available, the decoding information of the instruction (for example, , The type of operation or processing to be executed, the number of the vector register to be used), and the instruction holding unit 335 or 336 provided corresponding to the resource.
When this instruction requires initialization data in any of the scalar registers, the instruction execution control unit 303 issues the instruction after confirming that the data is already held in the scalar register. . In issuing the instruction, the data is read from the scalar register and transferred to the instruction holding unit 335 or 336 as a part of the decoding information of the instruction.

Instruction holding unit 335 or 336
Controls the resource corresponding to the instruction holding unit so as to temporarily hold the decoding information transferred from the execution control unit 303 and execute the processing specified by the decoding information. For example, if there is a preceding instruction using the corresponding resource, after the execution of the instruction is finished, the corresponding resource is based on the held decoding information,
The arithmetic pipeline 305 or load / store pipeline 306 is activated to execute the processing required by the instruction. The instruction holding unit 335 or 336 instructs reading of vector data to any of the vector registers designated by the decoding information in the vector register group 304 according to the decoding information held therein, or the processing of the processing. The writing of the vector data obtained as a result of the execution is instructed to the vector register designated by the decoding information in the vector register group 304. As outlined above, the technique of using the execution control unit 303 for controlling the instruction issue and the instruction holding unit 335 or 336 corresponding to each resource in the VPU is as follows.
It has already been described in JP-A-1-128162. In this embodiment, when the execution control unit 303 issues any instruction, if the instruction requires initialization data in any scalar register, the initialization data is already Issue the instruction after confirming that it has been written in the scalar register, and at the time of issuing the instruction, read the initialization data from the scalar register and read the initialization data from the instruction decoding information. It differs from the prior art in that it is transferred to one of the instruction holding units as a part of. further,
In the instruction holding unit 335 or 336, when the transferred instruction decoding information includes the initial setting data, the instruction holding unit 335 or 336 also holds the initial setting data until the processing specified by the instruction decoding information is executed. It differs from the prior art in that the initialization data is sent to the corresponding resource at the time of execution and is used for the processing.

In the present embodiment, after activating the VPU, the SPU sequentially supplies the initialization data such as the base address required for loading the vector data to be processed by the VPU in the order required by the VPU. Has become. The register control unit 620 sequentially sets these initial setting data in a scalar register designated by the SPU in the scalar register group 601, and
The valid bit V provided corresponding to each scalar register is set.

In executing an instruction, the execution control unit 303 generally determines whether or not a resource, such as an arithmetic pipeline, required for the execution of the instruction is available, and when the resource is available, the instruction is executed. When issuing the instruction, when the instruction requires the initialization data held in any of the scalar registers, the instruction is issued after determining whether the initialization data is available. In this embodiment, when the instruction is an instruction to load or store vector data, the initialization data stored by the SPU in any one of the scalar register group 601 is used as the base address of the vector data. It is supposed to do.

The execution control unit 303 issues the instruction when the initialization data has already been written to the scalar register, and otherwise waits for the initialization data to be written before executing the instruction. Issue. Whether or not the initial setting data is written in the scalar register is determined by whether or not the value of the valid bit V corresponding to the scalar register is 1. When the execution control unit 303 determines that the instruction can be issued, the initialization control unit 303 reads the initialization data from the scalar register designated by the instruction, and decodes the instruction together with the resource required by the instruction, for example, load store. Transfer to the instruction holding unit 336 corresponding to the pipeline 306. The instruction holding unit 336 executes its load or store instruction when the corresponding resource becomes available.

The VPU contains a specific instruction vlnk at the end of the sequence of instructions, which instruction execution unit 303.
Issued by the register control unit 600,
The validity bit group V620 corresponding to the scalar register group 601 is reset, and the initialization unit 350 sets the read completion bit L indicating the completion of the reading of the initialization data in the scalar register group 601 to 1.

SPU is a VPU scalar register group 60.
After transferring a plurality of initialization data to 1, while the VPU is executing the series of vector instructions, the series of vector instructions causes the VPU to be activated again in order to process another vector data next. . In starting this,
Whether or not the reading of the initialization data in the scalar register group 601 by the VPU is completed is determined by the reading completion bit L. When the reading is not completed, the completion of the reading is waited. When the reading is completed, the SPU sequentially sets up the next plurality of initialization data including the base address of the vector data to be processed by the VPU in the VPU. After that, the VPU repeats the same operation as described above. After that, the SPU and VPU further repeat the same operation.

In the VPU, the fact that a plurality of instructions issued before the vlnk instruction are actually executed in any resource may be delayed considerably from the time when each instruction is issued. However, at the time of issuing the vlnk instruction, the initialization data in the scalar registers specified by the instructions preceding the instruction have already been read from those scalar registers at the time of issuing the preceding instructions. There is. Therefore, in the present embodiment, the read completion bit L is set to 1 upon the issuance of the vlnk instruction, so that the scalar register group 601 can be executed before the execution of the series of instructions is completed. In addition, the following plural initial setting data can be set up from the SPU.

As described above, in this embodiment, the SPU is V
After starting the PU, set the initial setting data such as the base address to V
In the PU, the instructions are sequentially set, and in the VPU, the instruction that uses the VPU waits for the necessary data to be set by the SPU before executing the instruction. Therefore, since the vector instruction that uses the initialization data can be executed immediately after the initialization data is set, the VPU can be executed early.

Furthermore, the SPU need only activate the VPU once for execution of a series of vector instructions. Therefore, the process of waiting for the SPU to wait for the completion of the reading of the already-set-up initial setting data by the VPU needs to be performed only once, and therefore the waiting time is short.

Further, as described above, the initialization data in the scalar register required at the time of issuing each instruction is read and transferred to the instruction holding unit provided corresponding to the resource required by the instruction, At the time point after the issuance of the vlnk instruction, which is the last instruction of the group of instructions, a plurality of subsequent initialization data can be set in the scalar register group 601 from the SPU.

The circuit of this embodiment and its operation will be described below with reference to a specific example of an instruction sequence. FIG. 5 is a Fortran program which describes an example of processing to be processed by the vector processor of FIG. As already described, in the vector processor of FIG. 1, the VPU has a plurality of operation pipelines 305 and load / store pipelines 306, and the same processing can be executed in parallel on different vector data. ing. In order to utilize this fact, the program of FIG. 5 describes this product-sum operation by four arithmetic expressions so that the vector processor of FIG. ing.

This program is composed of a triple DO loop for executing a so-called sum of products operation in which the result of adding the two-dimensional array Z to the product of the two-dimensional array X and the two-dimensional array Y becomes a new two-dimensional array Z. When only the innermost loop is vectorized, the array Z and the array Y are treated as vector data, and each element of the array X is treated as scalar data. That is, the processing of the first expression of this innermost loop is performed by the vector data consisting of N pieces of data belonging to the j-th column of the array Z (hereinafter, this may be referred to as vector data Z0) and the k-th array of the array Y. A vector sum consisting of N pieces of data belonging to a column and an element at the k-th row and the j-th column of the array X is calculated, and the vector data consisting of the N elements obtained by the sum-of-products operation is used to form an array. It is performed as a vector operation to replace the jth column of Z. After this process, the intermediate D
According to the O loop, the value of j is changed by 4 and the array Z
The sum of products operation is performed using the vector data consisting of the elements belonging to the other columns of, the other one element of the array X, and the same vector data as on the array Y. Further, according to the outermost loop, the above processing is executed while changing the value of k.

The processes described in the second to fourth sentences of the innermost loop are also executed as similar product-sum operations for different element groups of the array data Z (i, j). The vector data, which is processed by these second to fourth equations and consists of different element groups of the array Z (i, j), will be referred to as vector data Z1, Z2, Z3 below. Elements of the array data X (i, j) used for calculation of these vector data Z0, Z1, Z2, Z3 are X0, X1, X respectively.
2, X3.

As described above, in the program of FIG. 5, one DO loop processes a plurality of vector data each consisting of N elements. In the apparatus of FIG. 1, each vector data is processed element by element equal to the length of the vector register (in this embodiment, it is assumed that the length of each vector register is 512). Therefore, each vector data on the main memory 100 is actually 512
It is processed by dividing it into a set of individual elements. That is, at the first execution of a series of vector instructions, the set of the first 512 elements of each vector data is stored from the main memory 100 into any of the vector registers, and the operation pipeline 305
And processed.

After execution of a series of vector instructions, the next set of 512 elements of each vector is similarly processed by the same series of vector instructions. Each of these 512 sets of vector data is also called vector data. Each time a series of vector instruction sequences is executed, the SPU calculates initialization data necessary for the execution of the instruction sequence or fetches it from the main memory 100, and the VPU scalar register group 6
Set it up to 01.

SPU to execute the program of FIG.
6 (a-1) and 6 (b-) respectively show an outline of a scalar instruction sequence to be executed by the VPU and a vector instruction sequence to be executed by the VPU.
1), and a flowchart of the processing of the scalar instruction sequence and the vector instruction sequence is shown in FIG.
It shows in (b-2). Furthermore, in FIG. 7 (a) and FIG.
Details of the scalar instruction sequence and the vector instruction sequence shown in (a-1) and (b-1) are shown.

As shown in FIG. 7A, the scalar instruction sequence is roughly divided into four scalar instruction sequences 1, 2, 3, and 4. Scalar instruction sequence 1 includes two mtvpr instructions that set up initialization data. These instructions set up the initialization data whose value does not change at each repetition of the vector instruction sequence among the initialization data that the SPU should set up in the VPU. The scalar instruction sequence 2 includes an exvp instruction that activates the VPU, and
However, the vector instruction sequence (this is vco
This command is activated after confirming that the execution of (de) is completed. That is, the scalar instruction sequence 2 waits until the read completion bit L becomes 0 by a loop using the bc instruction, and L =
When it becomes 0, the exvp instruction is issued. The scalar instruction sequence 3 is the vector instruction sequence vcode.
Among the initialization data required by the VPU, a plurality of initialization data whose values change each time the vector instruction is repeated
Command sequence for setting up any of the initial setting data to be set up from the main memory 100 to G
An instruction to load the R / FR register group 204 or G
It includes instructions to calculate any initialization data to be set up using the data in R / FR register group 204. The scalar instruction sequence 4 is a vector instruction sequence vcode.
Conditional branch instruction b for instructing to repeat the scalar instruction sequence again from the scalar instruction sequence 2 for the next execution of
c.

As described above, the scalar instruction sequence of this embodiment is
It is characterized in that it includes an instruction exvp for activating the VPU before the necessary initialization data is set up by the scalar instruction sequence 3. Another feature is that the scalar instruction sequence 3 is executed after waiting for the completion of reading the initialization data in the scalar register group in the VPU when executing the instruction exvp. Further, by the scalar instruction sequence 1, the initialization data that is repeatedly used every time the vector instruction sequence is repeated but its value does not change
Another feature is that it is set up in advance before U is started.

The vector instruction sequence vcode is shown in FIG.
In addition to the vector instruction sequence 11, the instruction 12 which is not a vector instruction is actually included. Among the vector instructions included in the vector instruction sequence 11, the instruction using the initialization data set up in any of the scalar register groups 601 is the V instruction provided corresponding to the scalar register.
The execution control unit 303 confirms that the bit is 1, and issues the instruction. Instruction 12
Is an instruction vlnk for notifying the VPU that issuance of the instruction in the VPU is completed. This instruction is executed when the issuance of the vector instruction sequence 11 is completed, and is read in the initial control unit 350 of the VPU. The completion bit L is reset to 0. When the L bit is reset by this vlnk instruction, the instruction fetch unit 301, the decode unit 302, etc. know that there is no subsequent instruction to be executed. The SPU can detect the end of the issuance of all the vector instructions in the vector instruction sequence vcode by looking at the L bit. Further, this instruction resets the V bit corresponding to the scalar register set up by the scalar instruction sequence 3 in the scalar register group 601, to 0, whereby the VPU newly initializes the scalar register group 601 from the SPU. It makes it possible to detect when data is set up. This instruction vlnk can specify a scalar register whose corresponding V bit should be reset to 0.

Hereinafter, the execution of the instruction sequence of FIG. 7 will be described in more detail with reference to the time chart of FIG. This figure is
The state of instruction execution in the case where the activation and execution of vcode is repeated twice outside is shown. In FIG. 8, the hatched portions indicate the execution of one vector instruction.

(Initialization Data to be Set Up in VPU) Initialization data to be set up in the VPU by the SPU in order to execute the processing specified by the program shown in FIG. 5 is as follows.

(A) Main memory address vcode of the first instruction in the vector instruction sequence to be executed (b) Vector data length N (The lengths of a plurality of vector data to be processed are all determined to be the same. (C) Main memory address interval between adjacent elements of vector data Z and Y (hereinafter referred to as stride) (this is assumed to be the same value for vector data Z and Y in this embodiment). (D) Start main storage address of vector data Y (hereinafter referred to as base address) (this is vector instruction string vcod
(It does not change every time e is executed.) (e) Start main storage address of vector data Z0, Z1, Z2, Z3 (hereinafter referred to as base address) (this changes every time the vector instruction string vcode is executed) ( f) Among the elements of the vector data X, the elements X0, X1, X2, X3 used for the product-sum operation with each of the vector data Z0, Z1, Z2, Z3 (these change each time the vector instruction sequence is executed) (Setup of Initial Setting Data by SPU (Part 1)) In the present embodiment, the scalar instruction sequence 1 is the above (c).
The data of (d) is sequentially set up in the VPU before starting the VPU. These setups have two mtv
It is performed by the pr instruction. The mtvpr instruction is an instruction for setting data in a scalar register in the VPU, and
U writes the initialization data specified by this instruction to the scalar register specified by this instruction and sets the corresponding V bit to 1. Specifically, when the mtvpr instruction is decoded in the decode unit 202 in the SPU, the execution control unit 203 causes the GR in the SPU to
Of the registers in the / FR register group 204, the stride or the base address of the vector data Y held in the register designated by each setup instruction mtvpr is read and transferred to the register control unit 600 in the VPU via the line 701. To do.

At this time, the number of the scalar register designated by the instruction is also transferred. Register group control unit 600
Then, as shown in FIG. 2, the write control unit 603
Write the initialization data transferred to the scalar register having the number of the scalar register transferred from the SPU in the scalar register group 601, and select the selector 6
By controlling 07, 1 is written in the V bit corresponding to this scalar register in the V bit group 602. In FIG. 8, the first two black circles indicate that these two initial setting data are sequentially set up.

(Activation of VPU by SPU) The first instruction exvp in the scalar instruction sequence 2 is an instruction for instructing activation of the VPU, the L bit 915 in the VPU is checked, and if the value is 1, that is, , If the reading of the scalar register group 601 by the vector instruction is not completed in the VPU, the condition code is set and the instruction is terminated.
The second instruction of the scalar instruction sequence 2 is a conditional branch instruction bc, and if the condition code is checked by checking the condition code, the designated instruction address, in this case, the address 1 of the exvp instruction Branch off. Therefore, SP
The U waits for the VPU to finish reading the scalar register group 601 by these two instructions.

When the L bit 915 is 0 when the exvp instruction is executed, that is, when the reading of the scalar register group 601 by the vector instruction is completed, the vector instruction address (here Then this is also expressed as vcode) and the vector length N is VP
The U is notified, the L bit 915 is instructed to be set to 1, and the execution of the instruction is ended. Specifically, when the exvp instruction is decoded in the decode unit 202 in the SPU, the execution control unit 203 causes the VP shown in FIG.
The value of the L bit 915 in U's initial control unit 350 is obtained via line 550-0. When the value of the L bit 915 is 1, a condition code is set in a condition code register (not shown), and this instruction ends.

When the L bit is 0, the execution control unit 203 initially controls the vector instruction address (vcode in this case) and the vector length N specified in the operand of the exvp instruction via the line 550-1. Unit 35
Send to 0. In the initial control unit 350, the instruction fetch activation unit 917 sends the vector instruction address vcode to the instruction fetch unit 301 via the line 552 and activates the instruction fetch. Also, the vector length setting unit 920 uses the line 557.
The vector length N is sent to the execution control unit 303 via -1. Further, the set control unit 916 sets the L bit 915 to 1. When L bit 915 becomes 1, line 553 activates instruction decode unit 302 to start decoding the instruction fetched by instruction fetch unit 301.

Reading the L-bit 915 via line 550 requires time for the signal to travel back and forth on line 550. Generally, the VPU is mounted on a separate mounting board from the SPU and the line 550 is compared. Become longer. Therefore, execution of the instruction exvp requires multiple cycles. For this reason, in FIG. 8, the execution time of the scalar instruction sequence 2 extends over a plurality of cycles. Also, as can be seen from FIG.
For the same reason, there is a delay between the execution of the instruction exvp and the change of the L bit from the value 0 to 1.

(Execution of Vector Instruction Sequence (1)) The vector instruction in the vector instruction vcode is composed of the following five partial instruction sequences. The first instruction vlfd is an instruction for loading the vector data Y into the vector register, and the vector data Y is the vector data Z0, Z1, Z2,
Commonly used for each calculation of Z3. Second instruction vl
The fourth instruction vstd from fd loads the vector data Z0 into the vector register from the main memory 100, executes the product-sum operation of the vector data Z0, the vector data Y, and the element X0 to generate new vector data Z0. After calculating and storing the result in the vector register, a process of storing the result vector data Z0 in the main memory 100 from the vector register is performed. Similarly, the fifth instruction vlfd to the seventh instruction vstd are vector data Z.
This is an instruction for calculating 1. The eighth instruction vlfd to the tenth instruction vstd are instructions for calculating the vector data Z2. The eleventh instruction vlfd to the thirteenth instruction vstd are instructions for calculating the vector data Z3.

In the VPU, the execution control unit 303
It is determined whether or not the first instruction of the fetched vector instruction sequence vcode can be issued, and if it can be issued, the instruction is immediately issued. In this case, the first instruction vlfd
Is a load instruction of vector data, and loads vector data designated by this instruction from the main memory 100 to the vector register designated by this instruction. The base address and stride required to calculate the vector data address are read from the two scalar registers specified by this instruction. However, when at least one of the two V bits corresponding to these scalar registers is 0, this instruction is issued after waiting for both V bits to become 1. If both of these V bits are set to 1, it means that the necessary data has been written to the scalar register group 601, and therefore, from the two scalar registers designated by this instruction in the scalar register group 601, the base address Read the stride and issue this command.

In the case of the program shown in FIG. 7, the leading vl
The fd instruction is an instruction for loading the vector data Y into the vector register, and the base address and stride required by this instruction have already been set up in the scalar register by the scalar instruction sequence 1 before the VPU is activated. Therefore, this load instruction can be issued and is issued immediately.

The second instruction of the vector instruction string vcode is an instruction to load the vector data Z0 from the main memory 100. The initialization data required by this command is
Since it has not been set up by the Scalar Instruction Sequence 1, this instruction is issued after those initialization data from the SPU have been set up.

More specifically, control of instruction execution in the VPU is performed as follows. When the vector instruction is decoded in the decode unit 302 in the VPU, the decode result is sent to the execution control unit 303 via the line 503. At the same time, when the instruction as a result of decoding refers to a scalar register, an instruction is given to the register group control unit 600 via the line 509. In the register group control unit 600, as shown in FIG. 2, the read control unit 605 reads the content of the scalar register designated through the selector 608 and sends it to the line 702-1, in accordance with the instruction on the line 509. The value of the V bit corresponding to the scalar register designated through the selector 609 is read and the line 702 is read.
-Send to 0.

The execution control unit 303 (see FIG. 4) is
The decoded instruction is transferred to the instruction register 80 via the line 503.
Receive to 0. In the contents of the instruction register 800, information about the type of instruction is fetched by the pipe check unit 804, and status display units 801 and 8 showing the operating statuses of the operation pipeline and the load store pipeline, respectively.
It is compared with the contents of 02 to see if the instruction can be issued. Each of the status display units 801 and 802 has a line 505.
-1, 506-1, the operating status of the operation pipeline 305 or the load / store pipeline 306 is notified. An instruction can be issued if a pipeline (resource) capable of executing the instruction is free. In this embodiment, whether or not this resource is actually available is determined by whether or not the instruction holding unit provided corresponding to the resource can hold a new instruction.

Information about which register is used in the contents of the instruction register 800 is fetched by the register check unit 805, and the vector register status display unit 803 showing the operating status of the vector register group 304.
Is compared to the value of the V bit indicated by line 702-0 to see if the instruction may be issued. The operating status of the vector register group 304 is notified to the vector register status display unit 803 via a line 504-1. When the read / write port of the required VR register is empty and the value of the V bit corresponding to the scalar register that needs to be read is 1, the instruction can be issued.

When both the pipe check unit 804 and the register check unit 805 determine that the instruction can be issued, the instruction issuing unit 806 issues the instruction.
That is, the value of the scalar register received from the line 702-1 and the type of the instruction received via the line 812 are transferred to the operation pipeline 305 or the load / store pipeline 306 via the line 505-0 or the line 506-0. Send out. The vector length received from the line 557-1, the number of the vector register received via the line 813, and the read / write status are sent to the vector register group 304 via the line 504-0. In addition, line 81
Pipeline operation status display unit 801,
802 and vector register operating status display unit 8
Update 03.

When the V bit corresponding to the scalar register designated by the instruction is 0, the issuing unit 806 waits until it becomes 1 before issuing the instruction.
When the instruction is issued, the contents of the scalar register designated by the instruction are read, and the resource required by the instruction, for example, an instruction holding unit provided corresponding to the load / store pipeline 306, for example, 336.
It is transferred with the decoding information of the instruction. Thus, when the instruction is issued, the reading of the scalar register required by the instruction is completed.

When the instruction issued by the issuing unit 806 is transferred to any instruction holding unit, eg, 336, the instruction holding unit corresponds to the decoded information of the transferred instruction and the instruction decoded information. And temporarily store the initialization data read from the scalar register, and when the corresponding load store pipeline 306 becomes available, the instruction decoding information and the initialization data that are held are used. , Instructing the corresponding resource to execute the processing requested by the instruction.

In the present example, for the first instruction vlfd of the vector instruction string vcode, the load / store pipeline 306 mainly sets the vector data Y based on the base address of the vector data Y set up by the SPU. The memory 100 loads one vector register designated by this instruction.

(Setup of Initial Setting Data by SPU (Part 2)) In the scalar instruction sequence 3, the VP described above is used.
Among the initial setting data to be set up in U, eight initial setting data described in (e) to (f) are set up. The scalar instruction sequence 3 is composed of four partial instruction groups for generating initial setting data necessary for processing each of the vector data Z0 to Z3 by the four arithmetic expressions of FIG. 5 and setting it up in the VPU. There is.

That is, the first instruction m of the scalar instruction sequence 3
The fourth instruction add from tvpr is vector data Z0.
It is a scalar instruction sequence related to the processing of. The first instruction mtvpr sets up the base address of the vector data Z0 stored in the general-purpose register in advance in the scalar register designated by this instruction. Second instruction lfdu
Is the array data X used to calculate the vector data Z0.
It is an instruction to load one element X0 of (i, j) into the floating point register in the SPU. Third instruction fmtvp
r is an instruction to set up the loaded data X0 in a scalar register in the VPU. Fourth instruction a
dd is an addition instruction for calculating the base address of vector data to be processed at the time of the next execution of the vector instruction vcode as the currently processed vector data Z0 of the vector data Z. The fifth instruction mtvpr to the eighth instruction add are similar instructions related to the processing of the vector data Z1. 9th instruction mtvpr to 1st
The second instruction add is a similar instruction related to the processing of the vector data Z2. 13th instruction mtvpr to 1st
The instruction add of 6 is a similar instruction related to the processing of the vector data Z3.

(Execution of Vector Instruction Sequence (Part 2)) When the first instruction mtvpr in the scalar instruction sequence 3 sets up the initialization data in the scalar register in the VPU, the second instruction vlfd in the vector instruction sequence vcode becomes This instruction is ready to issue and is issued immediately because both the required initialization data (ie, the base address and stride of the vector data Z0) are available. Third instruction vfmad in vector instruction vcode
d is a product that adds the vector data Y in the vector register and the data X0 in the scalar register to the scalar product of the vector data Z0 in another vector register, and replaces the original vector data Z0 with the result. This is an instruction to execute a sum operation. This instruction is issued when the initialization data X0 required by this instruction is set up by the third instruction lfdu in the scalar instruction sequence 3 executed by the SPU. The second and first vector instructions for loading the vector data Z0, Y required by this instruction into an appropriate vector register are already being executed.
Therefore, the third vector instruction vfadd uses the data loaded by these second and first instructions in parallel with loading the subsequent elements of these vector data by these instructions. This usage method is so-called chaining and is known per se. In this embodiment, a circuit for this purpose is also incorporated in the apparatus of FIG. 1, but is not shown for simplification. Vector instruction v
The fourth instruction vfstd of code is an instruction to store the vector data Z0 calculated by the third instruction from the vector register in the main memory 100. The initialization data required by this instruction is the base address and stride of this vector. This fourth instruction vfstd can be executed subsequent to the third instruction because these data have been set up in the scalar register by the already executed instruction.

Similarly, vector data Z1 and Z
A plurality of instructions for executing the processing of 2 and Z3 are also issued immediately as soon as the initialization data necessary for the execution of these instructions are set up from the SPU.

(Execution of vector link instruction vlnk) After the vector instruction sequence is issued, the vector instruction sequence vc
The last instruction vlnk of the ode is the instruction issue unit 804.
Issued and executed by. In the program of Figure 7,
This instruction resets the V bit to 0 for the scalar registers other than the two scalar registers holding the base address of the stride and vector data set up by the scalar instruction sequence 1 executed by the SPU before the activation of the VPU. This data is used also when the vector instruction string vcode is executed next time.
In addition, the L bit 915 is reset to 0, and the SPU
Is notified that the issuance of the vector instruction sequence vcode is completed.

The execution of this instruction is executed as follows. Vln in the decoding unit 302 in the VPU
When the k instruction is decoded, the decoding result is sent to the execution control unit 303 via the line 503. The execution control unit 303 (see FIG. 4) performs the following processing after all the preceding vector instructions have been issued. Ie line 7
The reset instruction of V bit designated by the instruction is sent to the register group control unit 600 via 02-2, and the reset instruction of L bit is sent to the initial control unit 350 via line 557-0. Register group control unit 6
00 (see FIG. 2), the reset control unit 604 is instructed by the line 702-2 to set the V bit designated by the selector 607. In the present example, the vector data Y, Z.
And the V bit corresponding to a scalar register other than the two scalar registers holding the base address of the vector data Y. In the initial control unit 350 (see FIG. 3), the reset control unit 919 sets the L bit 915 to 0 according to the instruction on the line 557-0. When the value of the L bit becomes 0, this value is notified to the instruction decode unit 302 by the line 553, and the instruction decode unit 302 finishes decoding the instruction.

Thus, when the instruction vlnk is executed,
The VPU is in a state of waiting for activation from the SPU,
Repeats the scalar instruction sequences 2 and 3 already described. When the scalar instruction sequence 3 is repeated, in the scalar instruction sequence 3, another element data of the array X (i, j) is transferred to the data X0,
Set up on the VPU as X1, X2, X3.

In the above embodiment, when issuing an instruction,
Since the data in the scalar register required by the instruction is referenced, the vlnk instruction 12 is issued and the L bit becomes 0.
When, the reference of all scalar registers referred to by the vector instruction sequence vcode is completed. Therefore S
The exvp instruction in the scalar instruction sequence 2 is executed again by PU,
Further, even if a new value is written to the scalar register by the scalar instruction sequence 3, the vector instruction sequence vcod currently being executed is
It does not adversely affect the execution of e. Also, by the vlnk instruction 12 located at the end of the vector instruction sequence vcode,
Since the validity bit V corresponding to each scalar register is reset, when executing the instruction sequence 11 in the next activated VPU, be sure to wait for the second execution of the scalar instruction sequence 3 in the SPU before the scalar register is executed. Since it refers to the value of, it never accidentally refers to the previous value. However, SPU
V of the scalar register set in the scalar instruction sequence 1
Since the bit has not been reset by the vlnk instruction 12, it can be read repeatedly over and over again.

As described above, in this embodiment, after the VPU is activated by the SPU, the initialization data is sequentially set up in the scalar register as the scalar instruction sequence 3 is sequentially executed by the SPU, and the validity corresponding to each scalar register is set. As the bit V is set and each initial setting data is set up, vector instructions in the VPU instruction sequence 11 can be sequentially issued. Therefore, the execution of the vector instruction sequence can be started immediately after starting the setup of the initialization data. Therefore, the execution time of the vector instruction sequence can be shortened.

Further, even when the cycle of supplying a plurality of initialization data from the SPU is long, the execution of the vector instruction sequence of the VPU can be started at the stage when a small number of initialization data have been set up. You can reduce the delay of completion of.

Further, in the present embodiment, the SPU may wait for the completion of the read-out of the already-set-up initialization data only once while executing the vector instruction sequence once. Therefore, when the vector instruction sequence is repeatedly executed, the total amount of time required for this waiting can be reduced.

In the embodiment, although a plurality of initial setting data are set up before the VPU is started, the VPU cannot be started during the setting of these initial setting data. However, these initial setting data are a vector instruction string. Since it is also used during the repetition of, there is no need to newly set up during this repetition, so that the processing of the VPU can be speeded up accordingly.

Furthermore, when the instruction issuing unit issues an instruction, the initialization data in the scalar register is read out and held in the instruction holding unit corresponding to the resource, so the last instruction vlnk of the vector instruction string vcode is issued. At that point, the reading of the scalar register group by the vector instruction sequence can be completed. For this reason, some instructions of this vector instruction sequence are
While being executed in U, a new set of initialization data can be set up in parallel for the next execution of the vector instruction sequence in the VPU. Therefore, V
When a vector instruction sequence is repeatedly executed by PU,
Their execution can continue. Moreover, setting up the initialization data for the next execution of this vector instruction sequence during execution of the vector instruction sequence is achieved by using a circuit for reading out the initialization data required by the instruction issued at the time of issuing the instruction, and Data can be realized with a simple circuit such as an instruction holding unit corresponding to resources.

<Modification> (1) In FIG. 1, the SPU and VPU are lines 500 and 701.
Although it is directly connected by the above, it may be connected by a bus.

(2) Although FIG. 1 shows a vector processor having a main processor and a scalar processing unit and a vector processing unit as slave processors, the present invention comprises a main processor and a slave processor which are not directly related to vector processing. It can also be applied to multiprocessors.

(3) In the embodiment, the instruction issuing unit is
The instructions in the vector instruction sequence vcode were issued in the decoding order of those instructions. However, as is already known in the vector processor, if one of the decoded instructions cannot be issued, the subsequent instruction is issued until the instruction becomes ready to issue. It is also possible to adopt the technology of issuing after passing. When using this overtaking technique, the vector instruction sequence vcode
Is not issued past the preceding instruction. At least, it is not issued prior to the issuance of the instruction using the initialization data held in any of the scalar registers located before this instruction. That is, this v
Since the read completion bit 1 is set by the lnk instruction, at the time of issuing this vlnk instruction, it is necessary to issue all the above-mentioned instructions using the initialization data. To this end, it is necessary to wait for the vlnk instruction to be issued until the initialization data read by the instruction preceding the vlnk instruction is completed.

(4) In the present embodiment, if the VPU is configured to execute only a predetermined series of instructions, the SP is activated when the SPU activates the VPU.
U does not need to specify to the VPU the sequence of instructions to be executed.

(5) The technique of this embodiment is based on the VP of this embodiment.
It is also applicable to other multiprocessors including a main processor and a slave processor that perform processing different from U and SPU. In them, the initial setting data set up by the main processor may not be the data designating the data to be processed by the slave processor as described in the embodiment but may be the data itself to be processed.

[0082]

According to the present invention, an instruction or an instruction sequence utilizing this data can be executed in the slave processor immediately after the start of the setup of a plurality of initialization data by the main processor. In addition, it is possible to reduce the total amount of time required to wait for the completion of the read-out of the initialization data that has been set up by the slave processor, which is necessary for restarting the slave processor.

Further, during execution of an instruction in the slave processor, initialization data for the next execution of the instruction sequence in the slave processor can be set up by a simple circuit.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a vector processor according to the present invention.

2 is a schematic configuration diagram of a register control unit in a vector processing unit used in the apparatus of FIG.

3 is a schematic configuration diagram of an initial control unit in a vector processing unit used in the apparatus of FIG.

4 is a schematic configuration diagram of an instruction issue control unit in a vector processing unit used in the apparatus of FIG.

5 is a diagram showing an example of a Fortran program showing processing to be executed by the apparatus shown in FIG.

6 is a flowchart showing the flow of execution of the program of FIG.

7 is a diagram showing an example of a program executed by the apparatus of FIG.

8 is a timing chart showing a pattern of instruction execution in the apparatus of FIG.

[Explanation of symbols]

601 ... Scalar register group, 602 ... Effectiveness display bit group, 915 ... Scalar register group read completion display bit L.

Claims (20)

[Claims] 1. A main processor and a slave processor connected to the main processor, wherein the main processor is required to execute a series of instructions and an activation means for instructing the slave processor to execute the series of instructions. Means for sequentially supplying a plurality of initialization data to the slave processor, wherein the slave processor has a plurality of registers for holding one of the plurality of initialization data and the execution from the main processor. An instruction executing means for executing the series of instructions in response to an instruction, the supplying means supplies the plurality of initial setting data after the slave processor is activated, and the instruction executing means includes the series of instructions. If the next instruction to be executed requests the initialization data held in any one of the plurality of registers, valid initialization data has already been written to that one register. Multiprocessor having instruction execution control means for controlling the execution of the instruction so that the instruction is executed when the instruction is present, and otherwise the instruction is executed after waiting for the initialization data to be written in the one register. system. 2. The slave processor holds a plurality of validity information corresponding to each of the plurality of registers and indicating whether or not the corresponding one register holds valid initial setting data. Means for changing any of the initialization information supplied by the main processor to one of the plurality of registers and changing the validity information corresponding to the one register to a value indicating data validity. And the instruction execution control means, among the plurality of registers,
Based on the validity information corresponding to the one register holding the initialization data required by the instruction to be executed next, it is detected whether or not the valid initialization data is written in the one register. The multiprocessor system according to claim 1, further comprising means. 3. The main processor executes the series of instructions based on a plurality of other initialization data,
After waiting for completion of reading the plurality of initialization data from the plurality of registers by the series of instructions,
2. The multiprocessor system according to claim 1, further comprising means for restarting the slave processor, and means for supplying the plurality of other initialization data to the slave processor after the restart. 4. The slave processor further includes means for holding read completion information indicating whether or not the read of the plurality of initialization data from the plurality of registers is completed, and the slave processor is In response to the activation by the main processor, there is a means for changing the read completion information into information indicating that the read is not completed, and the instruction executing means is included in the series of instructions.
A means for changing the read completion information to a value indicating that the reading by the series of instructions is completed in response to a specific instruction located after the plurality of instructions requiring reading of the plurality of initialization data. Then, the restart means reads the read completion information from the holding means, and when this information indicates the completion of the read of the plurality of initialization data, restarts the slave processor, and the read completion information is 4. A means for restarting the slave processor when waiting for the information to indicate that the reading is completed when the reading is not completed.
The described multiprocessor system. 5. The slave processor holds a plurality of validity information indicating whether or not valid data is held in a corresponding one of the plurality of registers, and the main processor includes: Each time any one of the supplied initial setting data is written into one of the plurality of registers, there is provided means for changing the validity information corresponding to the one register to a value indicating data validity. Means, among the plurality of registers,
Means for detecting whether or not valid initial setting data is written in the one register based on validity information corresponding to the one register holding the initial setting data required by the instruction to be executed next. The slave processor further includes means for changing the validity information corresponding to the plurality of registers holding the plurality of initial setting information to information indicating data invalidity in response to the specific instruction. Item 4. The multiprocessor system according to Item 4. 6. The main processor sets a part of the initialization data other than the plurality of pieces of initialization information in one of the plurality of registers of the slave processor before the startup of the slave processor by the startup means. Means for changing the validity information corresponding to the plurality of registers in the slave processor, and a part of the validity information corresponding to the some registers is data. The multiprocessor system according to claim 5, wherein the value is not changed to a value indicating invalidity. 7. The multiprocessor system according to claim 4, wherein the specific instruction is an instruction located at the end of the series of instructions and informing the slave processor that there is no subsequent instruction to be executed. 8. The means for changing the validity information corresponding to the plurality of registers in the slave processor is a part of the plurality of registers corresponding to a part of the registers designated by the specific instruction. 6. The multiprocessor system according to claim 5, further comprising means for selectively changing the validity information of the item to a value indicating invalid data. 9. The series of instructions includes a plurality of vector instructions requesting that the same processing be performed on a plurality of elements of vector data, respectively, and the instruction executing means includes a plurality of vector instructions. In response to one, a plurality of vector processing execution means capable of executing the same processing in parallel with each other for a plurality of elements of the vector data designated by the instruction, 8. The multiprocessor system according to claim 1, wherein said vector instruction includes information designating vector data to be processed. 10. A main processor and a slave processor connected to the main processor, wherein the main processor is required to execute a series of instructions and an activation means for instructing the slave processor to execute the series of instructions. Means for sequentially supplying a plurality of initialization data to the slave processor, wherein the slave processor has a plurality of registers respectively holding the initialization data and the series of units in response to the execution instruction from the main processor. Instruction decoding means for sequentially decoding the instructions, and if any of the instructions decoded by the decoding means requires reading of the initialization data held in any one of the plurality of registers, the initialization data From the one register, a means for holding the read initialization data until the processing requested by the decoded instruction is executed, The plurality of initialization data from the plurality of registers according to the series of instructions in response to a specific instruction included in the decree that is located after the plurality of instructions requiring reading of the plurality of initialization data. And holding means for generating and holding read completion information indicating that the reading has been completed, and the main processor is configured to execute the series of instructions by the slave processor in parallel with the completion of reading by the holding means. Means for detecting whether or not information is held, and means for controlling execution of an instruction related to restart of the slave processor depending on whether or not the holding means holds read completion information A multiprocessor system further comprising: 11. A means for controlling execution of an instruction included in the main processor executes an instruction for restarting the slave processor when the holding means holds read completion information, 11. The multiprocessor according to claim 10, further comprising means for executing the instruction for restarting after waiting for the H-hour means to hold the read completion information when the holding means does not hold the read completion information. system. 12. The means for controlling the execution of an instruction included in the main processor executes one of the plurality of initialization data used by the slave processor after the instruction for restarting is executed. 12. The multiprocessor system according to claim 11, further comprising means for sequentially executing a plurality of instructions, one of which is supplied to the slave processor. 13. A main processor and a slave processor connected to the main processor, wherein the main processor is required to execute a series of instructions and an activation means for instructing the slave processor to execute the series of instructions. Means for sequentially supplying a plurality of initialization data to the slave processor, wherein the slave processor has a plurality of registers respectively holding the initialization data and the series of units in response to the execution instruction from the main processor. Instruction decoding means for sequentially decoding the instructions and a plurality of instruction execution means for executing the processing required by each decoded instruction, each of which executes any one of a plurality of processings required by different instructions. And a decoding information of at least one instruction provided corresponding to the plurality of instruction executing means and executable by the corresponding instruction executing means. A plurality of instruction holding means for causing the corresponding instruction executing means to execute the instruction based on the held decoding information, and whether or not any of the instructions decoded by the decoding means can be executed, Decoding information of the instruction when it is executable,
An instruction issuing means for sending the instruction to an instruction holding means corresponding to an executable instruction executing means, wherein the instruction issuing means has any decoded instruction in any one of the plurality of registers. When requesting to read the held initial setting data, it has means for reading the initial setting data from the one register and supplying the decoded information of the decoded instruction to one of the plurality of instruction holding means. The slave processor is included in the series of instructions,
When a specific instruction located after the plurality of instructions requiring the reading of the plurality of initialization data is issued by the instruction issuing means, the plurality of initialization data from the plurality of registers according to the series of instructions The main processor further includes holding means for generating and holding read completion information indicating that the read is completed, and the main processor is configured to store the read completion information in parallel with the execution of the series of instructions by the slave processor. Is held in the holding unit, and when the holding unit holds the reading completion information, the instruction related to the restart of the slave processor is executed, and the holding unit holds the reading completion information. If not, the holding means waits for holding the read completion information and then executes the instruction related to the restart of the slave processor. A multiprocessor system further comprising means. 14. The slave processor holds a plurality of validity information respectively corresponding to one of the plurality of registers and indicating whether or not the corresponding one register holds valid initial setting data. And means for changing validity information corresponding to each of the plurality of registers, in which any of the initialization data supplied by the main processor is written, to a value indicating data validity. The instruction issuance control means, among the plurality of registers,
Means for detecting whether or not valid initialization data is already written in the one register based on validity information corresponding to the one register holding the initialization data required by the decoded instruction. The multiprocessor system according to claim 13, further comprising: 15. The slave processor further includes means for changing validity information corresponding to a plurality of registers holding the plurality of initialization data into information indicating data invalidity in response to the specific instruction. The multiprocessor system according to claim 14. 16. The supply means supplies the plurality of initialization data after the slave processor is activated, and the instruction issuing means stores any decoded instruction in any one of the plurality of registers. When requesting the retained initialization data, issue the instruction if valid initialization data has already been written to that one register, otherwise issue valid initialization data to that one register. The main processor further has a means for supplying the plurality of other initialization data to the slave processor after the restart, after having a command issuance control means for waiting for writing and issuing the command. The multiprocessor system according to any one of claims 13 to 14. 17. The means for changing the validity information corresponding to the plurality of registers in the slave processor is a part of the plurality of registers corresponding to a part of the registers designated by the specific instruction. 17. The multiprocessor system according to claim 16, further comprising means for selectively changing the validity information of the item to a value indicating invalid data. 18. The multiprocessor system according to claim 13, wherein said specific instruction is an instruction located at the end of said series of instructions and which notifies said slave processor of the end of a subsequent instruction to be decoded. 19. The series of instructions includes a plurality of vector instructions for performing the same processing on a plurality of elements of vector data, and the plurality of instruction executing means respectively includes one of the plurality of instructions. In response to a plurality of vector processing execution means capable of executing the same processing in parallel with each other for a plurality of elements of the vector data specified by the instruction, 19. A multiprocessor system as claimed in any one of claims 13 to 18, wherein the instructions include information specifying the vector data to be processed. 20. A master processor and a slave processor connected to the master processor, wherein the master processor sequentially supplies to the slave processor a plurality of initialization data used by a series of instructions to be executed by the slave processor. The slave processor has means for supplying, and the slave processor respectively corresponds to a plurality of registers for holding one of the plurality of initial setting data and one of the plurality of registers, and is effective in the corresponding one register. Means for holding a plurality of validity information indicating whether or not various initial setting data are held, and whenever any one of the initial setting data supplied by the main processor is written in one of the plurality of registers, The instruction executing means has means for changing the validity information corresponding to the one register to a value indicating data validity, and instruction executing means for executing the series of instructions. Means for reading data from a register designated by each instruction in response to a plurality of instructions that require data held in any one of the plurality of registers in the series of instructions, Of the plurality of validity information in response to a particular instruction located after the plurality of instructions using the data held in at least one of the plurality of registers in the series of instructions, Means for changing a part of the validity information corresponding to the plurality of registers designated by the specific instruction to information indicating that the data in the corresponding register is invalid, and in response to the specific instruction, Means for generating and holding read completion information indicating that reading of the data in the plurality of registers by the series of instructions is completed, and the main processor reads the read completion information into the holding means. To detect whether or not completion information is held, and to cause the slave processor to execute the series of instructions based on a plurality of other initialization data when the holding completion information is held in the holding means. Of the plurality of registers, the plurality of instructions are stored in one of some of the registers corresponding to the invalidated part of the validity information. A multiprocessor system consisting of a plurality of instructions for supplying each.