JPH095704A - Display device drive circuit and display device - Google Patents

Abstract

PURPOSE: To reduce power loss without restricting power supply voltage levels. CONSTITUTION: This circuit and device have CMOS transistors TR3, TR4 connected in series in between a power supply voltage terminal +VDD and a power supply voltage terminal -VEE and provided with an inverter part making these CMOS transistors TR3, TR4 alternately conduct in a prescribed cycle and outputting the voltage of the junction point of these CMOS transistors TR3, TR4 as the common voltage driving common electrodes of a liquid crystal display device and variable voltage lowering circuits TR1, TR2, OP1, OP2 adjusting the positive voltage to be impressed from the power supply terminal +VDD on the inverter part and the negative voltage to be impressed from the power supply terminal -VEE on the inverter part to prescribed levels VCOMH, VCOML.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display drive circuit and a display device for periodically shifting the potential of electrodes.

[0002]

2. Description of the Related Art In recent years, flat display devices typified by liquid crystal display devices have become quite popular because of their advantages of thinness, light weight, and low power consumption. A general liquid crystal display device has a structure in which a liquid crystal composition is held between an array substrate and a counter substrate. The array substrate and the opposing substrate have, for example, insulating properties and light transmissivity, respectively, and a liquid crystal cell is formed by filling a gap between the array substrate and the opposing substrate with a liquid crystal composition. The array substrate includes a matrix array of a plurality of pixel electrodes, a plurality of scanning lines formed along rows of these pixel electrodes, a plurality of signal lines formed along columns of these pixel electrodes, and a plurality of signal lines formed respectively. A first alignment film that entirely covers the matrix array of pixel electrodes. Each of the plurality of scanning lines selects a row of the pixel electrodes, and each of the plurality of signal lines is provided for applying a signal voltage to the pixel electrodes of the selected row. The counter substrate has a common electrode facing a matrix array of a plurality of pixel electrodes, and a second alignment film that entirely covers the common electrode. The first and second alignment films are provided for twisting nematic (TN) alignment of liquid crystal molecules in the liquid crystal cell when there is no potential difference between the pixel electrode and the common electrode. When polarized light enters the liquid crystal layer from one substrate side, the polarized light turns along the twist of the liquid crystal molecules arranged in the thickness direction of the liquid crystal layer, is guided to the other substrate, and is further selected via the polarizing plate. Is transparently transmitted. When a potential difference is applied between the pixel electrode and the common electrode, liquid crystal molecules tilt up from a plane parallel to the substrate surface on which an image is displayed by an angle proportional to this potential difference, and change the transmittance of polarized light.

In an active matrix type liquid crystal display device, a plurality of thin film transistors (TFTs) are formed adjacent to intersections of scanning lines and signal lines, respectively, and are used as switching elements for selectively driving corresponding pixel electrodes. . The gate of each TFT is connected to one scanning line, the drain is connected to one signal line, and the source is connected to one pixel electrode. The TFT supplies a signal voltage from a signal line to a pixel electrode when the TFT is turned on with a rising of a scanning pulse from the scanning line. The liquid crystal capacitance CLC between the pixel electrode and the common electrode is charged with a potential difference, and is held even after the TFT becomes non-conductive with the fall of the scanning pulse.

When the electric field is maintained in one direction, substances other than the liquid crystal move in the liquid crystal cell due to this electric field and gather on one electrode side. This causes the life of the liquid crystal cell to be shortened. Conventionally, as a solution to this problem, for example, there is known a technique of reversing the polarity of the signal voltage with the potential of the common electrode as a reference potential so that the electric field direction is reversed in each frame period. Further, the polarity reversal of the signal voltage may be performed, for example, every one horizontal scanning period in order to reduce flicker. The common electrode drive circuit is used to positively shift the reference potential for the purpose of avoiding the increase of the signal voltage amplitude, and the potential of the common electrode is the common voltage VCO generated from the common electrode drive circuit.
Controlled by M. In this case, the signal voltage is level-inverted with reference to the central level, and the common voltage VCOM
Is inverted from one of the high level VCOMH and the low level VCOML to the other every time the level of the signal voltage is inverted.
However, the potential of the pixel electrode is affected by the gate-source capacitance CGS when the TFT becomes non-conductive. That is, the charge on the pixel electrode moves to charge the capacitor CGS, which changes the potential of the pixel electrode to a predetermined level VP (1.3).
V). When the TFT is an N-channel type and the signal voltage changes in the range of 0V to + 5V, it is necessary to set the high level VCOMH to + 3.7V and the low level VCOML to -1.3V.

[0005]

The conventional common electrode drive circuit obtains the above-mentioned common voltage VCOM from the push-pull circuit. This push-pull circuit is +3.7
An NPN transistor connected between the positive power supply terminal and the output terminal for outputting a high level VCOMH of V;
It has a PNP transistor connected between the output terminal and the negative power supply terminal to output a low level VCOML of −1.3 V, and a high level VCOMH and a high level VCOMH depending on the polarity inversion signal POL supplied to the base of these transistors. One of the low level VCOML is selected. Considering the voltage drop corresponding to the base-emitter voltage VBE of the transistor, the voltages at the positive and negative power supply terminals are +6.
It must be fixed at about 5V and -5V. However, these power supply voltages are not used in the display device except the common electrode drive circuit. Therefore, the use of these power supply voltages results in a complicated structure of the DC / DC converter that generates various power supply voltages required for the display device from the external supply voltage which is normally set to + 5V. Further, the voltage drop corresponding to the voltage VBE results in power loss.

An object of the present invention is to provide a drive circuit for a display device and a display device capable of reducing power loss without restricting the power supply voltage level.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to have a CMO connected in series between a first power supply terminal and a second power supply terminal.
An inverter unit having an S transistor, which alternately conducts these CMOS transistors in a predetermined cycle, and outputs a voltage at a connection point of these CMOS transistors as a drive voltage of the display device, and a first power supply terminal is applied to the inverter unit. This is achieved by a drive circuit for a display device, which includes a variable voltage drop unit that adjusts at least one of the first voltage and the second voltage applied to the inverter unit from the second power supply terminal to a desired level.

Further, an object of the present invention is to provide a first electrode substrate having a first electrode arranged on a first insulating substrate, a second electrode substrate having a second electrode electrode arranged on a second insulating substrate, and A light modulation layer held between the first and second electrode substrates, a first electrode drive circuit for driving the first electrode, and a second electrode for driving the second electrode
In the display device including the electrode drive circuit, the second electrode drive circuit is configured to alternately connect the CMOS transistors connected in series between the first power supply terminal and the second power supply terminal at a predetermined cycle so that the CMOS transistor The voltage supply unit includes an inverter unit that outputs the voltage at the connection point to the second electrode, and a voltage supply unit that supplies the first voltage to the first power supply terminal and the second voltage to the second power supply terminal, respectively. This is achieved by a display device including resistance dividing means for resistance-dividing a power supply voltage supplied from the device into a first voltage and a second voltage.

[0009]

In this display device drive circuit, the inverter section has the CMOS transistor connected in series between the first power supply terminal and the second power supply terminal, and the variable voltage drop means is the first.
At least one of the first voltage applied from the power supply terminal to the inverter section and the second voltage applied from the second power supply terminal to the inverter section is adjusted to a desired level. In this case, since there is almost no voltage drop in the inverter section, the power loss of the drive circuit can be reduced by selecting the power supply voltage close to the desired level. Furthermore, since the power supply voltage is adjusted by the variable voltage drop means, it is not necessary to supply the power supply terminal in a stabilized state. Therefore, the external power supply voltage supplied to the display device or various power supply voltages generated from the external power supply voltage in the display device can be used as the power supply voltage of the drive circuit. In other words, it is possible to eliminate the need to generate a power supply voltage in the display device which is used only for this drive circuit.

In this display device, the CMO in which the inverter section is connected in series between the first power supply terminal and the second power supply terminal.
The S-transistor is alternately turned on in a predetermined cycle to form a CMOS
The voltage at the connection point of the transistor is output to the second electrode, and the voltage supply section supplies the first voltage to the first power supply terminal and the second voltage to the second power supply terminal. The resistance dividing means of the voltage supply unit divides the power supply voltage supplied from the outside by resistance division to generate the first voltage.
Voltage and second voltage. In this case, since there is almost no voltage drop in the inverter section, the power loss of the drive circuit can be reduced by selecting the power supply voltage close to the desired level. Further, since the first voltage and the second voltage are obtained by resistance division, various power supply voltages can be used as the power supply voltage of the display device. In other words, it is possible to eliminate the need to generate unnecessarily many power supply voltages.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A common electrode drive circuit according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of this common electrode drive circuit, and FIG. 2 schematically shows the circuit configuration of an active matrix type liquid crystal display device using this common electrode drive circuit.

The liquid crystal display device shown in FIG. 2 is, for example, a normally white mode liquid crystal panel 10 capable of color display.
An X driver 12 and a Y driver 14 electrically connected to the liquid crystal panel 10;
Controller 16 for controlling the Y and Y drivers 14
With.

The liquid crystal panel 10 has a structure similar to the conventional one in which a liquid crystal composition is held between an array substrate having light transmittance and a counter substrate. Array substrate is (640 × 3) ×
A matrix array of 480 pixel electrodes 20 and a scanning line Y formed along each row of these pixel electrodes 20
1 to Y480, signal lines X1 to X640 × 3 formed along the columns of the pixel electrodes 20, respectively, and a first alignment film that entirely covers the matrix array of the pixel electrodes 20. The scanning lines Y1 to Y480 each select a row of the pixel electrodes 20, and the signal lines X1 to X640 × 3
Are provided for applying a signal voltage to the pixel electrodes 20 of the selected row. The counter substrate has a common electrode 22 facing the matrix array of pixel electrodes 20, and a second alignment film that entirely covers the common electrode 22. The first and second alignment films are provided for twist nematic (TN) alignment of liquid crystal molecules in the liquid crystal cell when there is no potential difference between the pixel electrode 20 and the common electrode 22. Two polarizing plates set in directions orthogonal to each other are attached to the outer surfaces of the array substrate and the counter substrate.

For the array substrate, (640 × 3) ×
480 thin film transistors (TFTs) 24 are further provided with scanning lines Y1 to Y480 and signal lines X1 to X640 ×
3 are respectively formed adjacent to the intersections and are used as switching elements for selectively driving the corresponding pixel electrodes 20. The gate of each TFT 24 is connected to one of the scanning lines Y1 to Y480, the drain is connected to one of the signal lines X1 to X640 × 3, and the source is connected to one of all the pixel electrodes 20. Is done. Further, the auxiliary capacitance lines 26 are formed along the rows of the pixel electrodes 20.
Each pixel electrode 20 forms a liquid crystal capacitance CLC by capacitive coupling with the common electrode 22, and an auxiliary capacitance CS by capacitive coupling with the auxiliary capacitance line 26. The gate and the source of each TFT 24 have a parasitic capacitance C formed between them.
Inevitably has GS.

The liquid crystal controller 16 receives gradation data supplied from the outside on a pixel-by-pixel basis, generates a start pulse ST and a shift clock CK in synchronization with the supply timing of the gradation data, and outputs the gradation data to the start pulse S.
It is supplied to the X driver 12 together with T and the shift clock CK. The start pulse ST is generated every horizontal scanning period, and the shift clock CK is generated at each supply timing of 640 × 3 pieces of gradation data sequentially supplied in synchronization with the start pulse ST. The liquid crystal controller 16 further generates a selection signal for selecting one of the scanning lines Y1 to Y480 every horizontal scanning period, and supplies this to the Y driver 14. The shift clock CK is stopped when the gradation data is no longer supplied from outside. In this case, the liquid crystal controller 16 supplies gradation data fixed to a predetermined value representing perfect black to the X driver 12 so as to prevent deterioration of the liquid crystal composition, and at the same time, from 0V to + 5V.
A shutdown signal SHUT which rises to the common electrode drive circuit shown in FIG. In addition, the liquid crystal controller 16 outputs the polarity inversion signal POL that alternately changes from one of 0 V and +5 V to the other for each one frame period and one horizontal scanning period in order to perform the frame inversion drive and the line inversion drive of the pixel electrode. Supply to. The polarity inversion signal POL is also supplied to the common electrode drive circuit shown in FIG.

The X driver 12 is composed of a 640 × 3 stage shift register, an A / D converter, and 640 × 3 latch circuits. The shift register is shift clock C
In response to K, the start pulse ST is transferred to the subsequent stage. A
The / D converter responds to the shift clock CK, and the power supply voltage +
The gradation data is converted into a signal voltage level in the range of 0V to + 5V obtained from VDD (+ 5V). 6
The 40 × 3 latch circuits each latch the output of the A / D converter in response to the start pulse ST transferred to the corresponding stage of the shift register, and respond to the next start pulse ST supplied from the liquid crystal controller 16. Then, the latch voltage is continuously supplied as a signal voltage to the signal lines X1 to X640 × 3, respectively. The gradation data is the liquid crystal controller 1
When fixed to a predetermined value by 6, the A / D converter converts this gradation data into a signal voltage level of + 5V. The A / D converter outputs the signal voltage level converted from the grayscale data when the polarity inversion signal POL supplied from the liquid crystal controller 16 is + 5V, + 2.5V which is the central level in the range of 0V to + 5V. Invert with reference.

The Y driver 14 sequentially selects the scanning lines Y1 to Y480 based on the selection signal from the liquid crystal controller 16, and selects the scanning pulse which rises from -12V equal to the power source voltage -VOFF to + 19V equal to the power source voltage + VON. Supply to. The potential of the non-selected scanning lines is maintained at -12 V, which is equal to the power supply voltage -VOFF.

Each of the TFTs 24 supplies the signal voltage from the corresponding signal line to the pixel electrode 20 when it becomes conductive with the rising of the scanning pulse from the corresponding scanning line. The liquid crystal capacitance CLC between the pixel electrode 20 and the common electrode 22 and the auxiliary capacitance CS between the pixel electrode 20 and the auxiliary capacitance line 26 are charged by this signal voltage. The TFT 24 becomes non-conductive with the fall of the scan pulse, but the potential of the pixel electrode 20 is still held with the potential of the common electrode 22 as a reference after that, and is canceled when the TFT 24 becomes conductive again after one frame period. It

The common electrode drive circuit shown in FIG. 1 is incorporated in the above-mentioned liquid crystal display device to drive the common electrode 22 and the auxiliary capacitance line 26 of the liquid crystal panel shown in FIG. In this liquid crystal display device, as shown in FIG. 1, a power source voltage of +5 V is applied to a D source from a computer or the like via an external power source terminal VEX.
It is supplied to the C / DC converter CNV and the power supply terminal + VDD. The DC / DC converter CNV stabilizes the + 5V power supply voltage from the external power supply terminal VEX at + 19V, -1
It is converted into power supply voltages of 2V and -3V and supplied to power supply terminals + VON, -VOFF, and -VEE, respectively. Common electrode drive circuit is power supply terminal + VON, -VE
+ 19V, -3V and +5 supplied to E, + VDD
Operates with a power supply voltage of V. Where + 19V and -3
The power supply voltage of V is stabilized by the DC / DC converter CNV, but the power supply voltage of + 5V is external power supply terminal VE.
It is not stabilized because it is supplied directly from X. In other words, the + 5V power supply voltage varies among products.

As shown in FIG. 1, the common electrode drive circuit is M
OS transistors TR1-TR4, fixed resistors R1-R1
0, smoothing capacitors C1 and C2, variable resistors VR1 and VR2, operational amplifiers OP1 to OP4, and a multiplexer MPX. MOS transistors TR1 and TR3 are of P channel type, and MOS transistors TR2 and TR4 are of N channel type.
The operational amplifiers OP1 to OP4 operate in the power supply voltages of + 5V and -3V, and are of a rail-to-rail type that can obtain outputs substantially equal to these voltage levels. The multiplexer MPX is, for example, an HC4053 type that operates with a power supply voltage of + 5V.

The current path of the P-channel MOS transistor TR1 is connected between the power supply terminal + VDD and one end of the resistor R9, and the current path of the P-channel MOS transistor TR3 is connected between the other end of the resistor R9 and the common voltage output terminal VCOM. . The current path of the N-channel MOS transistor TR4 is the common voltage output terminal VCOM.
And an N-channel MO
The current path of the S transistor TR2 is connected between the other end of the resistor R10 and the power supply terminal-VEE. The MOS transistors TR3 and TR4 are rendered conductive in a complementary relationship according to the gate voltage controlled by the multiplexer MPX, and the power supply terminal + VDD to the MOS transistor TR1.
And a positive voltage (VCOM
H) and power supply terminal -VEE to MOS transistor T
Negative voltage (VC) applied via R2 and resistor R10
A CMOS inverter that outputs one of OML) to the common voltage output terminal VCOM is configured. Smoothing capacitor C1
Is connected between the connection point of the MOS transistor TR1 and the resistor R9 and the ground terminal (0V) in order to smooth the positive voltage applied to the CMOS inverter. The smoothing capacitor C2 is connected between the connection point of the MOS transistor TR4 and the resistor R10 and the ground terminal in order to smooth the negative voltage applied to the CMOS inverter.

The multiplexer MPX is -3V obtained from the power supply terminal -VEE when the polarity inversion signal POL from the liquid crystal controller 16 shown in FIG. 2 rises to + 5V.
+5 obtained from the power supply terminal + VDD when the polarity inversion signal POL rises to 0V.
The power supply voltage of V is selected, and the voltage thus selected is supplied to the MOS transistors TR3 and TR4 as the gate voltage. Further, the multiplexer MPX is obtained from the power supply terminal -VEE when the shutdown signal SHUT from the liquid crystal controller 16 rises to + 5V-3.
The power supply voltage of V is selected, the output voltage of the operational amplifier OP1 is selected when the shutdown signal SHUT falls to 0V, and the voltage thus selected is supplied to the MOS transistor TR1 as the gate voltage, and further, the MOS transistors TR3 and TR4. Also supply.

Each of the operational amplifiers OP1 to OP4 generates an output voltage from the output terminal according to the potential difference between the non-inverting input terminal and the inverting input terminal. The output terminal of the operational amplifier OP1 is connected to the multiplexer MPX, and the operational amplifier OP1
The output terminal of is connected to the gate of the MOS transistor TR2. The non-inverting input terminal of the operational amplifier OP1 has a resistor R9.
And a MOS transistor TR3 are connected via a resistor R6, and a non-inverting input terminal of the operational amplifier OP2 is connected to a connection point between a resistor R10 and a MOS transistor TR4 via a resistor R8. Resistor R3 is power supply terminal + VDD
And the variable resistor VR2 is connected between one end of the variable resistor VR2, the resistor R4 is connected between the other end of the variable resistor VR2 and the ground terminal, and the intermediate tap of the variable resistor VR2 is connected to the inverting input terminal of the operational amplifier OP1 and the inverting input terminal of the operational amplifier OP2. To be done. The output terminal of the operational amplifier OP3 is connected to the non-inverting input terminal of the operational amplifier OP1 and the inverting input terminal of the operational amplifier OP3 via the resistor R5. The output terminal of the operational amplifier OP4 is connected to the non-inverting input terminal of the operational amplifier OP2 and the inverting input terminal of the operational amplifier OP4 via the resistor R7. The resistor R1 is connected between the power supply terminal −VEE and the non-inverting input terminal of the operational amplifier OP3, the variable resistor VR1 is connected between the non-inverting input terminal of the operational amplifier OP3 and the non-inverting input terminal of the operational amplifier OP4, and the resistor R2 is connected with the operational amplifier OP4. It is connected between the non-inverting input terminal and the power supply terminal + VON. The center tap of the variable resistor VR1 is connected to one end of the variable resistor VR1.

That is, the resistor R3, the variable resistor VR2, and the resistor R4 form a voltage dividing circuit for dividing the voltage between the power supply terminal + VDD and the ground terminal by the resistance ratio, and the common center voltage VCOMC, that is, the high level of the common voltage VCOM. Used to set the average of VCOMH and low level VCOML. On the other hand, the resistor R1, the variable resistor VR1, and the resistor R2 are connected to the power supply terminals -VEE and + V.
The voltage divider circuit divides the voltage between ONs by a resistance ratio, and is used to set the amplitude VCOM (pp) of the common voltage VCOM, that is, the difference between the high level VCOMH and the low level VCOML.

Here, actual VCOMH, VCOML, V
The values of COMC and VCOM (pp) will be described. In the liquid crystal panel 10 of this embodiment, the signal voltage is generated from the voltage of the power supply terminal + VDD, and changes in the range of 0V to + 5V according to the gradation data. As shown in FIG. 4, for example, when the scanning line Y1 rises from -12V to + 19V by the scanning pulse from the Y driver 14, the corresponding T
The FT 24 becomes conductive, and the X driver 12 causes the first signal line Y1 to pass.
The signal voltage supplied to the corresponding pixel electrode 20 is applied to the corresponding pixel electrode 20.
At this time, if the signal voltage is + 5V, the pixel potential of the pixel electrode 20 changes to + 5V. However, the TFT 24
Since the gate and the source, and the pixel electrode and the scanning line have a parasitic capacitance CGS formed between them,
When the TFT 24 becomes non-conducting, the charge on the pixel electrode 20 moves to charge the capacitor CGS, which lowers the potential of the pixel electrode 20 by a predetermined level VP (about 1.3V) to + 3.7V. I will leave. When the level conversion of the signal voltage is performed for the frame inversion drive and the line inversion drive, the pixel potential of the pixel electrode 20 is 0V.
Becomes In this case, after the TFT 24 becomes non-conductive, the parasitic capacitance CGS further lowers it by a predetermined level VP (about 1.3V) to −1.3V. Pixel electrode 2
To obtain the required 5V potential difference between 0 and the common electrode 22, VCOMH is set to VP + 3.7V,
VCOML is set to -1.3V. In this case, VC
OM (p-p) is set to + 5V and VCOMC is +
It is set to 1.2V.

For example, the resistance values of the resistors R5, R6, R7 and R8 are selected so as to satisfy the following relationships.

R5: R6 = R7: R8 (1) The high level VCOMH and the low level VCOML of the common voltage VCOM are equal to the source voltage of the MOS transistor TR1 and the source voltage of the MOS transistor TR4, respectively. These VCOMH, VCOML, VCOM
C and VCOM (p-p) are expressed as follows using the inverting input voltage V0 of the operational amplifiers OP1 and OP2, the output voltage V1 of the operational amplifier OP3, and the output voltage V2 of the operational amplifier OP4.

VCOMH = V0 + (V0-V1) R6 / R5 = V0 (R5 + R6) /R5-V1.R6/R5 (2) VCOML = V0 + (V0-V2) R8 / R7 = V0 (R7 + R8) / R7- V2 * R8 / R7 ... (3) VCOMC = (VCOMH + VCOML) / 2 = V0 (R5 + R6) / R5- (V1 + V2) R6 / 2 * R5 ... (4) VCOM (p-p) = VCOMH-VCOML = (V2- V1) R6 / R5 (5) By the way, the voltage V0 changes due to the voltage fluctuation of the power supply terminal + VDD, and the common center voltage VCO has the relationship shown in FIG.
Set MC. That is, since the voltage between the power supply terminal + VDD and the ground terminal is divided by the voltage dividing circuit of the resistor R3, the variable resistor VR2, and the resistor R4, the fluctuation rate of the voltage V0 is the voltage dividing ratio (resistance ratio) of this voltage dividing circuit. Depends on.
Therefore, the voltage V0 is determined in advance so that the common center voltage VCOMC shifts to an optimum value determined by the type of the liquid crystal panel 10 when the voltage of the power supply terminal + VDD changes. The voltages V1 and V2 are determined from VCOM (p-p) and VCOMC unique to the liquid crystal panel 10, a voltage V0 having the common center voltage VCOMC as an optimum value when the power supply voltage changes, and the formulas (4) and (5). To be done. The resistors R1 and R2 are connected to the voltage V1 thus determined.
And V2 are obtained.

As an actual resistance value, the resistance R1 = 8.2.
kΩ, R2 = 68 kΩ, R3 = 47 kΩ, R4 = 6.8
kΩ, R5 = 4.7 kΩ, R6 = 4.7 kΩ, VR1 =
22 kΩ and VR2 = 47 kΩ are selected.

The operation of this common electrode drive circuit will be described.

The operational amplifiers OP3 and OP4 respectively reduce the impedance of the output voltage corresponding to the voltage divided by the voltage dividing circuit in which the common voltage amplitude VCOM (p-p) is set by the variable resistor VR1 and output it. Operational amplifier O
The non-inverting input terminal of P1 is set to a potential according to the output voltage of the operational amplifier OP3 supplied via the resistor R5 and the source voltage of the MOS transistor TR3 supplied via the resistor R6, and the inverting input terminal of the operational amplifier OP1 is The potential is set according to the voltage divided by the voltage dividing circuit in which the common center voltage VCOMC is set by the variable resistor VR2. The operational amplifier OP1 generates an output voltage according to the potential difference and supplies it to the multiplexer MPX. The shutdown signal SHUT of the multiplexer MPX is 0.
When maintained at V, the output voltage of the operational amplifier OP1 is supplied to the MOS transistor TR1 as a gate voltage. As a result, the voltage drop in the MOS transistor TR1 is controlled, and the source voltage of the MOS transistor TR3 is stabilized at the above-mentioned VCOMH. On the other hand, operational amplifier O
The non-inverting input terminal of P2 is set to a potential according to the output voltage of the operational amplifier OP4 supplied via the resistor R7 and the source voltage of the MOS transistor TR4 supplied via the resistor R8, and the non-inverting input terminal of the operational amplifier OP2 The potential is set to a potential corresponding to the voltage from the voltage dividing circuit in which the variable resistor VR2 is adjusted so that the above-mentioned common center voltage VCOMC is obtained. The operational amplifier OP2 generates an output voltage according to these potential differences and supplies this output voltage to the MOS transistor TR2 as a gate voltage. As a result, the voltage drop in the MOS transistor TR1 is controlled and the source voltage of the MOS transistor TR3 is set to the above-mentioned V
Stabilize to COML.

The multiplexer MPX has a polarity inversion signal PO.
Every time L changes with the level inversion of the pixel potential of the pixel electrode 20, the gate voltage of the MOS transistor TR3 is changed from one of -3V and + 5V to the other. The MOS transistor TR3 becomes conductive when the gate voltage is set to -3V and becomes non-conductive when the gate voltage is set to + 5V. Also, the MOS transistor T
R4 conducts when the gate voltage is set to + 5V,
It becomes non-conductive when the gate voltage is set to -3V.
That is, the stable VCOMH of + 3.7V and the stable VCOML of −1.3V are alternately alternated via the MOS transistors TR3 and TR4 to the common voltage terminal VC.
Applied to the OM. As a result, the direction of the electric field in the liquid crystal cell is reversed without changing the potential difference between the pixel electrode 20 and the common electrode 22.

If the power supply voltage of the power supply terminal + VDD changes, the potentials of the non-inverting input terminals of the operational amplifiers OP1 and OP2 change with this voltage change, the common center voltage VCOMC shifts to the optimum value, and VCOMH and VCOML. Shift corresponding to the shift of the common center voltage VCOMC.

When the shutdown signal SHUT changes to + 5V with the stop of the shift clock CK, the multiplexer MPX supplies the gate voltage of -3V to the MOS transistors TR1, TR3 and TR4. Therefore, the common voltage VCOM is equal to the MOS transistor TR.
Set to + 5V via 1 and TR3.

In the common electrode drive circuit of the above embodiment,
A CMOS transistor T in which a CMOS inverter is connected in series between a power supply terminal + VDD and a power supply terminal -VEE
R3 and TR4 and operational amplifiers OP1 and MO
The feedback loop of the S-transistor TR1 adjusts the positive voltage applied from the power supply terminal + VDD to the CMOS inverter and the negative voltage applied from the negative power supply terminal -VEE to the CMOS inverter to the desired levels VCOMH and VCOML, respectively, as a variable voltage drop means. . In this case, since the voltage drop in the CMOS inverter hardly occurs, the DC / DC converter CNV of the liquid crystal display device
+ 5V close to VCOMH and VCOML obtained from
And -3V can be used, which can reduce the power loss of the common electrode drive circuit. Furthermore, since the power supply voltages of the power supply terminals + VDD and -VEE are adjusted by the variable voltage drop means, it is not necessary to supply the power supply terminals + VDD in a stabilized state. Therefore, the external power supply voltage supplied to the liquid crystal display device or various power supply voltages generated from the external power supply voltage in the liquid crystal display device can be used as the power supply voltage of the common electrode drive circuit. In other words, it is possible to eliminate the need to generate a power supply voltage in the liquid crystal display device that is used only for the common electrode drive circuit.

In this embodiment, the common voltage amplitude VCOM is adjusted by adjusting VR1 so that the difference between VCOMH and VCOML in the liquid crystal panel 10 becomes appropriate.
If the common center voltage VCOMC is set by setting (pp) and adjusting the VR2 so that the flicker is eliminated in the liquid crystal panel 10, even if the voltage of the power supply terminal + VDD fluctuates thereafter, the common center voltage is changed. V
COMC is shifted according to this voltage fluctuation. Therefore, it is possible to prevent flicker from occurring due to the voltage fluctuation of the power supply terminal + VDD.

Further, in this embodiment, when the shift clock CK is stopped in the liquid crystal display device, the common voltage VCOM is set equal to the signal voltage + 5V at this time, so that the liquid crystal is prevented from being applied with an unnecessary DC voltage. The cell can be protected.

Next, a common electrode drive circuit according to the second embodiment of the present invention will be described with reference to FIG. This common electrode drive circuit is similar to the first embodiment in that the liquid crystal panel 1 shown in FIG.
It is incorporated in the above-mentioned liquid crystal display device in order to drive the 0 common electrode 22. This embodiment is applied when it is permitted to generate the power supply voltage dedicated to the common electrode drive circuit in the DC / DC converter CNV of the liquid crystal display device. The common electrode drive circuit has the same configuration as that of the first embodiment except as described below. The same parts as those of the first embodiment are designated by the same reference numerals in FIG. 5, and the description thereof will be omitted.

In the liquid crystal display device, +5 as shown in FIG.
The power supply voltage of V is from a computer or the like to the external power supply terminal VEX
DC / DC converter CNV and power supply terminal via
Supplied to VDD. The DC / DC converter CNV stabilizes the + 5V power supply voltage from the external power supply terminal VEX at +1.
Converted to power supply voltages of 9V, -12V, -1.3V and -3V, and power supply terminals + VON, -VOFF, -V, respectively.
Supply to BB and -VEE. The common electrode drive circuit is supplied to the power supply terminals -VBB, -VEE, + VDD-
It operates with power supply voltages of 1.3V, -3V and + 5V.
Here, the power supply voltage of -3V is the DC / DC converter CN.
Although stabilized by V, the power supply voltage of + 5V is not stabilized because it is directly supplied from the external power supply terminal VEX. The DC / DC converter CNV is VCOML.
The power supply voltage of −1.3 V, which is equal to, changes according to the fluctuation of the power supply voltage supplied from the external power supply terminal VEX, and the rate of this change can be changed by the adjustment signal ADJ. The rate of change of the power supply voltage at the power supply terminal −VBB is appropriately adjusted according to the central level of the signal voltage in order to prevent the flicker phenomenon from occurring.

The common electrode drive circuit shown in FIG. 5 includes MOS transistors TR1, TR3 and TR4, and a fixed resistor R.
3, R6, R9, smoothing capacitor C1, variable resistor VR,
It has an operational amplifier OP1, a multiplexer MPX, and a Zener diode ZD. MOS transistor TR
1 and TR3 are of P-channel type, and MOS transistor TR4 is of N-channel type. The operational amplifier OP1 operates on the power supply voltages of +5 V and -1.3 V, and is of a rail-to-rail type capable of obtaining an output substantially equal to these voltage levels. The multiplexer MPX is, for example, the HC 405 that operates with a power supply voltage of + 5V.
It is composed of 3 types.

In this common electrode drive circuit, the resistor R3 is connected between the power supply terminal + VDD and the inverting input terminal of the operational amplifier OP1, and the zener diode ZD is used to set the common voltage amplitude reference and the inverting input terminal of the operational amplifier OP1. Reverse connection is made between the terminal and VBB.
The non-inverting input terminal of the operational amplifier OP1 has a resistor R9 and a MOS.
It is connected to a connection point with the transistor TR3 via a resistor R6, and further connected to a power supply terminal −VBB via a variable resistor VR for adjusting the common voltage amplitude. The center tap of the variable resistor VR is connected to one end of the variable resistor VR.
The current path of the MOS transistor TR4 is connected between the common electrode output terminal VCOM and the power supply terminal-VBB. The inverting input terminal of the operational amplifier OP1 is the power supply terminal -VB
Zener voltage VD1 of Zener diode ZD rather than B
Therefore, the non-inverting input terminal of the operational amplifier OP1 is set to the potential divided by the resistor R6 and the variable resistor VR.

The source voltage of the MOS transistor TR3 is used as the high level VCOMH of the common voltage VCOM and is expressed as follows.

VCOMH = VCOML + (1 + R6 / VR1) VD1 (6) That is, the difference between VCOMH and VCOML is set by adjusting the variable resistor VR1.

In operation, the operational amplifier OP1 generates an output voltage such that the potential of the non-inverting input terminal becomes equal to the potential of the inverting input terminal and supplies it to the multiplexer MPX. The multiplexer MPX has a shutdown signal SHU.
When T is maintained at 0V, the output voltage of the operational amplifier OP1 is supplied to the MOS transistor TR1 as a gate voltage. As a result, the voltage drop in the MOS transistor TR1 is controlled, and the source voltage of the MOS transistor TR3 is stabilized at the above-mentioned VCOMH.

The multiplexer MPX has a polarity inversion signal PO.
Every time L changes with the level inversion of the pixel potential of the pixel electrode 20, the gate voltage of the MOS transistor TR3 is changed from one of -3V and + 5V to the other. The MOS transistor TR3 becomes conductive when the gate voltage is set to -3V and becomes non-conductive when the gate voltage is set to + 5V. Also, the MOS transistor T
R4 conducts when the gate voltage is set to + 5V,
It becomes non-conductive when the gate voltage is set to -3V.
That is, the stable VCOMH of + 3.7V and the stable VCOML of −1.3V are alternately alternated via the MOS transistors TR3 and TR4 to the common voltage terminal VC.
Applied to the OM. As a result, the direction of the electric field in the liquid crystal cell is reversed without changing the potential difference between the pixel electrode 20 and the common electrode 22.

If the power supply voltage of the power supply terminal + VDD changes, the potential of the power supply terminal -VBB changes with this voltage change, the common center voltage VCOMC shifts to the optimum value, and VCOMH and VCOML change the common center voltage. Shift corresponding to VCOMC shift.

When the shutdown signal SHUT changes to + 5V with the stop of the shift clock CK, the multiplexer MPX supplies the gate voltage of -3V to the MOS transistors TR1, TR3 and TR4. Therefore, the common voltage VCOM is equal to the MOS transistor TR.
1 and 2 above set to + 5V via TR3
According to the embodiment, the common electrode drive circuit can be constructed with a small number of parts, and the same effect as that of the first embodiment can be obtained.

The present invention is not limited to the above embodiment,
Various modifications can be made without departing from the spirit of the invention.

[0049]

According to the present invention, power loss can be reduced without limiting the power supply voltage level.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a common electrode drive circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram schematically showing a configuration of a liquid crystal display device in which the common electrode drive circuit shown in FIG. 1 is incorporated.

FIG. 3 is a graph showing a common center voltage depending on a power supply voltage + VDD in the common electrode drive circuit shown in FIG.

FIG. 4 is a time chart for explaining the operation of the common electrode drive circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a common electrode drive circuit according to a second embodiment of the present invention.

[Explanation of symbols]

OP1-OP4 ... Operational amplifier, TR1-TR4 ... MOS
Transistor, MPX ... Multiplexer, R1-R10
... Fixed resistors, VR1, VR2 ... Variable resistors.

Claims (10)

[Claims] 1. A CMOS transistor connected in series between a first power supply terminal and a second power supply terminal, wherein C
An inverter section that alternately turns on the MOS transistors in a predetermined cycle and outputs a voltage at a connection point of these CMOS transistors as a voltage for driving a display device; a first voltage applied from the first power supply terminal to the inverter section; A drive circuit for a display device, comprising: a variable voltage drop unit that adjusts at least one of the second voltage applied from the second power supply terminal to the inverter unit to a desired level. 2. The variable voltage drop means is a P channel M inserted between the first power supply terminal and the inverter section.
The drive for a display device according to claim 1, further comprising an OS transistor and a rail-to-rail operational amplifier that controls a gate voltage of the P-channel MOS transistor according to a first voltage applied to the inverter unit. circuit. 3. The variable voltage drop means further includes an N-channel MOS transistor inserted between the negative power supply terminal and the inverter section, and a gate voltage of the N-channel MOS transistor according to a negative voltage applied to the inverter section. The drive drive circuit for a display device according to claim 2, further comprising an operational amplifier for controlling the. 4. When a power supply voltage of the first power supply terminal used for driving a common electrode of the display device and used to obtain a signal voltage applied to a pixel electrode facing the common electrode is changed, The drive circuit for a display device according to claim 1, further comprising a voltage correction unit that shifts a center level and an amplitude of the drive voltage in response to fluctuations. 5. The common voltage is applied to the pixel electrode for driving a common electrode of the display device and canceling an electric field between the common electrode and a pixel electrode facing the common electrode when a clock is stopped. The display device drive circuit according to claim 1, further comprising liquid crystal protection means for fixing the voltage to a voltage equal to the signal voltage. 6. A first electrode substrate having a first electrode disposed on a first insulating substrate, a second electrode substrate having a second electrode electrode disposed on a second insulating substrate, and the first and second electrodes. A light modulation layer held between electrode substrates and a first electrode for driving the first electrode
In a display device including an electrode drive circuit and a second electrode drive circuit that drives the second electrode, the second electrode drive circuit is connected in series between a first power supply terminal and a second power supply terminal. An inverter unit configured to alternately turn on the CMOS transistor in a predetermined cycle to output the voltage at the connection point of the CMOS transistor to the second electrode;
A first voltage is supplied to the power supply terminal and a second voltage is supplied to the second power supply terminal. The voltage supply section divides the power supply voltage supplied from the outside by resistance to divide the first voltage. And a display device characterized by comprising resistance dividing means for forming the second voltage. 7. The first electrodes of the first electrode substrate are connected to signal lines and scanning lines through switch elements and arranged in a matrix, and the second electrodes of the second electrode substrate are formed.
The display device according to claim 6, wherein the electrode is a common electrode facing the first electrode. 8. An X driver for driving the signal line and a Y driver for driving the scanning line, wherein the X driver outputs a signal voltage based on the power supply voltage supplied from the outside. The display device according to claim 7. 9. The resistance dividing means is configured so that the first voltage and the second voltage follow a change in a potential change amount caused by a parasitic capacitance of the first electrode due to a change in the power supply voltage. The display device according to claim 8, wherein the first voltage and the second voltage are set. 10. The second electrode of the second electrode substrate is arranged so as to form an auxiliary capacitance with a pixel electrode connected to a signal line and a scanning line through a switch element, and the second electrode of the first electrode substrate is formed. The display device according to claim 6, wherein the first electrode is a common electrode facing the pixel electrode.