JPH0955724A - Clock phase shifting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a data error from being generated when a write and a read clock signal are in phase with each other and an ES is accessed at the same time at the time of a loop-back test. SOLUTION: To obtain the clock phase shifting circuit 1 which is used for a test using a loop-back circuit of a digital transmission network, a phase detection part 2 which detects the phases of the write and read clock signals when the write and read clock signals are asynchronous, phase judgement parts 3 and 4 which judge whether or not the write and read clock signals detected by the phase detection part 2 are in phase with each other, and phase shift parts 5 and 6 which shift the phase of one of the write and read clock signals when the phase judgement parts 3 and 4 judge that the write and read clock signals are in phase with each other are provided.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the field of testing with loopback circuits in digital transmission networks.

[0002]

2. Description of the Related Art In a maintenance test of a digital transmission device, a line test or the like is performed only when it is difficult to identify a failure point. In a normal maintenance test, a loopback test using a loopback circuit is performed. It is common. That is,
At the time of maintenance, the loopback circuit is almost always used. FIG. 4 is a schematic diagram showing an example of the loopback circuit. In FIG. 4, the DPPL circuit is a digital PLL (Phase Locked Loop) circuit and extracts a clock signal from input data. In FIG. 4, ISDN is used as a digital transmission line.
When (INS64) is used, there are B1 and B2 channels in the information channel of INS64, normal communication is performed with the terminal device in the B1 channel, and the individual channel loopback circuit 1 is used in the B2 channel from the subscriber side. The data of is returned to the subscriber side and output again.

In order to test only the distinguishing channel without interrupting the current service by using the loopback circuit, an ES (Elastotech Store) is provided in the loopback circuit, and the signal path of the individual channel is provided by this ES. This is possible by preventing the timing deviation due to the difference in That is, in the B1 channel, there is a time (for example, a round trip of 4 μs with a length of 150 m) that reciprocates the wiring cable to the terminal device, and this time is adjusted by ES in the B2 channel. In this case, the RAM used for the ES is of a type that cannot write and read at the same time. this is,
Dual port RA for simultaneous writing and reading
The minimum configuration of M is 4 bits or more, and the RAM of the primitive cell is used in order to reduce the cost by reducing the number of gates.
This is because you are using. The FIFO (First In First Out) used for the ES has a total 8-bit length of 6 bits in which a 2-bit offset according to the device standard and a transmission path delay time are taken into consideration, and a serial signal is handled. A RAM of 8 words x 1 bit is required.

[0004]

However, in such a conventional loopback circuit having an ES,
Single port RA that cannot be written and read at the same time due to manufacturing cost during mass production
Since M was used, there were problems as described below. That is, the write clock signal for ES uses the clock signal extracted from the subscriber side, and
As the read clock signal for the ES, a clock signal extracted from the terminal device side is generally used. However, when the frequency of the subscriber side clock signal and the frequency of the terminal device side clock signal are the same, the loopback circuit 1 When reading / writing the same address from / to the ES, the ES causes a data error. This is because when the frequencies of the subscriber-side clock signal and the terminal equipment-side clock signal are the same, the two clocks have the same phase in consideration of the delay in the transmission path, and the RAM in the ES has the same phase.
This is because reading and writing are performed at once.

An object of the present invention is to solve the above-mentioned problems, and in a loopback test, a data error in an ES when a write clock signal and a read clock signal simultaneously access the RAM in the ES in the same phase. To prevent.

[0006]

A clock phase change circuit according to claim 1 is a clock phase change circuit used for a test using a loopback circuit in a digital transmission network, and is based on data output from a subscriber side. When the extracted write clock signal and the read clock signal extracted from the data output from the terminal device side are asynchronous, a phase detection unit that detects the phases of the write clock signal and the read clock signal, respectively, and the phase detection unit. The phase determining unit that determines whether the respective phases of the write clock signal and the read clock signal detected by the above are the same phase, and the phase determining unit determines that the write clock signal and the read clock signal have the same phase. , One of the write clock signal and the read clock signal It is configured with the phase change section for changing the phase of the clock signal.

According to another aspect of the clock phase change circuit of the present invention,
A clock phase change circuit used for a test using a loopback circuit in a digital transmission network, which is a write clock signal extracted from data output from a subscriber side and a read extracted from data output from a terminal device side. If the clock signals are asynchronous, does the phase detection unit that detects the rising or falling edges of the clocks of the write clock signal and the read clock signal match the rising or falling edge of each clock signal detected by the phase detection unit? When the phase determining unit that determines whether or not the rising edge or the falling edge of each clock signal is determined by the phase determining unit, the phase of either one of the write clock signal and the read clock signal is changed. And the phase change part It is configured to obtain.

In this case, in addition to the clock phase change circuit according to claim 1 or 2, in the clock phase change circuit according to claim 3, the phase change portion has a delay circuit, and the write clock signal. When changing the phase of either one of the read clock signal and the read clock signal, the clock signal whose phase is to be changed is output through the delay circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a clock phase change circuit of the present invention. In FIG. 1, the same elements as those of the conventional example shown in FIG. 4 are designated by the same reference numerals. Clock phase change circuit 1 of the present invention
As shown in FIG. 1, a clock falling edge detection circuit 2 serving as a phase detecting unit, an inverter 3 and a D-flip-flop 4 serving as a phase determining unit, a delay circuit (delay circuit) 5 serving as a phase changing unit, and And a switch 6.

The clock falling detection circuit 2 detects the falling edge portion ("H" → "L") of the read clock signal (hereinafter referred to as the terminal device side clock signal) extracted from the output data from the terminal device side. By doing so, the phase of the read clock is detected, and its output is normally "H", and when an edge portion is detected, "L" is output only for a predetermined time based on the reference clock timing. . The clock signal on the terminal equipment side is 19
Since the specification of 2 kHz ± 100 ppm is satisfied, the fall detection signal can be output by calculating from the rise point. Specifically, since the system clock signal in this case uses 15.36 MHz, the time from the rising point to the falling point of the terminal device side clock signal can be known by counting this clock pulse 40 times.

The inverter 3 receives the output from the clock rise detection circuit 2 and inputs its inverted signal to the data input terminal D of the D-flip-flop 4. The D-flip-flop 4 is on the subscriber side. Falling edge portion of the write clock signal (hereinafter referred to as a subscriber side clock signal) extracted from the output data from the
The output from the inverter 3 is taken in at the input timing of "L") and output from the output terminal Q. This makes it possible to judge whether the clock signal on the subscriber side and the clock signal on the terminal device side are in phase, and when they are in phase, "H" is output from the output terminal Q. To be done.

The delay circuit 5 is for generating a clock signal by delaying the subscriber-side clock signal for a predetermined time, and its output end is connected to one input end of the switch 6. The switch 6 is for switching whether to output the subscriber-side clock signal as it is or to output it via the delay circuit 5. That is, based on the output signal from the D-flip-flop 4, when the output of the D-flip-flop 4 is "L", the switch 6 outputs the subscriber-side clock signal as it is, while the switch of the D-flip-flop 4 outputs. When the output is "H", the switch 6 outputs the subscriber-side clock signal delayed from the delay circuit 5 for a predetermined time. As a result, when the phase of the subscriber-side clock signal output through the switch 6 matches the terminal-device-side clock signal, the subscriber-side clock signal output from the delay circuit 5 is switched by the switching operation of the switch 6. The phase of the subscriber-side clock signal is changed by using a new subscriber-side clock signal (hereinafter, new subscriber-side clock signal).

Next, the operation of the above embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the signal waveform of each node in FIG. First, when the falling point of the subscriber side clock signal and the falling point of the terminal device side clock signal are different, input to the input terminal D of the D-flip-flop 4 at the falling point of the subscriber side clock signal. Is "L", the output from the output terminal Q is "L". That is, when the phases of the two clock signals are different, the output from the D-flip-flop 4 becomes "L", the switch 6 is switched to the through path, and the subscriber-side clock signal remains the new-subscriber-side clock. It is output as a signal.

On the other hand, when the trailing edge of the subscriber side clock signal and the trailing edge of the terminal equipment side clock signal have the same timing, the D-flip-flop 4 at the trailing edge of the subscriber side clock signal. Since the input to the input terminal D becomes "H", the output from the output terminal Q becomes "H". That is, when the two clock signals have the same phase, the output from the D-flip-flop 4 becomes "H" and the switch 6 receives the subscriber-side clock signal delayed by the delay circuit 5 for a predetermined time. It is output as a clock signal on the new subscriber side. As a result, the new subscriber side clock signal becomes a clock signal having a phase different from that of the terminal device side clock signal.

As described above, according to the present invention, when the two clock signals of the subscriber side clock signal and the terminal equipment side clock signal have the same phase, either one of them (in this case, the subscriber side). By shifting the phase of the clock signal of 1, the malfunction (data error) caused by the addition of the clock signal of the same phase to the ES of the loopback circuit can be prevented. Although the phase is changed by delaying the subscriber side clock signal by the delay circuit 5 in the above-described embodiment, the clock signal to be changed may be the terminal device side clock signal, or the delay circuit. The phase may be changed by a method different from the method described in No. 5.

FIG. 3 is a diagram showing an example of another phase changing unit different from that in FIG. In FIG. 3, the phase change unit in the present embodiment is a four-stage D-flip-flop 7a, 7b, 7
It is composed of c, 7d and an inverter 8. In the above configuration, the first-stage and third-stage D-flip-flops 7
A system clock signal of 15.36 MHz is applied to a and 7c, and a system clock signal inverted by the inverter 8 is applied to the second-stage and fourth-stage D-flip-flops 7b and 7d. . As a result, the signal input to the first-stage D-flip-flop 7a is delayed by the time of (2 / 15.36) MHz and becomes 4
It is output from the D-flip-flop 7d at the stage. Therefore, like the delay circuit 5 in the embodiment of FIG. 1, the phase can be changed by delaying the input clock signal by a predetermined time.

According to the present invention, in the loopback test, data generated by simultaneous access of the write clock signal from the subscriber side and the read clock signal from the terminal device side to the ES in the loopback circuit. You can prevent errors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a clock phase change circuit of the present invention.

FIG. 2 is a timing chart showing signal waveforms of each node in FIG.

FIG. 3 is a diagram showing an example of another phase changing unit different from FIG.

FIG. 4 is a schematic diagram showing an example of a loopback circuit.

[Explanation of symbols]

 1 Clock Phase Change Circuit 2 Clock Fall Detection Circuit (Phase Detection Section) 3 Inverter (Phase Judgment Section) 4 D-Flip Flop (Phase Judgment Section) 5 Delay Circuit (Phase Change Section) 6 Switch (Phase Change Section) 7 D -Flip-flop (phase change part) 8 Inverter (phase change part)

Claims (3)

[Claims] 1. A clock phase change circuit used for a test using a loopback circuit in a digital transmission network, wherein a write clock signal extracted from data output from a subscriber side and data output from a terminal device side. When the read clock signals extracted from the above are asynchronous, the phase detection unit that detects the phases of the write clock signal and the read clock signal respectively have the same phase as the write clock signal and the read clock signal detected by the phase detection unit. If the write clock signal and the read clock signal are in the same phase by the phase determining unit that determines whether they are in phase, the clock of either the write clock signal or the read clock signal A phase change part that changes the phase of the signal is provided. Clock phase change circuit characterized by 2. A clock phase change circuit used for a test using a loopback circuit in a digital transmission network, wherein a write clock signal extracted from data output from a subscriber side and data output from a terminal device side. When the read clock signal extracted from the clock signal is asynchronous, a phase detection unit that detects the clock rising or falling edge of the write clock signal and the read clock signal, and the rising or falling of each clock signal detected by the phase detection unit A phase determination unit that determines whether the edges match, and if the phase determination unit determines that the rising or falling edges of each clock signal match, one of the write clock signal and the read clock signal clock The position to change the phase of the signal Clock phase changing circuit, characterized in that it comprises a change unit. 3. The phase changing section has a delay circuit, and when changing the phase of one of the write clock signal and the read clock signal, the delay circuit outputs the clock signal whose phase should be changed. The clock phase change circuit according to claim 1 or 2, wherein the clock phase change circuit outputs the clock phase change circuit.