JPH0955597A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0955597A JPH0955597A JP7230730A JP23073095A JPH0955597A JP H0955597 A JPH0955597 A JP H0955597A JP 7230730 A JP7230730 A JP 7230730A JP 23073095 A JP23073095 A JP 23073095A JP H0955597 A JPH0955597 A JP H0955597A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- sealing resin
- wiring board
- shield
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000011347 resin Substances 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims abstract description 9
- 230000001070 adhesive effect Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 33
- 239000011241 protective layer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置に係わ
り、特に、薄型でリードレスタイプの表面実装用混成集
積回路装置のシールド構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a shield structure for a thin and leadless type surface mount hybrid integrated circuit device.
【0002】[0002]
【従来の技術】従来のリードレスタイプの表面実装用の
ICパッケージに於けるシールド構造を図2に示す。図
2に於いて、配線基板(10)の凹部(13)の底面に
ICチップ(14)を搭載して封止樹脂(16)で封止
する。しかる後、封止樹脂(16)の表面と該封止樹脂
(16)の表面と同一平面をなす配線基板(10)の表
面の安定電位、代表的には接地電位(以下GNDと称
す)の導体パターンの一部にかかる部分にまたがって、
Cu等の高電導率導体ペーストを印刷し、シールド層
(17)を形成していた。2. Description of the Related Art FIG. 2 shows a conventional shield structure of a leadless type surface mounting IC package. In FIG. 2, the IC chip (14) is mounted on the bottom surface of the recess (13) of the wiring board (10) and sealed with the sealing resin (16). Then, a stable potential of the surface of the sealing resin (16) and the surface of the wiring substrate (10) that is flush with the surface of the sealing resin (16), typically a ground potential (hereinafter referred to as GND), is applied. Straddling a part of the conductor pattern,
A shield layer (17) was formed by printing a high-conductivity conductor paste such as Cu.
【0003】この場合、封止樹脂(16)の主成分はエ
ポキシ系であるが、基板の反り対策等の為にシリコン系
の成分を含む場合が多い。また、ほとんどの場合、前記
シールド層(17)の酸化防止の為に、その上部にレジ
ストが印刷され、保護層(21)が形成される。In this case, the main component of the sealing resin (16) is an epoxy type, but in many cases, a silicon type component is included as a measure against the warpage of the substrate. In most cases, a resist is printed on the shield layer (17) to prevent the oxidation of the shield layer (17) to form a protective layer (21).
【0004】[0004]
【発明が解決しようとする課題】以上の従来の図2に示
すシールド構造では、封止樹脂がシリコン系成分を含む
場合には、前記高電導率導体ペーストによるシールド層
との密着性が充分ではなく、例えば、クロスカット試験
(JIS規格:K5400)による結果では、安定した
結果が得られず、特に該シールド層及び上部保護層の膜
厚が厚い程試験結果が悪く、引きはがし後の残りパター
ン数が50%程度、最悪0%となることもあった。In the conventional shield structure shown in FIG. 2 described above, when the sealing resin contains a silicon-based component, the adhesion of the high-conductivity conductor paste to the shield layer is not sufficient. However, for example, according to the result of the cross-cut test (JIS standard: K5400), stable results cannot be obtained. Particularly, the thicker the film thickness of the shield layer and the upper protective layer is, the worse the test result is, and the remaining pattern after peeling. The number was around 50%, and sometimes it was 0%.
【0005】しかしながら、上記密着性の改善の為に、
封止樹脂からシリコン系の成分と取り去ると、今度は、
基板の反りが顕著となり、2cm□程度のサイズで0.
2mm以上の反りが発生する場合もあって、表面実装パ
ッケージとしては致命的な欠陥となるという問題が生じ
る。However, in order to improve the above-mentioned adhesion,
After removing the silicon-based component from the encapsulation resin, this time,
The warp of the substrate becomes remarkable, and it becomes 0.
A warp of 2 mm or more may occur, which causes a problem of a fatal defect for a surface mount package.
【0006】[0006]
【課題を解決するための手段】本発明の特徴は、内部導
体層を有する配線基板の基板端部を除く、一主面の一部
に凹部を形成して該内部導体層の一部を露出させ、該凹
部にICチップもしくは受動素子チップを1つ以上搭載
して、ボンディングワイヤ、半田、バンプもしくは、導
電性接着剤により該搭載したチップと該内部導体層の一
部との接続を行った後、該凹部を非導電性の封止樹脂に
より封止して、前記封止樹脂の表面と前記配線基板の一
主面とは略同一平面を形成するようにし、前記配線基板
の前記一主面に、導体パターンパッドの一部もしくは全
部とを被覆する導電性シールドパターンを前記封止樹脂
の表面上から前記配線基板の一主面上にまたがって連続
的に印刷する半導体装置に於いて、該シールド層の印刷
前に該シールド層で覆われるべき封止領域に導電性接着
剤を予め印刷しているものである。A feature of the present invention is that a recess is formed in a part of one main surface of a wiring board having an internal conductor layer, excluding the substrate end, to expose a part of the internal conductor layer. Then, one or more IC chips or passive element chips were mounted in the recess, and the mounted chip and a part of the internal conductor layer were connected by a bonding wire, solder, bump, or conductive adhesive. After that, the recess is sealed with a non-conductive sealing resin so that the surface of the sealing resin and the main surface of the wiring board are substantially flush with each other. In a semiconductor device that continuously prints a conductive shield pattern covering a part or all of a conductor pattern pad on the surface from one surface of the sealing resin to one main surface of the wiring board. Before printing the shield layer, the shield layer The sealing region to be covered are those that are preprinted with conductive adhesive.
【0007】また、本発明は、シールド層がCuペース
トより形成された層であり、密着度強化層がAgペース
トより形成された層であることを特徴とする上記の半導
体装置である。詳しくは、配線基板の凹部にICチップ
もしくは他の受動素子チップを搭載して該凹部を封止し
た後、封止部とその近傍のコンタクト用GNDパターン
部とを同時に被覆する領域にAgペースト等の導電性接
着剤を印刷し、さらに、該導電性接着剤印刷領域の上部
にCu等の導体ペーストを印刷することによりシールド
層を形成するものである。Further, the present invention is the above semiconductor device, wherein the shield layer is a layer formed of Cu paste and the adhesion enhancing layer is a layer formed of Ag paste. Specifically, after mounting an IC chip or another passive element chip in the recess of the wiring board and sealing the recess, Ag paste or the like is applied to a region that simultaneously covers the sealing part and the contact GND pattern part in the vicinity thereof. The conductive adhesive is printed, and a conductor paste such as Cu is printed on the conductive adhesive printing area to form the shield layer.
【0008】[0008]
【作用】本発明においては、配線基板の凹部にICチッ
プもしくは他の受動素子チップ部品を搭載後、該凹部を
封止し、さらに該封止領域を導体ペースト印刷によって
シールドするパッケージに於いて、従来例におけるシー
ルド層と封止樹脂との間に新たに、密着度強化層を形成
することにより、シールド層の封止樹脂にに対する密着
性が改善、向上するものである。According to the present invention, in a package in which an IC chip or another passive element chip component is mounted in a recess of a wiring board, the recess is sealed, and the sealed area is shielded by conductor paste printing, By forming a new adhesion enhancement layer between the shield layer and the sealing resin in the conventional example, the adhesion of the shield layer to the sealing resin is improved and improved.
【0009】[0009]
【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0010】[0010]
【実施例】図1は、本発明の実施例のシールド構造をリ
ードレスタイプのICパッケージに適用した場合の断面
図である。図1に示すように、これらのシールド構造の
製造に当っては、まず、配線基板(10)の凹部(1
3)内に露出する内部導体(19)の搭載ランドパター
ンに、ICチップ(14)もしくは他の受動素子チップ
(図示せず)を導電性接着剤によりマウントし、ICチ
ップ(14)と内部導体層(19)の他の箇所とをワイ
ヤー(15)によりワイヤーボンィングを施して電気的
接続を行った後、封止樹脂(16)をその樹脂面が基板
表面(回路基板の主面)と±0.05mm程度の範囲で
一致するように充填し、封止樹脂の乾燥後の樹脂面と基
板表面とが互いに略同一平面の一部を構成するようにす
る。なお、(12)はGNDパターンであり、またコン
タクト用のスルーホールは略している図示している。1 is a cross-sectional view of a shield structure of an embodiment of the present invention applied to a leadless type IC package. As shown in FIG. 1, in manufacturing these shield structures, first, the concave portion (1) of the wiring board (10) is formed.
3) The IC chip (14) or another passive element chip (not shown) is mounted on the mounting land pattern of the internal conductor (19) exposed inside by a conductive adhesive, and the IC chip (14) and the internal conductor are mounted. After wire bonding with the wire (15) to the other parts of the layer (19) to make an electrical connection, the resin surface of the sealing resin (16) becomes the substrate surface (the main surface of the circuit board). The resin is filled so as to match within a range of about ± 0.05 mm so that the resin surface after the sealing resin is dried and the substrate surface form a part of substantially the same plane. Note that (12) is a GND pattern, and the through holes for contacts are omitted.
【0011】しかる後、Agペースト等の導電性接着剤
を少なくとも封止樹脂(16)の一部または全部とコン
タクト用GNDパターン(20)とを覆う領域に、例え
ば10〜50μm厚で印刷し、150℃30分程度で乾
燥することにより硬化させ、密着強化層(18)を形成
する。さらにしかる後、Cuペースト等の導体ペースト
を前記密着強化層(18)の領域の一部または全部を被
覆するように、例えば10〜50μm厚で印刷し、15
0℃30分程度で乾燥することにより硬化させ、シール
ド層(17)を形成する。Thereafter, a conductive adhesive such as Ag paste is printed in a region covering at least a part or all of the sealing resin (16) and the GND pattern for contact (20) with a thickness of 10 to 50 μm, for example. It is cured by drying at 150 ° C. for about 30 minutes to form an adhesion strengthening layer (18). Thereafter, a conductor paste such as Cu paste is printed at a thickness of, for example, 10 to 50 μm so as to cover a part or the whole of the area of the adhesion reinforcing layer (18), and 15
It is cured by drying at 0 ° C. for about 30 minutes to form a shield layer (17).
【0012】このように、本発明では、従来例における
シールド層(17)と封止樹脂(16)との間に新た
に、密着度強化層(18)を形成することにより、シー
ルド層(17)の封止樹脂(16)に対する密着性の向
上を図っているものである。尚、シールド層(17)の
酸化防止の為、必要に応じてシールド層の全部を覆う領
域にソルダーレジスト等を印刷し、150℃15分程度
で乾燥することにより硬化させ、保護層(21)を形成
する。As described above, in the present invention, the adhesion layer (18) is newly formed between the shield layer (17) and the sealing resin (16) in the conventional example, so that the shield layer (17) is formed. It is intended to improve the adhesion of (1) to the sealing resin (16). In order to prevent the shield layer (17) from being oxidized, a solder resist or the like is printed on an area covering the entire shield layer as needed, and the shield layer (17) is dried at 150 ° C. for about 15 minutes to be hardened, whereby the protective layer (21) is formed. To form.
【0013】[0013]
【発明の効果】以上説明したように、本発明のシールド
構造は、極めて軽く、薄い構造でありながら、部品搭載
面の搭載領域を覆うシールドパターンを設けた本半導体
装置の特徴を維持しつつ、該シールド層の封止面への密
着性を大巾に改善できるという効果を有する。例えば、
クロスカット試験(JIS規格:K5400)による試
験結果では、従来では良い結果を出すのが非常に困難で
シールド層及び保護層ともに20μ前後の厚さで、充分
な均一性を確保しない限りは、安定した密着性が確保出
来なかったが、本発明のシールド構造によれば、10〜
50μ前後の膜厚でバラツキがあっても、100%安定
な密着性が得られる。その為、ICパッケージとしての
信頼性の向上が著しく、極めて安定なシールド効果を有
するICパッケージの提供を可能とする。As described above, the shield structure of the present invention is extremely light and thin, while maintaining the features of the present semiconductor device in which the shield pattern covering the mounting area of the component mounting surface is provided. This has the effect of greatly improving the adhesion of the shield layer to the sealing surface. For example,
According to the test result by the cross-cut test (JIS standard: K5400), it is very difficult to obtain a good result in the past, and both the shield layer and the protective layer have a thickness of about 20 μ, which is stable unless sufficient uniformity is secured. However, according to the shield structure of the present invention,
Even if there is variation in the film thickness of about 50 μ, 100% stable adhesion can be obtained. Therefore, the reliability of the IC package is remarkably improved, and it is possible to provide an IC package having an extremely stable shield effect.
【図1】本発明の第一の実施例の半導体装置を示す断面
図である。FIG. 1 is a cross-sectional view showing a semiconductor device of a first embodiment of the present invention.
【図2】従来技術の半導体装置を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional semiconductor device.
10 配線基板 11 端面電極 12 裏面シールドパターン 13 凹部 14 ICチップ 15 ボンディングワイヤ 16 封止樹脂 17 シールド層 18 密着度強化層 19 内部導体層 20 コンタクト用GNDパターン 21 保護層 10 Wiring Board 11 End Face Electrode 12 Back Shield Pattern 13 Recess 14 IC Chip 15 Bonding Wire 16 Sealing Resin 17 Shield Layer 18 Adhesion Strengthening Layer 19 Internal Conductor Layer 20 GND Pattern for Contact 21 Protective Layer
Claims (2)
を除く一主面の一部に凹部を形成して該内部導体層の一
部を露出させ、該凹部にICチップもしくは、受動素子
チップを1つ以上搭載してボンディングワイヤ、半田、
バンプもしくは導電性接着剤により該搭載したチップと
該内部導体層の一部との接続を行った後、該凹部を非導
電性の封止樹脂により封止して、前記封止樹脂の表面と
前記配線基板の一主面とが略同一平面を形成するように
し、前記配線基板の前記一主面に、導体パターンパッド
の一部もしくは全部とを被覆する導電性シールドパター
ンを前記封止樹脂の表面上から前記配線基板の一主面上
にまたがって連続的に印刷することでシールド層を形成
する半導体装置に於いて、該シールド層と前記封止樹脂
との間に導電性接着剤印刷による密着度強化層を設けた
ことを特徴とする半導体装置。1. A concave portion is formed in a part of one main surface of a wiring board having an internal conductor layer excluding a substrate end portion to expose a part of the internal conductor layer, and an IC chip or a passive element is formed in the concave portion. Bonding wire, solder,
After connecting the mounted chip and a part of the internal conductor layer with a bump or a conductive adhesive, the recess is sealed with a non-conductive sealing resin, and the surface of the sealing resin is A main surface of the wiring board is formed to be substantially flush with the main surface of the wiring board, and a conductive shield pattern for covering a part or all of the conductor pattern pad is formed of the sealing resin. In a semiconductor device in which a shield layer is formed by continuously printing from the surface to one main surface of the wiring board, a conductive adhesive is printed between the shield layer and the sealing resin. A semiconductor device having an adhesion enhancement layer.
た層であり、密着度強化層がAgペーストより形成され
た層であることを特徴とする請求項1に記載された半導
体装置。2. The semiconductor device according to claim 1, wherein the shield layer is a layer formed of Cu paste, and the adhesion enhancing layer is a layer formed of Ag paste.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7230730A JP2734424B2 (en) | 1995-08-16 | 1995-08-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7230730A JP2734424B2 (en) | 1995-08-16 | 1995-08-16 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0955597A true JPH0955597A (en) | 1997-02-25 |
JP2734424B2 JP2734424B2 (en) | 1998-03-30 |
Family
ID=16912408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7230730A Expired - Fee Related JP2734424B2 (en) | 1995-08-16 | 1995-08-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2734424B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001250873A (en) * | 2000-01-24 | 2001-09-14 | Infineon Technologies Ag | Protective device and electrical component with device |
KR20010109149A (en) * | 2000-05-30 | 2001-12-08 | 가타오카 마사타카 | A surface mount type electronic circuit unit |
US6462960B1 (en) | 1999-04-22 | 2002-10-08 | Nec Corporation | High frequency shielding structure and method |
JP2006310629A (en) * | 2005-04-28 | 2006-11-09 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
US7224052B2 (en) | 1999-12-03 | 2007-05-29 | Renesas Technology Corp. | IC card with controller and memory chips |
WO2009037807A1 (en) * | 2007-09-21 | 2009-03-26 | Panasonic Corporation | Electronic component package and method for producing the same |
KR101070181B1 (en) * | 2005-01-06 | 2011-10-05 | 싸이칩 인크. | Integrated passive devices |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05152781A (en) * | 1991-06-24 | 1993-06-18 | Cmk Corp | Manufacture of printed wiring board |
JPH0775279A (en) * | 1993-08-31 | 1995-03-17 | Matsushita Electric Ind Co Ltd | Resin mold type electric motor |
-
1995
- 1995-08-16 JP JP7230730A patent/JP2734424B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05152781A (en) * | 1991-06-24 | 1993-06-18 | Cmk Corp | Manufacture of printed wiring board |
JPH0775279A (en) * | 1993-08-31 | 1995-03-17 | Matsushita Electric Ind Co Ltd | Resin mold type electric motor |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6462960B1 (en) | 1999-04-22 | 2002-10-08 | Nec Corporation | High frequency shielding structure and method |
US7224052B2 (en) | 1999-12-03 | 2007-05-29 | Renesas Technology Corp. | IC card with controller and memory chips |
US7538418B2 (en) | 1999-12-03 | 2009-05-26 | Renesas Technology Corp. | IC card |
US7547961B2 (en) | 1999-12-03 | 2009-06-16 | Renesas Technology Corp. | IC card with bonding wire connections of different lengths |
US7768110B2 (en) | 1999-12-03 | 2010-08-03 | Renesas Technology Corp. | Nonvolatile memory apparatus |
US8018038B2 (en) | 1999-12-03 | 2011-09-13 | Renesas Electronics Corporation | IC card with terminals for direct access to internal components |
JP2001250873A (en) * | 2000-01-24 | 2001-09-14 | Infineon Technologies Ag | Protective device and electrical component with device |
KR20010109149A (en) * | 2000-05-30 | 2001-12-08 | 가타오카 마사타카 | A surface mount type electronic circuit unit |
KR101070181B1 (en) * | 2005-01-06 | 2011-10-05 | 싸이칩 인크. | Integrated passive devices |
JP2006310629A (en) * | 2005-04-28 | 2006-11-09 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
WO2009037807A1 (en) * | 2007-09-21 | 2009-03-26 | Panasonic Corporation | Electronic component package and method for producing the same |
JP5234001B2 (en) * | 2007-09-21 | 2013-07-10 | パナソニック株式会社 | Electronic component package and manufacturing method thereof |
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