JPH0951344A - ATM bus system - Google Patents

Abstract

(57) Abstract: To provide an ATM bus system capable of flexibly coping with an increase in the amount of information and the type of information, a real-time property ensuring, and a change in the scale of data to be processed and a generation pattern, which accompany multimedia. An ATM bus 11 is a bus for transferring information based on an ATM transfer mode, and includes bus users 10a to 10a.
10d and the bus arbitration circuit 12 are connected. The control bus 8 is a bus for transferring control signals sent when the central control unit 1 controls the bus users 10a to 10d. When the bus users 10a to 10d simultaneously send a bus use request, the bus arbitration circuit 12 selects the only bus use request from the bus use requests, and displays information indicating the bus user who issued the selected bus use request, Notify all bus users. As a result, only the selected bus user starts the information transfer operation using the ATM bus 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for simultaneous processing of control processing and communication processing in a computer device such as a personal computer or a workstation.
TM bus system

[0002]

2. Description of the Related Art In recent years, in computer devices such as personal computers and workstations, in order to support multimedia, enormous information transfer accompanying image processing, simultaneous processing in a plurality of media, real-time performance in image communication, etc. Various processing functions, such as securing
That is, a function of performing control processing and communication processing in parallel is required. On the other hand, conventionally, measures have been taken to realize these requirements by a method of increasing the information transfer rate of a single bus provided inside a computer.

FIG. 16 is a block diagram showing the basic structure of a conventional information transfer system. The central control unit 1 uses the control signals 6a, 6b, 6c transferred via the control bus 8 to store the information storage unit 2, the information processing unit 3, which is a bus user,
It controls the network line connection unit 4. Information storage unit 2
Stores media information with strong real-time characteristics. Note that, here, information such as images and sounds that are requested to be processed in real time is referred to as media information having a strong real-time property. The information processing unit 3 processes media information having a strong real-time property into a predetermined format.

The network line connection unit 4 has an interface with the ATM network 5, and is connected to this system and A
Connect to the TM network 5. The signal 7a is media information with a strong real-time property that is transferred from the information storage unit 2 to the information processing unit 3. Similarly, the signal 7b is sent from the information processing unit 3 via the network line connection unit 4 to the ATM.
This is media information that is transferred to the network 5 and has strong real-time characteristics.

Here, ATM (Asynchronous Transfer)
Mode: Asynchronous transfer mode) A network is several tens of bp
A fixed length cell (packet) of 53 bytes (1 byte = 8 bits) for all communication information from s to several hundred Mbps
It is a communication network that divides into two, transfers them mixedly in a transmission line, and performs high-speed processing by high-speed packet exchange. A cell in the ATM network is composed of a header (control information section) of 5 bytes and an information field of 48 bytes. The advantage of the ATM network lies in the high flexibility and efficiency of being able to mix and transmit communication traffic of various speeds including high speed.

Next, taking a moving image signal as an example of media information having a strong real-time property, the above-mentioned configuration in the case of transferring the moving image signal from the information storage unit 2 to another computer device via the ATM network 5. The operation of the information transfer system will be described. The central control unit 1
Using the control signal 6b transmitted via the control bus 8, the information processing unit 3 is instructed to receive the moving image signal. As a result, the information processing unit 3 is
A signal indicating whether or not the moving image signal can be received is returned.

After confirming that the information processing unit 3 can receive the moving image signal, the central control unit 1 uses the control signal 6a transmitted via the control bus 8 to inform the information storage unit 2. Then, the transmission of the moving image signal to the information processing unit 3 is instructed. Then, the information storage unit 2 transmits the moving image signal 7a previously stored in the information storage unit 2 to the information processing unit 3 via the control bus 8. The information processing unit 3 receives the moving image signal 7a transmitted via the control bus 8 and processes it into a predetermined format.

Next, the central control unit 1 uses the control signal 6c transmitted via the control bus 8 to the ATM of the moving image signal 7b obtained by processing the moving image signal 7a to the network line connecting unit 4. The transfer to the network 5 is instructed.
As a result, the network line connection unit 4 returns to the central control unit 1 a signal indicating whether or not the moving image signal can be transferred. After confirming that the network line connection unit 4 can transfer the moving image signal, the central control unit 1 uses the control signal 6b transmitted via the control bus 8 to inform the information processing unit 3 of the network. Line connection part 4
To the transmission of the moving image signal 7b.

Then, the information processing section 3 receives the moving image signal 7b.
To the network line connection unit 4 via the control bus 8. Finally, the network line connection unit 4
Transfers the moving image signal 7b to the ATM network 5.

[0010]

By the way, in the above-mentioned conventional information transfer system, as the amount of data to be processed increases, the control information at the time of continuous data transfer and the real-time media information compete on the same bus. In addition, there is a drawback that waiting occurs between the information and it becomes difficult to secure real-time property.

To give an example, in the conventional information transfer system shown in FIG.
The moving image signal 7b is transferred from the information processing unit 3 to the network line connecting unit 4 in order to be transferred via the TM network 5.
During the transfer to the control signal 6a
Control signal 6a, 6b and moving image signal 7b, if the information storage unit 2 is instructed to transmit or the control signal 6b is used to instruct the information processing unit 3 to receive another moving image signal. Since the and are competing on the control bus 8, the moving image signal 7
In some cases, the transfer of b is forced to be interrupted.

Due to the interruption of the transfer, the image quality is deteriorated and the image is disturbed in the computer device of the communication partner receiving the moving image signal 7b through the ATM network 5. As a result, in multimedia communication in which moving image signals and the like are communication processed, processing of media information having a strong real-time property is often interrupted. In order to address this issue, Tran Switch (USA) has developed a technology to put ATM information transmission on the bus.
Cell Bus (transfer method) using CUBIT (VLSI) is known.

In addition, the STM (Synch
ronous Transfer Mode (Synchronous Transfer Mode) MVIP (Multivender In
integration protocol) is known. This standard is 1
990, Natural Micro Systems (NMS),
Go-MV was announced by Mitel and 5 other companies, and subsequently, in 1994, GO-MV became the industry-neutral organization.
IP (The Gloval Organization for MVIP) was established. However, conventionally, a technique for transferring information using the ATM bus together with the control bus has not been disclosed.

In multimedia communication, etc.,
It is necessary to perform so-called broadcast communication, in which media information with strong real-time property is simultaneously transferred to a plurality of bus users in a computer. However, the conventional broadcast communication method is for a plurality of bus users who are information transfer destinations. I was transmitting and receiving once in sequence. That is, in the conventional method,
In order to transfer the same data to a plurality of bus users, the data is held and the transfer destination address is designated for each transfer. However, according to such a method, there is a problem that a huge amount of time, which is proportional to the number of receiving side bus users, is required to complete the transmission of information to all the receiving side bus users.

In order to solve such a problem, the address information of all the receiving side bus users or the address information specified so that all the receiving side bus users can be designated at the same time is provided in the header portion of the information cell. It is also possible to consider a method in which the data is stored in and transmitted / received. However, in these cases, the generation of address information in the transmission circuit of the transmission side bus user and the determination processing in the reception circuit of the reception side bus user (the address information in the header is the above-mentioned specified address information However, there is a drawback in that the processing for determining whether or not it has been designated) becomes complicated and the transmission processing time becomes long.

Further, conventionally, one bus is shared by a plurality of bus users, and a bus arbitration circuit is provided on the bus so that data transmitted from each bus user does not compete on each bus user. There is an information transfer system that arbitrates the data transfer. In this type of information transfer system, when a bus user has data that he / she wants to transfer preferentially, when the bus user notifies the bus arbitration circuit of a bus use request, the bus user indicates the priority level of data transfer. The bus arbitration circuit that receives the bus use request by arbitrating from the highest priority stage based on the priority stage assigned to the bus use request and assigns one bus user according to the adjustment result. In some cases, a bus use permission is given and only a bus user who has received the use permission transfers data.

In such an information transfer system, conventionally, for example, when a plurality of bus users send a bus use request to which a priority level of the same level is given, the arbitration circuit selects one of the bus use requests. Only one was given permission to use the bus. For this reason, the bus user who is not granted the use permission has at least the bus user who is given the permission even though the bus use request of the same priority level as that of the bus user who is given the use permission is transmitted. The bus could not be used until the data transfer was completed.

Further, in the conventional information transfer system, for example, in the case of expanding the ATM bus in order to increase the information transfer capacity in an ATM bus system which transfers information in the ATM transfer mode based on a fixed length cell unit. , Use request phase (the stage where the bus user sends a bus use request to the bus arbitration circuit), bus use enable phase (bus arbitration circuit arbitrates the received bus use request and permits the bus user to use the bus according to the result. Bit cycle of the ATM bus while the bus cycle consisting of a data transmission / reception phase (a step in which a bus user who has received a bus use permission transmits data to a target bus user) remains the same before and after the bus expansion. It is conceivable to extend the data transfer amount per transfer only by extending only the data transfer amount.

However, in such a method, a bus user corresponding to the bit width of the expanded ATM bus can be connected to the expanded ATM bus, but a bus user corresponding to the bit width of the ATM bus before expansion can be connected to the expanded ATM bus. Cannot connect to the bus. Further, there is a problem that the bus arbitration circuit also has to be changed to a circuit corresponding to the bit width of the expanded ATM bus.

The present invention has been made in view of the above circumstances, and increases the amount of information and the type of information due to the multi-media, secures the real-time property, and changes the scale and generation pattern of data to be processed. A that can flexibly respond to
The purpose is to provide a TM bus system.

[0021]

According to a first aspect of the present invention, an AT which transfers information in an ATM transfer mode based on a fixed-length cell unit on a bus which is an information transfer path.
M bus system, the A for performing the information transfer
In an ATM bus system that simultaneously performs information transfer in units of one cell at the same time when a plurality of bus use requests of the TM bus occur, a plurality of devices connected to the ATM bus and sharing the bus to perform the information transfer. A bus user; and a bus arbitration unit for selecting a single bus use request from a plurality of bus use requests sent simultaneously by the bus user and determining a bus user who has issued the bus use request. An ATM bus system, wherein the cell unit is an AT
In addition to ATM bus data including an M header, an extension header is provided, and the extension header includes bus use request information for the bus user to make the bus use request to the bus arbitration means, and the bus arbitration means. Consisting of bus use permission information indicating the only bus user determined by and user address information for designating a transmission or reception bus user,
The bus arbitration unit arbitrates a plurality of bus use requests notified by the bus use request information, and uses the bus use permission information to grant a bus use permission given to only one bus user to all the bus users. The bus user judges the bus use permission information so that only the bus user who has received the bus use permission can transfer the information in cell units within the same cell time as the transfer of the extension header. Further, the bus user who has judged that the address is the corresponding address by judging the user address information is the AT
The ATM bus system is characterized by receiving M bus data.

According to a second aspect of the present invention, in the ATM bus system according to the first aspect, a central control means for controlling processing and information transfer performed by each of the bus users, and the central control means from the central control means A control bus for transferring control information for controlling each bus user to a user is provided.

According to a third aspect of the invention, in the ATM bus system according to the second aspect, an address peculiar to the bus user who is the sender of the information is given to all the bus users who are the receivers of the information. , The bus user, which is set in advance via the control bus and is the source of the information, assigns its own address unique to the bus user to the extension header in the cell unit, and then transmits the cell unit in the bus user. AT from the circuit
All the bus users who send out to the M bus and are the information receiving sources are individually and in parallel, and the user address of the sending source preset through the control bus and the AT
It is characterized in that a comparison is made with an address given to each cell on the M bus, and when the addresses match based on the comparison result, the broadcast communication is performed by receiving the cell.

According to a fourth aspect of the present invention, in the ATM bus system according to any one of the first to third aspects, a plurality of priority stages indicating the priority of the information transfer are provided, and the bus user. Selects one priority stage from the plurality of priority stages and adds it to the bus use request information, and the bus use permission at a certain priority stage in the bus arbitration means is higher than the certain priority stage. If there is no bus use request of the certain priority stage, the bus use request of the priority stage lower than the certain priority stage is ignored, and the bus is sequentially and equally used for the bus use request of the certain priority stage and the same priority stage as the certain priority stage. It is characterized by performing a multi-stage priority bus arbitration that gives a bus permission as much as possible.

The invention according to claim 5 is the ATM bus system according to any one of claims 1 to 4, wherein the ATM bus is a main bus in which two identical buses are installed in parallel. And a sub-bus, and the bus arbitration unit separately arbitrates the bus use request from the bus user in one data transfer in the main bus and the sub-bus, and the main bus, An ATM bus system comprising a synchronization control unit that synchronizes bus cycles of the sub-bus, wherein the bus user is connected to the main bus and is provided so as to share the main bus and the sub-bus. , The main bus and the sub bus are respectively connected, and when there is data to be transferred, the two Bus controller which issues the bus use request to the star controller and transfers data when the bus use permission is obtained from the master controller, bus use state detecting means for detecting the use state of the ATM bus, and the bus The bus user selects one data unit for transfer by the main bus or the sub-bus according to the bus congestion information by the use state detecting device; For the unit transfer, first, the main bus is used, and the sub-bus is used only when the bus use state detecting means detects that the main bus is congested.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an ATM bus system according to the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing the structure of an ATM bus system according to a first embodiment of the present invention. In this figure, parts corresponding to the parts in FIG. 16 are assigned the same reference numerals and explanations thereof are omitted.

In FIG. 1, 10a to 10d are bus users of the ATM bus system. Each bus user 10a-
Addresses different from each other are assigned to 10d, and it is possible to uniquely determine which bus user is by specifying the address. Further, 11 is an ATM bus which is a common data transfer path of this ATM bus system. Each of the bus users 10a to 10d can directly transfer data via the ATM bus 11 to any other party on this bus. The data transferred here is media information with a strong real-time property. Also, 1
2 is a bus arbitration circuit.

Here, generally, in the bus, only one information transfer is performed at a time. Therefore, the bus arbitration circuit 12 determines which bus user can transmit information at a certain time, and arbitrates the conflict caused by the bus users 10a to 10d sharing the data transfer path. In the control bus 8, the central control unit 1 controls each bus user 10
This is a transfer path used when transferring control signals to a to 10d, and is not used for transferring media information having a strong real-time property.

On the other hand, in this ATM bus system,
Data transfer is performed in a so-called ATM transfer mode, which is composed of a plurality of fixed length cell units. Figure 2 shows ATM bus 11
It is an example of the data structure of the above one cell unit. As shown in the figure, the data in units of one cell is composed of an extension header provided at the head and ATM bus data. Furthermore, the extension header is composed of three types of information fields: bus use request information, bus use permission information, and bus user address information.

Here, the bus use request information in the extension header is transmitted to the bus arbitration circuit 12 by the AT of each bus user.
This is a field that stores request information for requesting permission to use the M bus 11. The bus use permission information is an information field for designating the only bus user selected by the bus arbitration circuit 12 from the bus users who have made a bus use request according to a procedure described later. Further, the user address information is an information field including an address for designating another bus user when a certain bus user sends data to another bus user.

On the other hand, the ATM bus data is composed of 53 bytes, and has an ATM header defined by the international standard ITU-TS (International Telecommunication Union-Telecommunication Standardization Sector) or the ATM Forum and an information field ATM. It consists of a payload.

Next, with reference to FIG.
The operation of the TM bus system will be described. Here, the case where data transfer from the bus user 10a to the bus user 10d and data transfer from the bus user 10b to the bus user 10c are shown. The central control unit 1 instructs the bus users 10a and 10b via the control bus 8 to transmit data. As a result, the bus user 10a transmits the transmission data SDa to the ATM bus 11 in cell units, and the bus user 10d receives the data as reception data RDd in cell units.

Similarly, the bus user 10b sends the transmission data S
Db is transmitted to the ATM bus 11 in cell units, and this data is received in cell units as reception data RDc by the bus user 10c. In addition, 13 represents a cell array on the ATM bus 11, in the order determined by the bus arbitration circuit 12,
It shows how cells are sequentially arranged on the ATM bus 11. Data transfer is performed by sequentially repeating the three phases of the bus use request phase, the bus use permission phase, and the data transmission / reception phase shown in FIG. 2 during one cell time. Hereinafter, description will be given with reference to FIGS.

(1) Bus use request phase When a request for information transfer using the bus occurs, each bus user 10a to 10d uses the bus use request information in common and sends the request via the ATM bus 11. Arbitration circuit 1
Notify 2.

(2) Bus use permission phase The bus arbitration circuit 12 monitors the bus use request information of the cell notified from each of the bus users 10a to 10d in the cell time and makes a bus use request. Find out. As a result of the monitoring, the bus use request is issued from a plurality of bus users, and the ATM bus 1 is
1 is used to determine the only bus user that is authorized to send out one cell of data. After selecting any one bus user as described above, all the bus users 10a to 10d are notified via the ATM bus 11 of the information about the determined bus user as the bus use permission information.

(3) Data Transmission / Reception Phase Each of the bus users 10a to 10d who has issued the bus use request is
The content of the bus use permission information included in the data notified from the bus arbitration circuit 12 is checked to determine whether or not the user is a bus user who has been given the data transmission permission. As a result of this judgment, if it is found that the transmission permission is given,
The bus user sends one cell of data to the ATM bus 11. At the same time, each of the bus users 10a to 10d determines the user address information, and when the address designated by the information corresponds to the received address, receives the ATM bus data following the user address information.

In this way, data is transmitted and received among the bus users 10a to 10d in units of fixed length cells. As described above, in the present embodiment, the control signal is transferred via the control bus 8 and the media information having a strong real-time property is transferred via the ATM bus 11. Therefore, for example, if a continuous moving image signal is
During transfer of the moving image signal from the bus user 10a to the bus user 10d for transfer via the TM network, the central control unit 1 instructs the bus user 10b to send via the control bus 8. However, since the moving image signal from the bus user 10a is transferred through the ATM bus 11, the transfer is not interrupted.

As described above, since the control signal and the media information having a strong real-time property are transferred via different buses, they are completely separated from each other and mutual influence is avoided. Therefore, there is no competition between the two, and real-time property such as continuity of the moving image signal is secured.
Further, the ATM bus 11 uses the ATM system as the information transfer system in addition to sharing the function with the control bus 8 as the information transfer bus as described above, and therefore has the following characteristics. The ATM method is a method in which all information is divided into fixed-length packets called cells (53 bytes + extension header in this method) and transferred at high speed. This allows the ATM traffic to be independent of the communication traffic scale and generation pattern. It is possible to select various transfer rates.

In addition, by using the ATM method, a plurality of continuous data do not affect each other at the same time, and the transfer state can be maintained. Further, since the media information having a strong real-time property is directly transferred by the ATM method via the ATM bus 11, it becomes possible to connect the transfer information to the ATM network without the network line connecting section having a conversion device. , It is possible to prevent the deterioration of information quality at the time of network connection.

[Second Embodiment] The second embodiment of the present invention flexibly supports broadcast communication between a single transmitting-side bus user and a plurality of receiving-side bus users on an ATM bus. An ATM bus system that can be used will be described. The configuration of the ATM bus system according to this embodiment is similar to that of the ATM bus system according to the first embodiment shown in FIG. Further, the information cell according to the present embodiment,
Although it is similar to the information cell in the first embodiment shown in FIG. 2, as the user address information in the extension header, not the receiving side user address but the transmitting side user address is designated. Further, the arbitration by the bus arbitration circuit 12 is performed in exactly the same way.

Next, the operation of the broadcast communication by the ATM bus system having the above configuration will be described with reference to FIG. In addition, here, as an example, a case where the broadcast communication is performed from the bus user 10a to the bus users 10b and 10c is shown. First, when a request for information transmission from the bus user 10a to the bus users 10b and 10c occurs, the bus user 10b and the bus user 10c are set with the address of the bus user 10a via the control bus 8. Then, the bus user 10b and the bus user 10c store the address in the built-in memories in the receiving circuits (not shown).

Next, the bus user 10a on the transmitting side
The data to be transmitted is stored in the ATM payload portion of the information cell, and the address of itself (bus user 10a) is stored in the user address information portion of the extension header. Then, the bus user 10a sends the information cell created by the above method onto the ATM bus 11 by using a transmission circuit (not shown). Next, the bus user 1 on the receiving side
0b constantly monitors the ATM bus 11, and the ATM bus 1
When the information cell is transmitted to the first cell, the reception circuit is used to fetch the information cell and read the transmission side user address information stored in the extension header portion thereof.

Then, the bus user 10b compares the transmitting side user address information with the address stored in the built-in memory (the address set via the control bus 8). As a result, if the two addresses match, the data of the ATM payload portion is subsequently read. At that time, the bus user 10c also performs the same processing in parallel with the above-mentioned processing by the bus user 10b (acquisition of information cells, comparison of addresses, reading of data in the payload portion). That is, the bus user 10
b and the bus user 10c individually and in parallel fetch the information cells, compare the addresses, and read the data of the payload portion.

By the above procedure, the broadcast communication from the bus user 10a to the bus users 10b and 10c is performed. The bus user 10a divides the data into a plurality of information cells and stores them, and individually sends the information cells onto the ATM bus 11 as shown in FIG. And
The bus user 10b and the bus user 10c individually receive a plurality of information cells transmitted on the ATM bus 11 by the same processing as the above-mentioned receiving method, and the ATM of the information cells is received.
Read data from the payload part.

As described above, according to the broadcast communication method in the ATM bus system according to the present embodiment, a plurality of receiving side bus users can simultaneously receive information in parallel. It takes less time. Further, the transmitting side bus user may always store only the address information of himself / herself as the process of storing the address information in the information cell, and the receiving side bus user may receive the transmitting side user address given via the control bus 8. Since it is only necessary to detect information, it is possible to simplify the processing for both bus users on the transmitting side and the receiving side.

[Third Embodiment] In the third embodiment of the present invention, when a bus user notifies a bus arbitration request to a bus arbitration circuit, a priority stage indicating the priority of data transfer is added and transmitted, and When an arbitration circuit receives a bus use request, the arbitration circuit arbitrates from a higher priority stage based on the priority stage given to the bus use request. An ATM bus system including a bus arbitration circuit that performs arbitration so that the bus users can use the bus evenly when transmitted from the following.

The operation of the above ATM bus system will be described below with reference to FIGS. Further, FIG. 9 shows the configuration of information cells transmitted and received at that time. FIG. 5 is a block diagram showing the configuration of the ATM bus system according to the same embodiment. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the bus users 10a to 10d, 14
Reference numerals a to 14d denote data transfer control circuits, which select one from a plurality of priority stages provided and make a use request and data transfer of the ATM bus 11. Also, 15a to 15d
Is a bus controller and has an input / output function on the ATM bus 11. In the bus arbitration circuit 12, 1
Reference numeral 7 denotes a master controller, which is a bus user 10a to 1
It controls the input / output of each bus controller 15a to 15d at 0d. 18a, 18b, 18c, ..., 18n are priority stage arbitration circuits, which have a priority stage 1, a priority stage 2, a priority stage 3, ...
Arbitration for bus use permission in. Further, 19 is a bus use permission transmission circuit, which is a priority stage arbitration circuit 18a ...
The master controller 1 collects the arbitration results by 18n.
All bus users 10a to 10d are notified of the bus use permission via 7. Here, it is assumed that priority level 1 has the highest priority, followed by priority level 2, priority level 3, ..., Priority level n. Further, the priority stage arbitration circuits 18a to 18n are installed by the number of priority stages supported by this system.

First, in the bus use request phase, when the bus users 10a to 10d have data to be transferred, the data transfer control circuits 14a to 14d select one from a plurality of priority levels, and the priority level information. 16a-1
The bus use request information 20 to which 6d is added is transmitted to the master controller 17 via the bus controllers 15a to 15d. Then, the master controller 17 sets the received bus use request information to 20a and sets the priority stage 1 arbitration circuit 1
Pass to 8a. In this figure, the bus user 10
a and the bus user 10b assign priority level 1 to the bus user 1
0c and the bus user 10d specify the priority level 2 respectively.

Next, in the bus use permission phase,
The priority stage 1 arbitration circuit 18a uses the bus use request information 20a.
Priority level 1 if there is a priority level 1 request in the
Arbitrate each other. Then, the arbitration result 21a is passed to the bus use permission transmission circuit 19. On the other hand, when there is no priority stage 1 request, the bus use request information is passed to the priority stage 2 arbitration circuit 18b as 20b. At this time, the priority stage 2 arbitration circuit 18b passes the arbitration result 21b to the bus use permission transmission circuit 19 when there is a request of the priority stage 2, and sets the bus use request information as 20c and sets the priority stage 3 when there is no request. It is passed to the arbitration circuit 18c. Here, arbitration between the same priority stages in each arbitration circuit is performed so that the corresponding bus users are sequentially and equally selected.

Similarly, when there is a request for arbitration in each arbitration circuit, the arbitration circuit performs arbitration and transfers the arbitration result to the bus use permission transmission circuit 19. And
The bus use permission transmission circuit 19 uses the arbitration results 21a to 21n.
When any one of the above is received, the bus use permission information 22 including the information about the bus user determined by the arbitration result is passed to the master controller 17. Further, the master controller 17 notifies the same information 22 to all the bus users 10a to 10d via the ATM bus 11.

In the case of this figure, the bus users 10a,
10b, 10c, 10d are priority levels 1, 1, 2,
Since 2 is designated, the priority stage 1 arbitration circuit 18a transmits the arbitration result 21a for permitting the bus user 10a or the bus user 10b to the bus use permission transmission circuit 19. Then, the bus use permission information 22 which permits the use of the ATM bus 11 is transmitted to the bus users 10a to 10d.

Next, in the data transmission / reception phase, each of the bus users 10a to 10d who has issued the bus use request checks the content of the bus use permission information included in the data notified from the bus arbitration circuit 12, and sends the data by itself. Determine if you are an authorized bus user. If it is determined as a result of this determination that the transmission permission has been given, the bus user transmits one cell of data to the ATM bus 11. In this case, the bus user 10a and the bus user 10b
And alternately transfer data. This state is shown in FIG.

FIG. 6 shows the flow of data on the ATM bus in the priority stage of each bus user shown in FIG. Here, the bus user 10a has priority level 1, the bus user 10b has priority level 1, and bus user 10c.
Since the priority level is 2 and the bus user 10d is the priority level 2, the ATM bus 11 is alternately used depending on the data of the bus users 10a and 10b.

Similarly, FIG. 7 shows the bus user 10a in FIG.
, The bus user 10a has no use request, the bus user 10b has priority stage 1, the bus user 10c has priority stage 2, and the bus user 10
Since d becomes the priority stage 2, the ATM bus 11 is used by the data of the bus user 10b only.

Similarly, FIG. 8 shows a case where there is no more usage request from the bus user 10b in FIG. 7, that is,
The bus user 10a has no use request, the bus user 10b has no use request, the bus user 10c has the priority stage 2, and the bus user 10d has the priority stage 2.
And ATM bus 1 alternately according to the data of the bus user 10d
1 is used.

As described above, in this embodiment, 1
In a system in which one ATM bus is shared by a plurality of bus users, the bus users add priority stage information to the bus use request information and notify the bus arbitration circuit,
The bus arbitration circuit selects the bus request from the bus user having the highest priority level and gives the bus use right. Therefore, a bus user who wants to transfer high-priority data can preferentially transfer data using the ATM bus. Further, even when the bus use requests of the same priority stage are transmitted from a plurality of bus users, those bus users can use the bus equally.

[Fourth Embodiment] In the fourth embodiment of the present invention, an AT capable of connecting a bus user corresponding to the bit width of the ATM bus before expansion to the ATM bus after expansion.
The M bus system will be described. Hereinafter, a fourth embodiment will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of the ATM bus system according to the same embodiment. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. However, the central controller 1 and the control bus 8 are not shown.

The ATM bus system shown in this figure has two ATM buses in parallel with the ATM bus before expansion, which are called a main bus 11A and a sub bus 11B, respectively. Here, the main bus 11A is an ATM bus used first by each bus user during data transfer, and the sub-bus 11B is an ATM bus used when data transfer on the main bus 11A is congested. The main bus 11A and the sub-bus 11B have the same bit width as the above-mentioned ATM bus before expansion. And bus users 10c and 10d corresponding to the ATM bus before expansion
The bus controllers 15c and 15d of the main bus 11
Connected to A only.

Reference numeral 10e is a bus user provided in place of the bus user 10a, and has two bus controllers 15eA and 15eB having the same functions as the bus controllers 15c and 15d in the bus users 10c and 10d. The one bus controller 15eA is connected to the main bus 11A, and the other bus controller 15eB is connected to the sub bus 11B. Further, 24e is a bus use state detection circuit, which is a bus controller 15e.
According to the usage status information 25e from A, the main bus 11A
Monitor the usage status of.

Further, reference numeral 26e is a used bus selection circuit, and the bus used state detection circuit 24e transfers the bus to the minimum by the bus congestion information 27e which is transferred when the congestion of the main bus 11A is detected by the use state information 25e. Switch for each data transfer unit. This switching is performed by the bus controller control signal 28 for selecting the bus to be used.
e from the used bus selection circuit 26e to the bus controller 1
It is performed by outputting to 5eA and 15eB.

A bus user 10f is provided in place of the bus user 10b and has the same structure as the bus user 10e. The bus controller 15fA in the bus user 10f is connected to the main bus 11A, and the bus controller 15fB is connected to the sub bus 11B.

Reference numeral 12a is a bus arbitration circuit, which arbitrates permission to use the buses of both the main bus 11A and the sub-bus 11B, and synchronizes both bus cycles. In this bus arbitration circuit 12a, 17A and 17B are master controllers, each having the same function as the master controller provided in the bus arbitration circuit 12 before expansion,
It controls each bus controller connected to the main bus 11A and the sub bus 11B. A synchronization control unit 29 synchronizes the bus cycles of the main bus 11A and the sub-bus 11B with a synchronization signal 30.

Here, bus users 10c and 10d.
Is connected only to the main bus 11A and uses the same main bus 11A to perform exactly the same operation as before the bus expansion. Further, the bus users 10e and 10f are connected to both the main bus 11A and the sub-bus 11B. However, when transferring one data unit, these buses are not used at the same time. To use. Then, the sub bus 11B is used only when the bus usage state detection circuits 24e and 24f determine that the main bus 11A is congested. Information transfer between these bus users is performed based on the bus use request phase, the bus use permission phase, and the data transmission / reception phase, as in the first embodiment.

The operation of the ATM bus system having the above configuration will be described below. First, regarding the data transfer between the bus users 10e and 10f corresponding to the extension of the ATM bus,
This will be described with reference to FIG. Here, a case where data is transferred from the bus user 10e to the bus user 10f is shown. First, the bus user 10e performs the data transfer 31A to the bus user 10f by using the main bus 11A, and thereafter, when the main bus 11A is used by another bus user, the bus use state detection circuit 2 of the bus user 10e.
4e is the main bus 11A based on the usage status information 25e.
And the bus congestion information 27e is notified to the used bus selection circuit 26e.

Next, the used bus selection circuit 26e receives the bus congestion information 27e and receives the bus controller control signal 2
8e instructs the bus controller 15eA connected to the main bus 11A to stop the data transfer, and instructs the bus controller 15eB connected to the sub bus 11B to transfer the data. As a result, the data transfer 31A by the main bus 11A is
The data transfer by B is switched to 31B. At that time, the bus user 10f receives the data from the main bus 11A, but the bus user 10f receives the data from the sub bus 11B by switching the transfer bus of the bus user 10e. In this case, the bus user 10f is on the main bus 11A and the sub-bus 1
Although the data on 1B can be received at the same time, the data to be received is identified and processed by the address described in the user address information.

After that, another bus user selects the main bus 11
When the use of A is stopped and the bus 11A becomes unused,
The bus usage state detection circuit 24e determines that the congestion of the main bus 11A has been resolved. As a result, the used bus selection circuit 26e instructs the bus controller 15eB to stop the data transfer and the bus controller 15eA to transfer the data by the bus controller control signal 28e. Therefore, data transfer 31 on the sub-bus 11B
B is switched to the data transfer 31A on the main bus 11A, and the bus user 10f receives the data from the main bus 11A.

FIG. 12 is a diagram showing in time series an example of changes in the bus use states of the main bus 11A and the sub-bus 11B. In this example, when the bus user 10e uses the main bus 11A to transfer data to the bus user 10f, if the bus 11A becomes congested, the sub bus 11B is used, and then the congestion of the main bus 11A disappears. It is shown that the bus 11A is used again. In this figure, one frame shows one bus cycle,
The frame 32a marked "Use 10e" is the bus user 10e.
Indicates the bus cycle used for data transfer. A frame 32b shows a bus cycle used for data transfer by another bus user, and a frame 32c shows an unused bus cycle.

Next, the bus user 1 corresponding to before the bus expansion
Data transfer between 0c and the bus user 10e corresponding to the bus extension will be described with reference to FIG. Here, a case where data is transferred from the bus user 10e to the bus user 10c is shown. First, it is assumed that the bus user 10e uses the main bus 11A to transfer data 33A to the bus user 10c, and then the main bus 11A is used by another bus user. However, at this time, the bus user 10e determines that the bus 11A is crowded, so that the main bus 11A
The switching operation from the upper data transfer 33A to the data transfer on the sub bus 11B is not performed.

That is, the bus user 10c selects the sub-bus 1
Since the data cannot be received from 1B, the bus user 10e does not transfer the data when the main bus 11A is congested. In this case, for example, by recording the addresses of the bus users 10c and 10d corresponding to before expansion via the control bus 8 (not shown) in advance, the bus user 10e can sub-bus 1 when the main bus 11A is busy.
It is possible not to perform the switching operation to 1B.

After that, when the main bus 11A becomes unused, the bus usage state detection circuit 24e determines that the congestion of the bus 11A has been resolved, and restarts the data transfer 33A to the bus user 10c using the bus 11A. To do. FIG.
Is the main bus 11A and the sub bus 11B in this case.
FIG. 6 is a diagram showing an example of a change in bus usage state in time series. The frames 32a, 32b, 32c in this figure
Is similar to each bus cycle in FIG. In the figure, when the bus user 10e uses the main bus 11A to transfer data to the bus user 10c, when the bus 11A is congested, the data transfer is stopped, and when the congestion is resolved, the data transfer is restarted. Is represented.

Finally, the data transfer between the bus users 10c and 10d before the bus expansion will be described with reference to FIG. In this figure, the case where the data transfer 34A from the bus user 10c to the bus user 10d is performed is shown. In this case, since both bus users 10c and 10d are connected only to the main bus 11A, data transfer is performed only via the same bus 11A.
That is, the data transfer is performed in exactly the same way as the data transfer before the bus expansion.

As described above, in the fourth embodiment, as shown in FIG. 10, two ATM buses having the same bit width as before expansion are used.
Books are installed in parallel. Then, the corresponding bus user before expansion can be connected to the main bus so that the bus user uses only the main bus. Also,
A bus user who is connected to both of the two buses and supports the bus expansion uses the main bus when transferring data to the corresponding bus user before the bus expansion, and transfers data to the bus user corresponding to the bus expansion. In this case, the main bus is used first, and the sub bus is used only when the main bus is crowded.

The determination of the congestion of the main bus may be made, for example, by monitoring the bus use request information (see FIG. 2) on the same bus. Further, the transmission side bus user corresponding to the bus extension does not use two buses at the same time in the same bus cycle in order to maintain the order of arrival of data in the reception side bus user. In addition, the receiving bus user can simultaneously receive data from different bus users in the same bus cycle. The bus arbitration circuit of the present invention uses the synchronization control unit in the bus arbitration circuit so that the bus user does not have to adjust the timing in the bus user every time the bus user switches the bus. Fully synchronize the bus cycle of.

According to the configuration described above, the AT before expansion
By installing two M buses in parallel and expanding the buses, the information transfer capacity of the ATM bus is doubled. At the same time, since the main bus and the sub bus after the bus expansion have the same bit width as the ATM bus before the expansion, the bus user corresponding to the bus expansion and the bus user corresponding to the bus before expansion can be used together. . Furthermore, by connecting the bus user corresponding to the bus before expansion to the main bus, the effect that the same bus user can transfer information as before the bus expansion is obtained.

The first to fourth embodiments of the present invention have been described above in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments and does not depart from the gist of the present invention. Even if the design of the range is changed, it is included in the present invention.

[0077]

As described above, according to the first aspect of the present invention, the bus arbitration is performed when the expansion head is provided for each cell and each bus user sharing the bus sends a bus use request at the same time. Means arbitrates bus usage requests of a plurality of bus users using the information in the extension header to determine a unique bus user, which the bus user does within the same cell time as the information transfer; Since only specified bus users receive ATM bus data, each bus user is equal and data can be sent from any bus user, and any bus user can receive data. It is possible to obtain an effect that data can be freely transferred between bus users. In addition, information transfer on the bus is
Since the ATM type bus which is performed based on the TM transfer mode is adopted, the affinity with the ATM communication network is very good,
In addition, the minimum data unit can be a fixed length cell unit. As a result, continuous transfer of a specific large amount of data is not permitted, and it is possible to simultaneously transfer information of a plurality of cells while securing different bands, and thus it is possible to easily secure real-time performance. .

According to the second aspect of the invention, the control information for each bus user is transferred from the central control means to the control bus, and the real-time media information or the like is transferred to the ATM bus. Control information and real-time media information can be separated, and mutual influence between both information is avoided. As a result, the amount of information and the type of information that accompanies the computerization of multimedia are increased, real-time performance is ensured, and it is possible to flexibly respond to changes in the scale of data to be processed and the generation pattern, and an optimal information transfer method for multimedia communication is provided. realizable.

Further, according to the invention described in claim 3, for all the bus users who receive the information, the address unique to the bus user who sends the information is preset through the control bus. However, the bus user who is the source of the information is
After the address unique to the bus user is added to the extension header of the cell unit, the cell unit is transmitted from the transmission circuit in the bus user onto the ATM bus. Then, all the bus users who receive the information have a source user address preset in parallel via the control bus and an address given in a cell unit on the ATM bus. When a comparison is performed and the addresses match based on the comparison result, the broadcast communication is performed by receiving the cell unit, so one source bus user among a plurality of bus users connected by the ATM bus. Therefore, it is possible to carry out the broadcast communication to a plurality of receiving source bus users in a short time. Further, it is possible to simplify the processing in both the transmission source and the reception source bus users.

According to the invention described in claim 4, the bus arbitration means permits the bus user who has transmitted the bus use request information added with the higher priority stage to use the bus, and At this time, if a bus use request with the same priority level is sent from another bus user,
Since the bus user and the other bus users are sequentially given permission to use the bus, the bus user who wants to transfer data having a high priority among the bus users preferentially uses the bus to transfer the data. Even when the bus users can be transferred and a bus use request of the same priority stage with a higher priority is transmitted from a plurality of bus users, the bus user concerned
You can use the bus equally.

Further, according to the invention of claim 5,
Since the bus is expanded by installing two ATM buses before expansion and the same bus as the ATM bus in parallel, the information transfer capacity of the ATM bus is doubled, and the main bus and sub-bus after the bus expansion Since each has the same bit width as the ATM bus before expansion, it is possible to use both the bus user corresponding to the bus expansion and the bus user corresponding to the bus before expansion. Furthermore, by connecting the bus user corresponding to the bus before expansion to the main bus, the effect that the same bus user can transfer information as before the bus expansion is obtained.

[Brief description of drawings]

FIG. 1 is an AT according to first and second embodiments of the present invention.
It is a block diagram which shows the structure of an M bus system.

FIG. 2 is an explanatory diagram for explaining an example of a data configuration of one cell unit on an ATM bus in the ATM bus system according to the first, second and fourth embodiments of the present invention.

FIG. 3 is an explanatory diagram illustrating an operation concept of the ATM bus system according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining an operation concept of broadcast communication in the ATM bus system according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an ATM bus system according to a third embodiment of the present invention.

FIG. 6 is a bus user 1 in the ATM bus system.
It is explanatory drawing for demonstrating an example of the change of the ATM bus use state by 0a and 10b.

FIG. 7: Bus user 1 in the ATM bus system
It is the figure which showed an example of the change of the ATM bus use state only by 0b in a time series.

FIG. 8: Bus user 1 in the ATM bus system
FIG. 6 is an explanatory diagram for explaining an example of changes in the ATM bus use state depending on 0c and 10d.

FIG. 9 is an explanatory diagram for explaining an example of a data configuration of one cell unit on an ATM bus in the same ATM bus system according to the third embodiment of the present invention.

FIG. 10 is a block diagram showing the structure of an ATM bus system according to a fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram for explaining the operation of data transfer between bus users corresponding to the expansion in the ATM bus system.

FIG. 12 is an explanatory diagram for explaining an example of changes in bus usage states of a main bus and a sub bus in the same data transfer.

FIG. 13 is an explanatory diagram for explaining an operation when data is transferred from a corresponding bus user after expansion to a corresponding bus user before expansion in the same ATM bus system.

FIG. 14 is an explanatory diagram illustrating an example of changes in bus usage states of a main bus and a sub bus in the same data transfer.

FIG. 15 is an explanatory diagram for explaining an operation of data transfer between bus users corresponding to before expansion in the ATM bus system.

FIG. 16 is a block diagram showing a basic configuration of a conventional information transfer system.

[Explanation of symbols]

10a, 10b, 10c, 10d, 10e, 10f ...
Bus user, 11 ... ATM bus, 11A ... Main bus, 11B ... Sub bus, 12 ... Bus arbitration circuit, 14
a, 14b, 14c, 14d ... Data transfer control circuit,
15a, 15b, 15c, 15d, 15eA, 15e
B, 15fA, 15fB ... Bus controller, 17 ...
... master controller, 18a, 18b, 18c, ...,
18n ... Arbitration circuit, 19 ... Bus permission circuit,
24e, 24f ... Bus usage condition monitoring circuit, 26e, 2
6f ... Used bus selection circuit, 29 ... Synchronous control unit.

Front page continuation (72) Inventor Mitsuko Anai 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Ryoichi Himeno 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Within the Telegraph and Telephone Corporation (72) Inventor Keiju Igarashi 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Inside the Nippon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. An ATM bus system for performing information transfer in an ATM transfer mode based on a fixed-length cell unit on a bus which is an information transfer path, and a bus of the ATM bus for performing the information transfer. An AT that only transfers information in units of one cell at the same time when multiple usage requests occur
In the M bus system, a plurality of bus users connected to the ATM bus and sharing the bus to transfer the information, and a single bus use request from a plurality of bus use requests sent simultaneously by the bus user are transmitted. An ATM bus system comprising bus arbitration means for selecting and determining a bus user who has made a bus use request, wherein the cell unit includes an extension header in addition to ATM bus data including an ATM header. The extension header has bus use request information for the bus user to make the bus use request to the bus arbitration unit, and bus use permission information indicating the only bus user determined by the bus arbitration unit. And user address information for designating a transmission or reception bus user, and the bus arbitration means notifies by the bus use request information. Arbitrating a plurality of bus use requests, and using the bus use permission information, notifies all the bus users of the bus use permission given to only one bus user, and the bus user permits the bus use permission. By determining the information, only the bus user who has received the bus use permission performs the information transfer in units of cells within the same cell time as the transfer of the extension header, and further determines the user address information and applies the corresponding information. An ATM bus system, characterized in that a bus user determined to be an address to receive the ATM bus data. 2. A central control means for controlling processing and information transfer performed by each bus user, and a control for transferring control information for controlling each bus user from the central control means to each bus user. The ATM bus system according to claim 1, further comprising a bus. 3. A bus serving as a source of information, wherein an address peculiar to the bus user who is a sender of the information is preset for all the bus users who are the recipients of the information via the control bus. The user gives an address peculiar to the bus user to the extension header in the cell unit, and then the cell unit is transferred from the transmission circuit in the bus user to the ATM.
All the bus users who send out on the bus and are the information receiving sources are individually and in parallel, and the user address of the transmission source preset through the control bus and the cell unit on the ATM bus are set. 3. The ATM bus system according to claim 2, wherein a broadcast communication is performed by receiving the cell unit when the address is matched based on the comparison result by comparing with the address assigned to the ATM bus system. 4. A plurality of priority stages indicating the priority of the information transfer are provided, and the bus user selects one priority stage from the plurality of priority stages and adds it to the bus use request information, In the bus arbitration means, the bus use permission in a certain priority stage is such that if there is no bus use request in a priority stage higher than the certain priority stage, the bus use request in a priority stage lower than the certain priority stage is ignored. 4. A multi-stage priority bus arbitration for giving a bus use permission so that the bus can be used sequentially and evenly in response to a bus use request of a step and the same priority step as the certain priority step. The ATM bus system according to item 1. 5. The ATM bus is composed of a main bus and a sub bus in which two identical buses are installed in parallel, and the bus arbitration means uses the bus in one data transfer in the main bus and the sub bus. An ATM bus system comprising two master controllers that respectively arbitrate the bus usage requests from a user and a synchronization control unit that synchronizes bus cycles of the main bus and the sub-bus, wherein the bus user comprises: The bus user is connected to the main bus and is provided so as to share the main bus and the sub-bus. The bus user is connected to the main bus and the sub-bus, and when there is data to be transferred, Each bus use request is issued and the bus use is issued from the master controller. A bus controller that performs data transfer when permission is obtained, a bus usage state detection unit that detects an ATM bus usage state, and a single data unit transfer according to bus congestion information by the bus usage state detection unit. And a bus use unit for switching between the bus use and the sub-bus use. The bus user first uses the main bus for one data unit transfer, and the bus use 5. The ATM bus system according to claim 1, wherein the sub-bus is used only when the state detecting means detects that the main bus is congested.