JPH0936844A - Data transmission equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a data transmission device which is less affected by a data error due to noise and can easily cope with an increase in the number of devices on the receiving side. An address generation unit 13 adjusts the data stored in a transmission memory 12 from a control unit 11 that controls data transmission from a transmission side device to each reception side device to the number of reception side devices based on a frame reference signal. The valid information generating unit 15 adds valid information generated corresponding to each receiving side device to the data and transmits the data, and the valid information comparing unit 17 in the receiving side device reads the received data. Valid information is analyzed, and when it is determined to be valid, the data is taken into the internal register 19.

Description

Detailed Description of the Invention

[0001]

This invention relates to transmission error
The present invention relates to a data transmission device that is not easily affected.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, JP-A-5-145526.
FIG. 6 is a block diagram showing a conventional data transmission device disclosed in Japanese Patent Publication No. In the figure, 1a to 1c are measurement circuits provided for each object to be measured, and 2 is each of these measurement circuits 1
It is an output circuit that converts the measurement data of a to 1c into data for serial communication and sends the data continuously twice. Reference numeral 3 is a transmission line through which the data sent from the output circuit 2 is transmitted, and 4 is an interface circuit (hereinafter I / F) for converting the data transmitted through the transmission line 3 into parallel data.
Circuit). 5 is the data received the first time and 2
Reference numeral 6 is a judgment circuit for judging whether or not the data received for the second time coincides with each other. Reference numeral 6 is a processing circuit which operates according to the data output when the judgment circuit 5 detects the coincidence of the both data. Further, in the determination circuit 5, 5a is a holding circuit for holding the first received data, and 5b is a holding circuit.
A comparison circuit for comparing the data received for the first time and the data for the first time held in the holding circuit 5a.
It is a latch circuit that latches the data received the next time and outputs the latched data to the processing circuit 6 when the comparison circuit 5b detects a match between the two.

Next, the operation will be described. In the device on the transmission side, each of the measurement circuits 1a to 1c measures the corresponding measurement object and sends the measurement data to the output circuit 2. When the output circuit 2 receives the measurement data from each of the measurement circuits 1a to 1c, the output circuit 2 converts the measurement data into data for serial communication, and the transmission line 3 is continuously transmitted twice each.
To the receiving side device. In the receiving side device, the data sent via the transmission path 3 is received by the I / F circuit 4, converted into parallel data and input to the determination circuit 5. In the judgment circuit 5, the first received data out of the data continuously sent twice is first held by the holding circuit 5.
a. Next, when the second data is received, the latch circuit 5c latches it, and the comparison circuit 5b compares the second received data with the first data held in the holding circuit 5a. When the comparison circuit 5b detects a match between the two, it outputs a signal to the latch circuit 5c to output the latched data to the processing circuit 6. On the other hand, the comparison circuit 5b
If a mismatch between the two is detected by the above, it is considered that there is an influence of noise or the like in the transmission process of the data received at the first time or the second time, the data is invalidated, and it is output to the processing circuit 6. Prohibit to do.

Note that, as other literatures describing the technique related to such a conventional data transmission apparatus, for example, Japanese Patent Application Laid-Open No. 6-14012 and Japanese Patent Application Laid-Open No. 5-2 are disclosed.
27134, JP-A-4-104545 and the like.

[0005]

Since the conventional data transmission apparatus is constructed as described above, when the amount of data to be transmitted to the receiving side apparatus increases, the holding circuit 5a and the latch necessary for comparing the data are latched. Circuit 5c and comparison circuit 5
When it is necessary to increase b and the like, and when there are a plurality of receiving side devices, the load on the transmitting side device increases as the number of receiving side devices increases. There has been a problem that it is difficult to deal with the increase in the number with a simple circuit change.

The present invention has been made in order to solve the above-mentioned problems, and has little influence on noise and malfunction, and can easily cope with an increase in the number of receiving side devices. The purpose is to obtain the device.

[0007]

According to a first aspect of the present invention, there is provided a data transmission apparatus comprising: a control unit for integrally controlling data transmission from a transmission side apparatus to a plurality of reception side apparatuses; The data to be transmitted to the device is stored in the transmission memory, and the valid information is added to the data read from the transmission memory by the address generation unit according to the memory address repeatedly generated according to the number of the reception side devices based on the frame reference signal. Effective information for individually identifying the receiving side device generated by the generation unit is added and transmitted, and the receiving side device analyzes the effective information of the received data in the effective information comparison unit and determines that it is effective. In the case of being processed, the data is taken into the internal register.

Further, in the data transmission apparatus according to the present invention as defined in claim 2, the address generation section has a retransmission circuit for shortening the repeating interval of the generated memory address for the specific receiving side apparatus. It was made.

Further, in the data transmission apparatus according to the present invention as defined in claim 3, the auxiliary memory for transmitting the data collectively is a transmission memory for storing the data to be transmitted from the transmission side apparatus to the reception side apparatus. And the control unit.

Further, in the data transmission apparatus according to the present invention as defined in claim 4, the transmitted data is returned from the reception side apparatus to the transmission side apparatus, and the return data and the transmission data are compared by the comparison unit, and they do not match. When the packet is detected, the control unit requests the receiving side device to retransmit the data, and in accordance with the pattern for retransmitting the data created by the retransmitting circuit based on the retransmit request, the control unit transmits the transmission memory. The memory address of is generated.

Further, in the data transmission device according to the invention described in claim 5, the result of the comparison by the comparison unit is directly input to the retransmission circuit, and when the comparison result does not match, the data retransmission created by the retransmission circuit is performed. The memory address of the transmission memory is generated from the address generator according to the pattern for.

Further, in the data transmitting apparatus according to the invention described in claim 6, when the control unit repeatedly requests data retransmission to the same receiving side apparatus, the address generating section instructs the receiving side apparatus to the receiving side apparatus. On the other hand, the receiving side device, which has received the notification, generates the initial setting data in the initial setting data generating unit, sets it in the internal register, and notifies the alarm generating unit from the alarm generating unit. It is something that is done.

[0013]

In the data transmitting apparatus according to the present invention, the memory address for reading the data to be transmitted to each receiving side device, which is stored in the transmitting memory by the control unit, is used as the frame reference signal by the address generating unit. Based on the number of receiving devices, the information is repeatedly generated in order, and effective information for individually identifying the receiving devices generated by the effective information generating unit is added to the read data according to the memory address, By periodically and repeatedly transmitting to each receiving device, even if data error occurs due to noise on the transmission path, it is possible to reduce the effect and increase the number of receiving devices. On the other hand, it will be possible to deal with the problem simply by increasing the pattern of valid information.

Further, the retransmission circuit in the invention described in claim 2 has an effect on the system by shortening the repeat interval of the memory address generated by the address generation unit for a specific receiving side device. It is possible to transmit data in a shorter cycle to a receiving side device having a large number.

Further, in the auxiliary memory according to the third aspect of the invention, data to be sent to a plurality of receiving side devices at a time is written by the control unit, and the data is transferred to the transmitting memory to receive each of the data. It is possible to complete the transmission to the side device within a fixed period.

Further, the control section in the invention according to claim 4 resends the data to the receiving side apparatus when the comparing section which compares the data returned by the receiving side apparatus with the transmission data detects a mismatch. A request is made to the address generation unit, and the address generation unit generates a memory address of the transmission memory according to the pattern created by the retransmission circuit based on the retransmission request, so that the reception side device in which a transmission error due to noise has occurred is generated. On the other hand, the data is retransmitted immediately.

Further, the address generating section in the invention according to claim 5 is such that when the comparing section for comparing the data returned by the receiving side apparatus with the transmitted data detects the non-coincidence, the re-transmission circuit prepares the reception. By generating the memory address of the transmission memory according to the pattern for retransmitting data to the receiving side device, the receiving side device in which a transmission error due to noise has occurred can immediately receive the data without increasing the load on the control unit. It is possible to re-transmit.

Further, in the initialization data generating section in the invention described in claim 6, when the request for data retransmission to the same receiving side apparatus is repeatedly generated from the control section, the abnormality generated by the address generating section is generated. When the notification of the occurrence of is generated, the initial setting data is created and set in the internal register to prevent inadvertent control of the peripheral circuits in the event of an abnormality, and the alarm notification unit receives the notification. By notifying that the alarm has occurred, the receiving side can confirm the occurrence of the abnormal state.

[0019]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a data transmission device according to a first embodiment of the present invention. In the figure, reference numeral 11 denotes a control unit that is arranged in the transmission side device and integrally controls the transmission of data from the transmission side device to the plurality of reception side devices (A, B, ..., N). Reference numeral 12 denotes a transmission memory for storing data (control information) transmitted from the transmission side device to each reception side device by the control unit 11.
It is a port memory. Reference numeral 13 is an address generation unit that repeatedly and sequentially generates a memory address associated with each receiving side device of the 2-port memory 12, in accordance with the reference frame signal, and 14 is the 2-port memory 12
A parallel / serial data conversion unit for converting the data read from the parallel data to the serial data, 15 is added to the data transmitted to the receiving side device,
This is a valid information generation unit that generates valid information for individually identifying each of the receiving side devices in association with a memory address generated by the address generation unit 13.

Reference numeral 16 is a serial / parallel data conversion unit for converting the data transmitted from the transmission side device into parallel data, and 17 is the data (control information) transmitted from the transmission side device. The effective information comparison unit compares the added effective information with the effective information assigned to the self-reception side device to determine whether to take in the data. Reference numeral 18 denotes a timing generation unit that generates a timing for comparing valid information in the valid information comparison unit 17. Reference numeral 19 is an internal register for taking in the control information portion of the data converted by the serial / parallel data conversion unit 16 when the effective information comparison unit 17 determines that the effective information is effective, and 20 is the It is a peripheral circuit controlled by the control information taken into the internal register 20.

Reference numeral 21 is an in-apparatus reference signal generating section for generating a reference signal in the data transmission apparatus, and 22 is supplied from the in-apparatus reference signal generating section 21 to the transmitting side apparatus and each receiving side apparatus. A frame reference signal serving as a transmission reference of serial data, and 23 is a serial synchronization clock signal used for synchronization when transmitting serial data. Reference numeral 24 is serial transmission data transmitted from the transmission side device to each reception side device via a transmission line connecting the transmission side device and each reception side device.

Next, the operation will be described. The control unit 11 arranged in the transmission side device is configured to operate the peripheral circuit 20 of each reception side device.
The data (control information) for controlling is sequentially set in the 2-port memory 12. In the address generation unit 13, this 2
The memory address of the data stored in the port memory 12 to be transmitted to the receiving side device is repeatedly generated in order according to the reference frame signal, and the address is set in the 2-port memory 12. Data is read from the set address from the 2-port memory 12 and sent to the parallel / serial data converter 14.

FIG. 2 is a timing chart showing the time relationship of each signal in the data transmission apparatus according to the present invention. FIG. 2A is a frame reference signal 22 generated by the in-apparatus reference signal generator 21, The figure (b) shows the serial synchronous clock signal 23, and the figure (c) shows the serial transmission data 24 transmitted from the transmitting side device to each receiving side device. Note that, in FIG. 2, for simplification, only serial transmission data to the three reception side devices A to C are shown, and notations are omitted for the other serial transmission data to the reception side devices D to N. ing. The generation of addresses in the address generator 13 will be described below with reference to the timing chart of FIG.

The address generator 13 uses the frame reference signal 22 and the serial synchronization clock signal 23 sent from the in-apparatus reference signal generator 21 to generate the transmission timing of the data to be transmitted to the receiving side apparatus. At that time, in order to time-division-multiplex the data to be transmitted from the transmission side device to each of the plurality of reception side devices, the change (for example, the leading edge of the pulse) of the frame reference signal 22 is counted and the data is transmitted. To determine the time phase of the receiving device. Then, the address generator 13 sequentially and sequentially generates the memory address of the 2-port memory 12 determined in correspondence with the time phase. In accordance with the memory address generated by the address generator 13, the 2-port memory 12
Is accessed and the data (control information) stored at the address is input to the parallel / serial data conversion unit 14.

On the other hand, in the effective information generator 15, in synchronization with the frame reference signal 22 from the in-apparatus reference signal generator 21, the effective information assigned to each of the receiving side devices is repeatedly and sequentially generated, and To the parallel / serial data converter 14. At this time, the valid information generated by the valid information generating unit 15 is the 2-port memory 12 corresponding to the memory address generated by the address generating unit 13.
Is assigned to the receiving side device to which the data stored at the address is to be transmitted. The parallel / serial data converter 14 adds the valid information generated by the valid information generator 15 to the control information read from the 2-port memory 12 and converts the control information into serial data. Therefore, every time the frame reference signal 22 is generated from the in-device reference signal generator 21, the 2-port memory 12
, Are sequentially read out to the respective receiving side devices A, B, C, ..., And each of A, B, C ,. Corresponding effective information for identifying the receiving side device is added, and the parallel / serial data conversion unit 14 sends out as serial transmission data 24 as shown in FIG.

In each receiving side device, the serial transmission data 24 transmitted on this transmission line is converted by the serial / parallel data conversion unit 16, the control information portion is sent to the internal register 19, and the effective information portion is sent. It is sent to the valid information comparison unit 17. On the other hand, the timing generation section 18 generates the timing for comparing the valid information in the valid information comparison section 17 in synchronization with the frame reference signal 22 given from the in-apparatus reference signal generation section 21. The valid information comparison unit 17 compares the valid information from the serial / parallel data conversion unit 16 with the valid information assigned to the self-reception side device at the timing generated by the timing generation unit 18. As a result, if the two match, the valid information comparison unit 17 sends a signal to the internal register 19 to cause the serial / parallel data conversion unit 16 to fetch the control information. The control information fetched by the internal register 19 is set in the peripheral circuit 20, and the peripheral circuit 2
0 executes a predetermined control operation based on it.

That is, according to the first frame reference signal 22, the address generator 13 generates a memory address corresponding to the receiving device A, and the data read from the address of the 2-port memory 12 is added to the receiving device. A valid information of A is added and sent to each receiving apparatus, and the valid information is judged to be valid, that is, receiving apparatus A
The data is taken in only at. When the next frame reference signal 22 is generated, the address generator 13
Advances a counter to generate a memory address corresponding to the receiving side device B, adds valid information of the receiving side device B to the data read from the address of the two-port memory 12, and adds it to each receiving side device. The data is taken in only by the receiving side device B which is sent and whose validity information is judged to be valid. Thereafter, the receiving side devices C, D, and
... is also imported. Therefore, even if the number of receiving side devices is increased, if the pattern of the effective information is increased accordingly, it is possible to easily cope with it without causing a large circuit change.

In addition, the address generator 13 resets the count value to the initial value when the number of frame reference signals has been increased by the number of receiving side devices, thereby sequentially repeating the memory address corresponding to each receiving side device. Can occur. Therefore, even if the same data is not set by the control unit 11 one by one, the same data is read from the 2-port memory 12 in a predetermined cycle and retransmitted to each receiving side device. Therefore, even if a part of the serial transmission data 24 is changed due to external noise or the like, the correct serial transmission data 24 is sent out again when the frame reference signal 22 makes a round corresponding to the number of the receiving side devices. The influence on data errors can be reduced. When it becomes necessary to send new data (control information) to the receiving side device, the control unit 11 sets the data to be sent to the address corresponding to the receiving side device in the 2-port memory 12 each time. do it.

Example 2. 3 is a block diagram showing a data transmission device according to a second embodiment of the present invention. In the drawing, 11 is a control unit, 12 is a 2-port memory as a transmission memory, 14 is a parallel / serial data conversion unit, and 16 is a parallel / serial data conversion unit.
Is a serial / parallel data conversion unit, 17 is a valid information comparison unit, 18 is a timing generation unit, 19 is an internal register,
20 is a peripheral circuit, 21 is a reference signal generator in the apparatus, 22 is a frame reference signal, 23 is a serial synchronization clock signal,
Reference numeral 24 represents serial transmission data, which are the same as or equivalent to those in the first embodiment denoted by the same reference numerals in FIG. 1, and therefore detailed description thereof will be omitted.

Further, reference numeral 25 is a retransmission circuit for shortening the repeat interval of the memory address which is repeatedly generated with respect to the one corresponding to the specific receiver device, compared with the interval of other normal receiver circuits. , 26 are address generators different from those of the first embodiment denoted by reference numeral 13 in FIG. 1 in that the resending circuit 25 is included. Reference numeral 27 denotes a valid information generating unit that generates valid information for identifying each receiving side device in association with a memory address. In this case, the address generating unit 26 controls the specific receiving side device according to the control of the retransmission circuit 25. Since the corresponding memory address is generated in a short cycle, the valid information generation unit 27 also receives the signal from the retransmission circuit 25 and generates the valid information of the receiving side device accordingly.

Next, the operation will be described. Resending circuit 25
Monitors the memory address generation interval corresponding to a specific receiving side device whose memory address generation repetition interval is set shorter than other receiving side devices, and at that interval, the specific receiving side device is monitored. The address generation unit 26 is instructed to generate a corresponding memory address, and the address generation unit 26
Generates a memory address according to the instruction. This memory address is generated, for example, as follows. That is, the address generator 26 normally counts the frame reference signal 22, associates the count value with each of other general receiving side devices, and outputs the memory address associated with each receiving side device. It is generated repeatedly in order. When the retransmitting circuit 25 detects that the short repetition interval given to the specific receiving side device has elapsed, it causes the address generating unit 26 to stop counting the frame reference signal 22 and cause the specific receiving side device to stop counting. The generation of the associated memory address is performed. After that, the address generation unit 26 returns to the normal processing, restarts the counting of the frame reference signal 22, and continues the generation of the memory address for the other receiving side device.

Similarly to the address generating unit 26, the valid information generating unit 27 normally repeatedly generates valid information associated with each of the other receiving side devices in order, and a specific receiving side is generated. When a short repeat interval given to the device has passed, when the resending circuit 25 that detects it has received a signal sent from it, the generation of valid information associated with the other receiving device is temporarily stopped, and Generate valid information associated with a particular receiving device. After that, the generation of the valid signal of the other receiving side device which has been stopped is restarted. The other operations are the same as in the case of the first embodiment, and the description thereof is omitted.

As a result, it becomes possible to send data to a specific receiving side device at a shorter interval than other normal receiving side devices, which may greatly affect the system of this data transmission device. By applying the second embodiment to a high receiving side device, it is possible to more surely suppress the influence from external noise.

Example 3. 4 is a block diagram showing a data transmission device according to a third embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 3 and their explanations are omitted. In the figure, 28 is a control unit 30 corresponding to the control unit 11 in each of the above embodiments, and a 2-port memory 12 as a transmission memory.
It is a two-port memory as an auxiliary memory that is arranged between and and sends the data set by the control unit 30 all together. Reference numeral 2 in FIG. 3 indicates that 29 has a function of generating a memory address when the data stored in the 2-port memory 28 is sent to the 2-port memory 12.
The address generator is different from that designated by 6, and the controller 30 has a function of controlling the sending of the data stored in the 2-port memory 28 to the 2-port memory 12 in the address generator 29. This is different from the control unit 11 in the point.

Next, the operation will be described. As shown in FIG. 4, an additional 2 units are provided between the control unit 30 and the 2-port memory 12.
By providing the port memory 28, the control unit 30 can collectively write the same data (control information) to be transmitted to a plurality of receiving side devices at one time. That is,
When the setting of the data in the 2-port memory 28 is completed, the control unit 30 controls the address generating unit 29 to instruct the data set in the 2-port memory 28 to be sent to the 2-port memory 12. As a result, the same data transmitted to a plurality of receiving side devices is set in each of the corresponding addresses of the 2-port memory 12. Thus, 2
The operation after the data is set in the port memory 12 proceeds in the same manner as in each of the above-mentioned embodiments, and the description thereof will be omitted.

As described above, by collectively setting the data written in the two-port memory 28 by the control unit 30 in the two-port memory 12, it is possible to prevent a plurality of receiving side devices from affecting each other. Even if the control unit 30 does not consider the transmission timings one by one, if the transmission control instruction is given to the address generation unit 29 at the time when the setting of the data in the two-port memory 28 is completed, the frame reference signal is cycled. In the meantime, the setting of the same data is completed in all the desired receiving side devices. Therefore, it is possible to prevent an extra state from occurring when the control setting state changes, and it is possible to improve the stability of the data transmission device when the setting is changed.

Embodiment 4 FIG. FIG. 5 is a block diagram showing a data transmission device according to a fourth embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 4 and their explanations are omitted. In the figure, 31 is a peripheral circuit different from that indicated by reference numeral 20 in FIG. 4 in that it has a function of returning the data set in the internal register 19 to the transmitting side device, and 32 is A return register for storing the data to be returned, 33 has a function of generating a transmission timing of the data stored in the return register 32, and is different in timing from that denoted by reference numeral 18 in FIG. It is a generating part. Reference numeral 34 is a parallel / serial data converter for converting the data output from the return register 32 from parallel data to serial data, and 35 is a serial / parallel converter for converting the data returned from the receiving side device from serial data to parallel data. It is a data conversion unit.

Reference numeral 36 holds the data to be transmitted to the receiving side apparatus, and compares the data with the data converted by the serial / parallel data converting section 35 and returned from the receiving side apparatus. Reference numeral 30 in FIG. 4 is a comparison unit, which has a function of requesting the receiving side device to retransmit data when a mismatch is detected as a result of the comparison in the comparison unit 36. This is a control unit different from the one marked with. 38 is a resending circuit different from that designated by reference numeral 25 in FIG. 4 in that it has a function of creating a pattern for resending data to the receiving side device in accordance with the data resending request from the control section 37. Yes, 39 is an address generator different from that designated by reference numeral 29 in FIG. 4 in that it has a function of generating a memory address of the two-port memory 12 in accordance with the pattern created by the retransmission circuit 38.

40 is serial return data returned from the receiving side device to the transmitting side device via a transmission line connecting the transmitting side device and each receiving side device, and 41 is multiplexed with the serial returning data 40. This is a two-port memory in which failure information of the receiving side device sent from the receiving side device to the transmitting side device is written, and the data is taken in by the control unit 37.

Next, the operation will be described. The operation until the serial transmission data 24 from the transmission side device to the reception side device is set in the internal register 19 of the reception side device is the same as in each of the above embodiments. After that, the peripheral circuit 31 fetches the control information set in the internal register 19 to start the control operation and sends the control signal to the return register 32. On the other hand, the timing generation unit 33 generates the transmission timing of the setting data in the return register 32 in synchronization with the frame reference signal 22 given from the in-apparatus reference signal generation unit 21. The return register 32 matches the timing generated by the timing generator 33 with the parallel / serial data converter 34.
Send data to. The parallel / serial data converter 34 converts the data from the return register 32 into serial data, and sends it out as serial return data 40 on the transmission path.

This serial transmission data 40 is transmitted to the transmission side device on the transmission path and input to the serial / parallel data conversion section 35 of the transmission side device. The serial / parallel data conversion unit 35 converts the data into parallel data and then inputs the parallel data to the comparison unit 36. The comparison unit 36 holds the data read from the two-port memory 12 and transmitted to the parallel / serial data conversion unit 14 for transmission to the reception side device, and returns the data and the reception side device. Lever serial / parallel data converter 3
The data converted in step 5 is compared. As a result of the comparison, if the two match, it is determined that the data set in the internal register 19 of the receiving side device has no error, and thereafter no processing is performed on the data. However, if they do not match, the control unit 37 is notified that an error has occurred in the setting data of the internal register 19 of the receiving side device.

The control unit 37 controls the address generation unit 39 to retransmit the data to the receiving side device in order to promptly retransmit the data to the receiving side device in which an error in the transmission data has occurred. The resending circuit 38 of the address generating unit 39, which has received the request for resending the data, carries out the processing of resetting the repetition of the counter carried out in the second embodiment to the address of the receiving side device for resending the data and sending it out. After the process of retransmission to the receiving side device is completed, the normal repetitive process is resumed. If an error occurs again after that, the data will be retransmitted in the next frame, and the data can be retransmitted sequentially and repeatedly. At this time, by performing a process of alternately setting the counter that determines the order of the receiving side device and the value of the counter for performing the retransmission process, the receiving side device that retransmits the data and the next receiving side device Transmission data can be sent to each other. As described above, with the above configuration, the data is promptly retransmitted to the receiving side device in which a transmission error due to noise or the like has occurred, so that it is possible to minimize malfunction due to noise.

In the fourth embodiment described above, the return register 32 is provided in the receiving side device, but the control information from the internal register 19 to the peripheral circuit 31 is returned to the parallel / serial data converter 34. By outputting, the internal register 19 and the return register 32
The same effect can be obtained as in the above embodiment even if the return register 32 is omitted.

Furthermore, in the above-mentioned fourth embodiment, the one having the two-port memory 41 is shown.
Is not indispensable for the operation of the invention. That is, normally, data other than control information, for example, failure information of the receiving side device may be multiplexed and transmitted to the serial return data 40 from the receiving side device in the data transmission device. In the fourth embodiment, the 2-port memory 41 is provided so that such information can be fetched by the control unit 37.

Embodiment 5 FIG. FIG. 6 is a block diagram showing a data transmission device according to a fifth embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 5 and their explanations are omitted. In the figure, reference numeral 42 indicates the data transmitted to the receiving side device and the data returned and returned by the receiving side device when a mismatch is detected in the comparing part 36, the data concerned is sent to the receiving side device. Is a retransmitting circuit that creates a pattern for retransmitting
5 has the function of generating the memory address of the 2-port memory 12 in accordance with the pattern created by
This is an address generator different from the one marked with 9. In the fifth embodiment, unlike the case of the fourth embodiment, the comparison result of the comparison unit 36 is directly applied to the retransmission circuit 42 of the address generation unit 43. A control unit 3 equivalent to that of the third embodiment shown in FIG.
0 is used.

Next, the operation will be described. The serial transmission data 24 from the transmission side device to the reception side device is set in the internal register 19 of the reception side device, and the peripheral circuit 31
The operation until the data is fetched by the device, is set in the return register 34, is returned to the transmitting side device as the serial returning data 40, and is compared with the data transmitted to the receiving side device in the comparing section 36. It is similar to the case. As a result of the comparison in the comparison unit 36, if they match,
It is determined that the data set in the internal register 19 of the receiving side device has no error, and thereafter, no processing is performed on the data. However, if they do not match, the retransmission circuit 42 of the address generator 43
Is notified that an error has occurred in the setting data of the internal register 19 of the receiving side device. The resending circuit 42 of the address generating unit 43, which receives the notification from the comparing unit 36, uses the second embodiment.
Then, the counter is repeatedly set in the address of the receiving side device that retransmits the data, and is sent out. Then, the same operation as in the fourth embodiment is performed. With this configuration, the data can be promptly retransmitted to the receiving side device in which a transmission error due to noise or the like has occurred, without increasing the processing load of the control unit 30.

Embodiment 6 FIG. FIG. 7 is a block diagram showing a data transmission device according to a sixth embodiment of the present invention. Corresponding parts are designated by the same reference numerals as those in FIG. 5 and their explanations are omitted. In the figure, 44 is provided with a function for notifying the receiving side device of the occurrence of an abnormal state when the control unit 37 repeatedly requests data retransmission to the same receiving side device. , An address generator different from that indicated by reference numeral 39 in FIG. 45 is this address generator 4
4 is an initial setting data generation unit that creates initial setting data when it receives an abnormality notification signal from No. 4, and sets the created initial setting data in an internal register to be described later. This is an internal register different from that indicated by reference numeral 19 in FIG. 5 in that data can be set. Reference numeral 47 denotes an alarm notification unit that receives an abnormality notification signal generated by the address generation unit 44 and generates an alarm notification. Reference numeral 48 indicates from the address generation unit 44 of the transmission side device to the initialization data generation unit 4 of each transmission side device.
5 and an alarm notification signal sent to the alarm notification unit 47.

Next, the operation will be described. The comparison unit 36 compares the data returned from the receiving-side device with the data transmitted to the receiving-side device, and if a mismatch is detected, the control unit 37 notifies the address generating unit 44. The operation up to the control of the data retransmission request to the receiving side device is the same as in the case of the above-mentioned fourth embodiment, and therefore its explanation is omitted. The address generation unit 44 causes a failure or a reception on the transmission line when the data retransmission request generated by the control unit 37 based on the comparison result of the comparison unit 36 is repeatedly generated continuously for a specific receiving side device for some reason. An abnormality notifying signal 48 for notifying the occurrence of an abnormal state when it is judged as an abnormality of the side device is generated and sent to the receiving side device. In the receiving side device which has received this abnormality notification signal 48, the initial setting data generator 45 generates the initial setting data and sends it to the internal register 4
Set to 6. As a result, even if the receiving side device cannot normally receive the data (control information) from the transmitting side device, the peripheral circuit 31 operates by taking in the initial setting data. The careless control will not be applied. In addition, in the receiving side device, when the abnormality notification signal 48 is received, the alarm notification section 47 is activated to generate an alarm such as lighting of a lamp or ringing of a buzzer. This allows the receiving side to quickly recognize the occurrence of the abnormal state.

[0049]

As described above, according to the first aspect of the present invention, each reception side stored in the transmission memory by the control unit that controls the transmission of data from the transmission side apparatus to each reception side apparatus. The address generator reads the data to be transmitted to the device according to the memory address that is repeatedly generated according to the number of the receiving side devices based on the frame reference signal, and the valid information generating part reads the valid information assigned to the receiving side device. When it is generated, it is added to the data read from the transmission memory and transmitted, and the receiving side device analyzes the valid information of the received data in the valid information comparing section, and only when it is determined to be valid, the Since the data is stored in the internal register, the same data is sent from the transmission memory in a predetermined cycle without the need to set the same data from the controller. Even if a part of the serial transmission data changes due to external noise, etc., it is re-transmitted to each receiving side device, and if the frame reference signal makes one cycle for the number of receiving side devices, the correct serial Not only can transmission data be sent out and the effect of noise on data errors can be minimized, but even if the number of receiving side devices increases, the pattern of this valid information should be increased accordingly. In this case, there is an effect that a data transmission device can be obtained which can be easily dealt with without requiring a drastic circuit change.

According to the second aspect of the present invention, the address generating section is provided with a retransmission circuit for shortening the repeating interval of the generated memory address for a specific receiving side device. Therefore, it becomes possible to send data to a specific receiving side device at a shorter interval than other normal receiving side devices, and to a receiving side device that is likely to have a great influence on the system of this data transmission device. On the other hand, if the data transmission interval is shortened, it is possible to further suppress the influence of external noise on the receiving side device, and it is possible to realize a more reliable data transmission device.

According to the third aspect of the present invention, the data is collectively transmitted between the control unit and the transmission memory for storing the data to be transmitted from the transmission side device to the reception side device. Since the auxiliary memory is arranged, the frame reference signal goes round even if the control unit does not consider the transmission timings one by one even for the control in which a plurality of receiving side devices influence each other. Since the setting of the same data is completed in all the desired receiving side devices in the meantime, it is possible to suppress the occurrence of an extra state when the control setting state changes, and the stability of the data transmission device when the setting is changed. There is an effect that it is possible to improve.

According to the fourth aspect of the present invention, the comparing section compares the transmitted data with the data returned and returned by the receiving side apparatus, and the control section determines that the comparison results do not match. A request to retransmit data is made to the receiving side device, and the address generation unit generates the memory address of the transmission memory according to the pattern for retransmitting the data created by the retransmission circuit based on the retransmission request. Since the configuration is adopted, data is promptly retransmitted to a receiving side device in which a transmission error due to noise or the like has occurred, and it is possible to minimize malfunction due to noise.

According to the invention described in claim 5, the result of the comparison by the comparing section is directly input to the resending circuit of the address generating section, and the resending circuit is created when the comparison results do not match. According to the pattern for data retransmission,
Since the memory address of the transmission memory is generated from the address generation unit, data is promptly retransmitted to the receiving side device in which a transmission error due to noise or the like has occurred without increasing the processing load of the control unit. There is an effect that a possible data transmission device can be obtained.

Further, according to the invention described in claim 6, when the control section repeatedly requests data retransmission to the same receiving side apparatus, the address generating section causes an abnormality in the receiving side apparatus. In the receiving side device that has received the notification, the initial setting data generation unit creates the initial setting data and sets it in the internal register, and the alarm notification unit notifies the occurrence of the alarm. Therefore, even if the device on the receiving side cannot normally receive data from the device on the transmitting side, the peripheral circuit operates by fetching this initial setting data, so that careless control may be applied to the peripheral circuit. The effect is that the reception side can promptly recognize the occurrence of an abnormal state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data transmission device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a time relationship of each signal in the above embodiment.

FIG. 3 is a block diagram showing a data transmission device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a data transmission device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a data transmission device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a data transmission device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a data transmission device according to a sixth embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional data transmission device.

[Explanation of symbols]

11, 30, 37 Control unit, 12 2-port memory (transmission memory), 13, 26, 29, 39, 43, 44 Address generation unit, 15, 27 Effective information generation unit, 17 Effective information comparison unit, 18, 33 Timing Generator, 19,
46 internal register, 22 frame reference signal, 25,
38, 42 resending circuit, 28 2 port memory (auxiliary memory), 36 comparing section, 47 alarm notifying section.

Claims (6)

[Claims] 1. A transmission memory for storing data to be transmitted from a transmission side device to each reception side device, and a memory address of the transmission memory respectively associated with the reception side device, according to a frame reference signal. An address generator that is repeatedly generated in order, and valid information that is added to the transmitted data and that individually identifies the receiving side device, and a valid information generator that is generated in association with the memory address. A valid information comparing unit that analyzes the valid information added to the received data and determines whether to fetch the data, and a timing generating unit that generates a timing of data comparison in the valid information comparing unit. An internal register for fetching the data determined to be valid by the validity information comparing unit, and each receiving side device from the transmitting side device. A data transmission device including a control unit for controlling overall data transmission to a storage device. 2. The address generating section is provided with a resending circuit for shortening a repeating interval of memory addresses that are repeatedly generated for a specific receiving side device. 1. The data transmission device according to 1. 3. An auxiliary memory for collectively sending the data is provided between the control unit and the transmission memory for storing data to be transmitted from the transmission side device to the reception side device. The data transmission device according to claim 1 or 2, characterized in that. 4. A comparison unit is provided for comparing data returned based on the data received by the reception side device and data transmitted to the reception side device, and the control unit causes a mismatch in the comparison unit. Is provided with a function of requesting the device on the receiving side to retransmit the data, and the address generation unit has a retransmission circuit that creates a pattern for the retransmission based on the request from the control unit. 4. The data transmission device according to claim 1, wherein the memory address is generated according to the pattern created by the retransmission circuit. 5. A comparison unit is provided for comparing the data returned based on the data received by the reception side device with the data transmitted to the reception side device, and the address generation unit is configured to enable the address generation unit to It is characterized in that it has a resending circuit that creates a pattern for resending the data to the receiving side device in which a mismatch is detected, and generates a memory address according to the pattern created by the resending circuit. The data transmission device according to any one of claims 1 to 3. 6. The address generating unit has a function of notifying the receiving side device of the occurrence of an abnormality when the control unit repeatedly requests data retransmission to the same receiving side device. An initialization data generation unit that creates initial setting data upon receiving the notification of the occurrence of the abnormality and sets it in the internal register; and an alarm notification unit that notifies the occurrence of the alarm upon receiving the notification of the occurrence of the abnormality The data transmission device according to claim 4 or 5, further comprising: