JPH09306174A - Dynamic SRAM - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To provide an SRAM capable of operating at high speed with low power consumption
I will provide a. A memory cell (CEL11) including a flip-flop for information storage and a first capacitor section that supplies a circuit voltage Vdd to Vss to the flip-flop so that the stored content is held; and a bit line (BL1) to which the memory cell is connected. A second capacitor unit CL1 + CL2 selectively connected to / BL1 * and charged to the circuit voltage; first intermittent charging means Q11 + Q12 for intermittently charging the second capacitor unit CL1 + CL2 to the circuit voltage at a first timing.
+ RE0; second capacitor portion CL at the second timing
Bit line BL1 using the voltage charged in 1 + CL2
Second intermittent charging means Q13 + Q for intermittently charging / BL1 *
14 + RE1; bit line BL1 / at the third timing
A third intermittent charging means Q3 + Q4 + DW10 for intermittently charging the first capacitor unit using the charging voltage of BL1 * is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device that involves a refresh operation to maintain stored information.

[0002]

2. Description of the Related Art Currently, mainstream semiconductor memory devices are a dynamic memory (hereinafter referred to as DRAM) which requires refreshing to maintain stored contents and a static memory (hereinafter referred to as SRAM) which does not require refreshed to maintain stored contents. It can be roughly divided.

The DRAM retains its stored contents by charging a very small capacity memory cell capacitor. If the electric charges (stored contents) charged / stored in the memory cell capacitor are left as they are, they will disappear within a short time due to a leak current inside the memory chip. In order to prevent the loss of the stored contents, in the DRAM, the stored contents are once read out from the individual memory cells with a relatively short cycle (usually within 10 ms) in a period when there is no external memory access (read / write). The read contents are written back to the same memory cell. The read / write-back operation of the stored contents repeated in this short cycle,
This is called a DRAM refresh operation.

Since the refresh operation in the DRAM is repeated charging / discharging with respect to the total capacitance of all memory cell capacitors, the power consumption of the refresh operation is large.

On the other hand, the SRAM retains its stored contents depending on the operating state of the flip-flop which is always in the power supply state (one of the pair of cross-connected transistors is on or off). The SRAM does not need a refresh operation (read / write back operation of stored contents) like that of a DRAM, and has a minimum power supply current required to maintain a circuit operation state of a flip-flop (it can be suppressed to almost a leak current level). Only possible).

However, in order to obtain the above-mentioned feature of the SRAM "consumes almost no power supply current", the DC resistance value of the drain load circuit of the flip-flop needs to be extremely large. For example, S operating at power supply voltage + 3V
To keep the current consumption per cell of RAM below 1 nA (nanoampere), the drain load resistance is 3000M.
Must be greater than Ω.

[0007]

Generally, the high resistance load resistance (a pair of flip-flop load resistances) of SRAM is formed of low impurity concentration polysilicon. However, since this polysilicon high resistance has a high temperature dependency, at a high temperature, the resistance value becomes small and the power consumption current increases. On the other hand, at low temperatures, the value of the pair of flip-flop load resistors does not always balance and increases,
The balance of the operational states of the flip-flop circuit is lost, and an error easily occurs in the stored contents. To prevent this, keep the flip-flop load current low and allow the flip-flop circuit current to flow to some extent so that the on / off state of the flip-flop does not change even if the load resistance balance is slightly disturbed. There is a need.

After all, in an SRAM using a high resistance load resistor, there is a trade-off relationship between low current consumption and low error occurrence rate.

An object of the present invention is to provide a new type SRAM which can operate at high speed with a power consumption current as low as that of an ordinary SRAM and yet is less likely to cause an error.

[0010]

To achieve the above object, in the SRAM of the first invention, a plurality of pairs of bit lines (B
In a memory device (FIG. 1) having a matrix structure in which a plurality of memory cells (CELmn) are arranged at intersections of Ln / BLn *) and a plurality of word lines (WLn), each of the memory cells (for example, CEL11) is A flip-flop circuit (Q1 + Q2) having a pair of output nodes (AR1 / AR2) for outputting storage contents having mutually opposite logic levels; and the word line (WL)
By selectively conducting according to the signal level of 1), the pair of output nodes (AR1 / AR2) of the flip-flop circuit (Q1 + Q2) is connected to the pair of bit lines (BL1 / BL1 *). Bit line connecting means (Q3 + Q4) for connecting respectively; the memory cell (CEL1)
1) A first capacitor section (C1 + C2) for applying a circuit operating voltage (Vdd to Vss) of a predetermined value or more (for example, 1 V or more) to the flip-flop circuit (Q1 + Q2) so that the stored content of 1) is held; Line (BL1 /
BL1 *) is selectively connected to the circuit operating voltage (V
second capacitor section (CL1 + CL2) charged to a voltage corresponding to dd to Vss; first timing (FIG. 1)
3 at t01), the second capacitor section (CL1 + CL
First intermittent charging means (Q11 + Q1) for intermittently charging 2) to a voltage corresponding to the circuit operating voltage (Vdd to Vss).
2; VRE0 from DR10) and; at the second timing (t03 in FIG. 13) different from the first timing (t01 in FIG. 13), the second capacitor unit (CL1 + C)
L2) is charged to the bit line (BL
Second intermittent charging means (Q1) for intermittently charging 1 / BL1 *)
3 + Q14; VRE1 from DR10); and the bit line (BL1) charged by the second intermittent charging means at a third timing (t03 in FIG. 13) different from the first timing (t01 in FIG. 13). / BL1 *) charging voltage of the first capacitor unit (C1 + C2)
Third intermittent charging means (Q3 + Q4; DW1) for intermittently charging
0) and;

In order to achieve the above object, in the SRAM of the second invention, a plurality of pairs of bit lines (BLn / BLn) are used.
In the memory device (FIG. 1 or FIG. 8) having a matrix structure in which a plurality of memory cells (CELmn) are arranged at the intersections of *) and a plurality of word lines (WLn), each memory cell (for example, CEL11) is And a flip-flop circuit (Q1 + Q2) having a pair of output nodes (AR1 / AR2) for outputting storage contents having mutually opposite logic levels; and the word line (WL1).
1 by selectively conducting according to the signal level of
A pair of output nodes (A) of the flip-flop circuit (Q1 + Q2) are connected to the pair of bit lines (BL1 / BL1 *).
R1 / AR2) are respectively connected to bit line connecting means (Q3 + Q4); a predetermined value or more (for example, 1 V or more) is applied to the flip-flop circuit (Q1 + Q2) so that the memory content of the memory cell (CEL11) is held. A capacitor section (C1 + C2) for providing the circuit operating voltage (Vdd to Vss) of the above; and the first timing (t0 in FIG. 13).
In 1), the bit line intermittent charging means (Q13 / Q14 + D in FIG. 1) for intermittently charging the bit line (BL1 / BL1 *) to a voltage corresponding to the circuit operating voltage (Vdd to Vss).
VRE1 from R10; or Q11 / Q12 + in FIG.
VR from R11 / R12 + r11 / r12 + DR10
E0) and; second timing (t in FIG. 13 for the configuration in FIG. 1)
03; in the configuration of FIG. 8, at t01 in FIG. 13, the capacitor section intermittent charging means (Q3 + Q4) for intermittently charging the capacitor section (C1 + C2) by using the charging voltage of the charged bit line (BL1 / BL1 *). DW10) and;
It has.

In the SRAM of the second invention, the bit line intermittent charging means (Q11 / Q12 + R11 / R12) is used.
+ R11 / r12 + DR10) is the bit line (BL
When intermittently charging 1 / BL1 *), this bit line (BL
Resistor circuit (R1 that suppresses the current flowing into 1 / BL1 *)
1 + R12 and / or r11 + r12).

Further, in order to achieve the above object, in the SRAM of the third invention, a plurality of pairs of bit lines (BLn / BL) are provided.
In the memory device (FIG. 1) having a matrix structure in which a plurality of memory cells (CELmn) are arranged at intersections of n *) and a plurality of word lines (WLn), each memory cell (for example, CEL11) is configured. And a flip-flop circuit (Q1 + Q2) having a pair of output nodes (AR1 / AR2) for outputting storage contents having mutually opposite logic levels; selected according to the signal level of the word line (WL1) Are electrically connected to the pair of bit lines (BL1 / BL1 *), the pair of output nodes (AR1 / A of the flip-flop circuit (Q1 + Q2)) (AR1 / A).
R2) are respectively connected to bit line connecting means (Q3 +
Q4); and the flip-flop circuit (Q1 +) so that the memory content of the memory cell (CEL11) is retained.
A first capacitor unit (C1) that applies a circuit operating voltage (Vdd to Vss) of a predetermined value or higher (for example, 1 V or higher) to Q2).
+ C2); the first timing (t03 in FIG. 15 or FIG. 17, t05 in FIG. 16, FIG. 1) so that the circuit operating voltage (Vdd to Vss) is maintained at or above the predetermined value.
8 at t01), the first capacitor section (C1
+ C2) first switch means (Q5 + Q) for intermittent charging
6) ;; a second capacitor portion (CLs) selectively connected to the first switch means (Q5 + Q6) and charged to a predetermined voltage (Vdd); and a second timing (t01 in FIG. 15 or FIG. 17). , T03 in FIG. 16 and t0 in FIG.
Second switch means (Q10) which is turned on in 3) to intermittently charge the second capacitor unit (CLs) to the predetermined voltage.
1; VRE0X from DR10); and the second timing (t01 in FIG. 15 or FIG. 17, t03 in FIG. 16)
Third timing (t15 in FIG. 18) different from that in FIG.
Alternatively, t03 in FIG. 17, t05 in FIG. 16, t0 in FIG.
The third switch means (Q10) which conducts in 1) and conducts the first switch means (Q5 + Q6) with the voltage (VRE1) charged in the second capacitor part (CLs).
2; VRE1X from DR10) and;

Further, in order to achieve the above object, in the SRAM of the fourth invention, a flip-flop (Q1 + Q2 in FIG. 2 or FIG. 10) for storing information and this flip-flop (Q1 + Q2) so that the stored contents are held. A memory cell (CELmn) including a first capacitor section (C1 + C2) for applying a circuit operating voltage (Vdd to Vss) to
And; a signal line (BL1 / BL1 * in FIGS. 1 and 2) to which the plurality of memory cells (CELmn) are connected; or FIG.
Which is selectively connected to RE1) of FIG.
Secondly charged to the circuit operating voltage (Vdd to Vss)
Capacitor part (CL1 + CL2 in FIG. 1; or C in FIG. 9)
Ls); and at the first timing (t01 in FIG. 13; or t01 in FIG. 15), the second capacitor section (CL1 + C).
L2; or CLs is the circuit operating voltage (Vdd to V)
first intermittent charging means (Q11 + Q12 + RE0 in FIG. 1; or Q10 in FIG. 9) for intermittent charging to a voltage corresponding to ss).
1 + RE0X); second timing (t0 in FIG. 13)
3; or at t03 of FIG. 15, the second capacitor section (C
Second intermittent charging means (FIG. 1) for intermittently charging the signal line (BL1 / BL1 * in FIGS. 1 and 2; or RE1 in FIGS. 9 and 10) by using the voltage charged in L1 + CL2; or CLs). Q13 + Q14 + RE1; or Q in FIG.
102 + RE1X); and the third timing (t in FIG. 13).
03; or t01 of FIG. 15; or t05 of FIG. 16)
Then, the charging voltage of the signal line (BL1 / BL1 * of FIGS. 1 and 2; or RE1 of FIGS. 9 and 10) is used (the voltage of BL1 / BL1 * is directly used in FIG. 2; RE1 in FIG. 10).
Of the voltage of the first capacitor part (C1 +
Third intermittent charging means for intermittently charging C2) (Q3 + Q4 + DW10 in FIGS. 1 and 2; or Q5 + Q in FIGS. 9 and 10)
6) and;

In summary, in order to achieve the above object,
According to the present invention, the flip-flops (Q1, Q1) forming the SRAM memory cell (for example, CEL11 in FIG. 2) are formed.
In the load circuit of 2), a pair of capacitors (C1, C2) charged to a voltage corresponding to the power supply voltage (Vdd) is used instead of the high load resistance connected to the power supply circuit (Vdd).

The pair of capacitors (C1, C2) holds the circuit potential for maintaining the circuit operation state (information storage state) of the flip-flops (Q1, Q2), and directly holds the storage information of the memory cell. Not a thing. But,
The charge accumulated in the pair of capacitors (C1, C2) is discharged by a leak current or the like, and the flip-flops (Q1, Q2) are discharged.
When the drain voltage of 2) becomes lower than a certain level, the circuit operating state of the flip-flops (Q1, Q2) cannot be maintained, and the stored contents of the memory cells (CEL11 etc.) configured by the flip-flops disappear.

In order to prevent the memory contents of the memory cell from being lost, in the present invention, a means for charging the pair of capacitors (C1, C2; non-information storage medium) which constitutes the load circuit at a certain cycle (for example, TW in FIG. 13). (For example, Q3, Q4,
DW10) is provided. This charging means (Q3, Q4,
Since the cyclic charging operation of the pair of capacitors (C1, C2) by the DW10) is similar to the refresh operation in the DRAM, the SRAM of the present invention is referred to as a dynamic SRAM in this specification.

However, while the normal DRAM refresh is an operation of "precharging for each corresponding bit line, then reading the current memory cell storage contents and writing back the read contents," the dynamic of the present invention. SR
The AM refresh is an operation of "not reading the current stored contents, but merely intermittently charging the load capacitor for maintaining the state of the flip-flop circuit" (from a different viewpoint, the paired capacitors C1 and C2 of the present invention are: ,
It can be said that it is a switched capacitor for a load circuit instead of the high load resistance of the SRAM flip-flop). This point is essentially different from a normal DRAM.

Therefore, the refresh of the present invention can be batch-executed for a plurality of memory cells at an appropriate timing (a period when there is no memory access) for a short time. Therefore, the refresh of the present invention reduces the read / write operation speed of the memory. It does not become a factor, and high speed performance comparable to a normal SRAM can be obtained.

Further, as long as the circuit state (on / off state) of the flip-flop can be maintained, the charging voltage of the load circuit capacitors (C1, C2) may be in an arbitrary range to some extent. Therefore, if the charge voltage of the load circuit capacitors (C1, C2) immediately after refreshing is set sufficiently high, no error occurs even if refreshing (charging / discharging) is not performed as frequently as in a normal DRAM that stores information in the cell capacitors. . Therefore, the refresh cycle can be set longer than that of the DRAM of the same scale, and the current consumption associated with the refresh can be reduced.

Here, the circuit state of "keep the charging voltage of the load circuit capacitors (C1, C2) immediately after refreshing sufficiently large" is the load circuit capacitor (C
This can be realized without always holding the charging circuit (1, C2) (the other bit line BLn in FIG. 1 or the refresh line REm in FIG. 9) in the precharged state. In the present invention, a circuit for charging the load circuit capacitors (C1, C2) (see FIG.
Another bit line BLn or refresh line RE of FIG.
This circuit state is realized by intermittently charging m) at a predetermined timing. Due to this intermittent charging, the charging circuit for the load circuit capacitors (C1, C2) (the other bit line BLn in FIG. 1 or the refresh line RE in FIG. 9).
The time integrated value of the current for repeatedly charging m) becomes smaller (as compared with the case where intermittent charging is not performed), and the dynamic S
The power consumption of the RAM can be effectively reduced.

[0022]

DETAILED DESCRIPTION OF THE INVENTION A dynamic SRAM according to an embodiment of the present invention will be described below with reference to the drawings. It should be noted that common or similar reference numerals are used for functionally common or similar parts in a plurality of drawings to avoid redundant description.

FIG. 1 is a block diagram for explaining a schematic structure of a dynamic SRAM according to an embodiment of the present invention. Here, for the sake of clarity, 16 cells CEL11 among a large number of memory cells CELmn
Only the CEL 44 and its peripheral circuit blocks are shown.

In FIG. 1, bit line pairs BL1 / BL1 * to BL4 / BL4 * of the first to fourth columns are connected to sense amplifiers SA1 to SA4, respectively (the asterisk * attached to the reference numeral of the bit line). Refers to having the opposite logic level to the one without *).

Bit line pair BL1 / BL1 * in the first column
Are connected to the cells CEL11 to CEL41, and the bit lines BL2 / BL2 * in the second column are connected to the cells CEL12 to CEL12.
CEL42 is connected and bit line pair BL3 of the third column
The cells CEL13 to CEL43 are connected to / BL3 *, and the cells CEL14 to CEL44 are connected to the bit line pair BL4 / BL4 * in the fourth column.

The cells CEL11 to CEL14 are connected to the first word line WL1, the cells CEL21 to CEL24 are connected to the second word line WL2, and the cells CEL31 to CEL are connected.
The third word line WL3 is connected to EL34, and the cell CE
The fourth word line WL4 is connected to L41 to CEL44.

The word lines W1 to W4 are word line decoders D
The sense amplifiers SA1 to SA4 are connected to W10 and are connected to the bit line decoder DB10.

Further, the bit line pair BL1 / of the first column
BL1 * is a capacitor pair CL1 / C via a first column refresh transistor pair Q13 / Q14, respectively.
It is connected to L2. This capacitor pair CL1 / CL2
Are respectively the first column refresh transistor pair Q
It is connected to the power supply line Vdd via 11 / Q12.

Similarly, the bit line pair BL2 / BL2 * to B
L4 / BL4 * is connected to a capacitor pair CL1 / CL2 via refresh transistor pairs Q23 / Q24 to Q43 / Q44, respectively, and these capacitor pairs CL1 / CL2 form refresh transistor pairs Q21 / Q22 to Q41 / Q42, respectively. Through the power line Vdd
Connected to.

Refresh transistor pair Q13 / Q1
The gates of 4-Q43 / Q44 are connected to the refresh line RE1, and the refresh transistor pair Q11 / Q12 is connected.
The gates of Q41 / Q42 are connected to the refresh line RE0. The refresh lines RE0 and RE1 are refresh pulses (VRE0 and VRE1 to be described later).
Is connected to the refresh decoder DR10.

The capacitor pair CL1 / CL2 is intermittently charged by the voltage of the power supply line Vdd via the transistor pair Q11 / Q12 to Q41 / Q42 which are turned on / off by the pulse (VRE0) of the refresh line RE0. Then, each bit line pair (BL1 / BL1 * to BLn / BL
n *) is a pulse (VRE1) of the refresh line RE1
Transistor pair Q13 / Q14 to be turned on / off by
Via Q43 / Q44, capacitor pair CL1 / CL2
It is intermittently charged by the charging voltage of.

Here, about 1 pF to 10 pF is selected as the capacitance of each of the capacitor pair CL1 / CL2. A capacitor inside a memory cell group (CEL11 to CEL41, etc.) in which the sum of the capacitor pair CL1 / CL2 and the capacitance of each bit line pair (BL1 / BL1 *, etc.) hangs on the bit line pair (BL1 / BL1 *). If it is sufficiently large with respect to the total value of C1 and C2 (10 fF or less per cell), the bit line pair (B
It is possible to suppress the voltage fluctuation of L1 / BL1 *).

Each refresh transistor pair (Q
11 / Q12 to Q41 / Q42) and 100 fF (0.1 pF) to 10 at the connection points between the power source line Vdd and the power source line Vdd, respectively.
A voltage fluctuation absorbing capacitor Css of about pF is connected. The total capacitance of these capacitors Css and the power supply line Vd
The capacitance of the capacitor pair CL1
The voltage fluctuation of the power supply line Vdd due to the intermittent charging of / CL2 (due to the pulse driving of the refresh line RE0) is suppressed.

FIG. 2 shows an internal configuration example (one cell, four transistors) of each cell of FIG. 1 for the cell CEL11 (same for other cells).

That is, the sources (lightly doped drain LDD structure) of the Nch transistors Q1 and Q2 are connected to the ground line Vss. The polysilicon gate of the transistor Q1 is connected to the drain (lightly-doped drain LDD structure) of the transistor Q2 via the wiring L1. Similarly, the polysilicon gate of the transistor Q2 is connected to the drain (lightly doped drain LDD structure) of the transistor Q1 via the line L2. In this way, the flip-flop circuit (Q1 + Q2) whose gates are cross-connected (cross-coupled) constitutes the information storage section (cell structure of SRAM) of the cell CEL11.

This flip-flop circuit (Q1 + Q2)
Has a pair of output nodes that output the stored contents whose logic levels are opposite to each other. One output node is connected to the source (or drain) of the Nch (or Pch) transistor Q3 via the wiring region (diffusion layer) AR1. The drain (or source) of the transistor Q3 is
It is connected to one of the bit line pairs BL1 / BL1 * BL1.

Similarly, a flip-flop circuit (Q1 + Q
The other output node of 2) is the wiring region (diffusion layer) AR2.
Is connected to the source (or drain) of the Nch (or Pch) transistor Q4. The drain (or source) of the transistor Q4 is connected to the other BL1 * of the bit line pair (metal wiring layer) BL1 / BL1 *. The polysilicon gates of transistors Q3 and Q4 are connected to word line (polysilicon layer) WL1.

A drain capacitor C1 is provided between the wiring region AR1 (the drain output of the transistor Q1) and the ground line Vss, and a drain capacitor C1 is provided between the wiring region AR2 (the drain output of the transistor Q2) and the ground line Vss. C2 is provided.

The capacitor C1 or C2 is charged by the voltage of the bit line BL1 / BL1 * (corresponding to the charging voltage of the capacitor pair CL1 / CL2) at the moment when the transistors Q3 and Q4 are conducted by the refresh pulse on the word line WL1. It For example, transistor Q1 is off,
Bit line voltage is + 3V when transistor Q2 is on
If so, the capacitor C1 may have, for example, +1 to +1 depending on the high level period of the refresh pulse and its repetition period.
It is charged to about + 2.5V. Also, the transistor Q2
Is off and the transistor Q1 is on, the capacitor C2 is charged to, for example, about +1 to +2.5 V according to the high level period of the refresh pulse and its repetition period.

When the transistors Q1 and Q2 are turned on,
In the off state (contents of SRAM cell CEL11), when both capacitors C1 and C2 are completely discharged,
Lost. In order to prevent the loss of the stored contents, the capacitors C1 and C2 are appropriately charged by the bit line voltage via the transistors Q3 and Q4 which are intermittently turned on by the refresh pulse. (The capacitors C1 and C2 can be considered as switched capacitors in view of the circuit operation of being intermittently charged by the transistor switch.) Furthermore, between the power supply line Vdd and the ground line Vss,
Total capacitance of capacitors C1 and C2 (eg 10f
A power supply voltage fluctuation absorbing capacitor Css (for example, about 100 fF to 10 pF) that is sufficiently larger than F) is connected. Since the relative large-capacity capacitor Css is constantly charged with the power supply voltage Vdd, the power supply voltage of the cell CEL11 does not drop drastically the instant the relative small-capacity capacitors C1 and C2 are refresh-charged.

FIG. 3 is a plan view exemplifying a deformed integrated circuit structure in which all the transistors Q1 to Q4 of FIG. 2 are formed of NchMOS transistors on a P substrate or P well.

For example, the cell formation region of the P substrate (3 to 4 μm)
N-type impurities (phosphorus, etc.) in an area of about mx 4-5 μm)
Are thermally diffused to form the drain and source regions of the transistors Q1 to Q4 (in this region, a small amount of P-type impurity such as boron is ion-implanted in advance, which becomes a lightly doped drain LDD region). . Simultaneously with the formation of the drain / source LDD regions, connection wiring regions (diffusion layers) AR1 and AR2 that connect the electrodes of the transistors Q1 to Q4 as shown in FIG. 2 and power supply lines (diffusion layer) Vdd. (Not shown) are formed.

After the diffusion layer is formed, the gate regions of the transistors Q1 to Q4 and the word line WL1 are formed of a polysilicon layer in one step via a silicon oxide layer (not shown).

After the polysilicon layer is formed, the metal wiring 1 of the ground line Vss is interposed via a silicon oxide layer (not shown).
Is formed. A part of this Vss metal wiring pattern is parallel to the connection wiring regions AR1 and AR2 and the Vdd diffusion layer via the silicon oxide layer. Then, a capacitor C1 having a silicon oxide layer as a dielectric is formed between the area AR1 and the Vss metal wiring, and a capacitor C2 having a silicon oxide layer as a dielectric is formed as the areas AR2 and V2.
It is formed between the ss metal wiring.

Although not shown, the pair of capacitors CL1 and CL2 shown in FIG. 1 can be formed in the same structure as the capacitors C1 and C2 shown in FIG.

After the metal wiring layer 1 is formed, a bit line pair BLn / BLn * orthogonal to the word line WL1 is formed by the metal wiring 2 via a silicon oxide layer (not shown). In addition, a square mark in the drawing indicates a contact hole.

In the configuration of FIG. 3, only one type of polysilicon (polysilicon layer having a relatively low resistance) may be used, so that a conventional SRAM using two types of polysilicon (one type for low resistance wiring, another type for polysilicon) Seeds are less expensive to manufacture than high resistance flip-flop load resistors). Further, since the polysilicon high resistance having a large temperature change is not used, it is possible to obtain a flip-flop memory cell having excellent temperature stability in the storage state.

In FIG. 4, the transistors Q1 and Q2 in FIG. 2 are N-channel MOS transistors on the P substrate or P well, and the transistors Q3 and Q4 are Pc in the N well.
It is a top view which deforms and exemplifies the integrated circuit structure when it comprises an hMOS transistor.

FIG. 4 shows the Nch transistor Q3 of FIG.
Pch transistors Q3 and Q in which Q4 is housed in the N well
4 and the other structure is the same as that of FIG.

Incidentally, in the embodiment of FIG. 3 or 4, the capacitors C1 and C2 (and the capacitors CL1 and CL1,
CL2) has a parallel plate capacitor structure using silicon oxide as a dielectric. However, these capacitors may be ferroelectric capacitors or PN junction capacitors as long as the required capacitance can be obtained and the leakage current can be reduced to a level that poses no practical problem.

The capacitors C1 and C2 and the capacitors CL1 and CL2 may have a trench structure or a multiple fin structure.

FIG. 5 is a block diagram for explaining a schematic structure of a dynamic SRAM according to the second embodiment of the present invention. The configuration of FIG. 5 has a sense amplifier group SAn.
The configuration is the same as that of FIG. 1 except that the arrangement of the bit line decoder DB10 is changed.

FIG. 6 is a block diagram for explaining a schematic structure of a dynamic SRAM according to the third embodiment of the present invention.

In the configuration of FIG. 6, refresh pulses (refresh lines RE01 to RE01 to Q11 / Q12 to Q41 / Q42) are applied to the gates of each refresh transistor pair (Q11 / Q12 to Q41 / Q42).
The pulses VRE01 to VRE04 on RE04 are generated at different timings (see FIG. 14), and each refresh transistor pair (Q13 / Q14 to Q43 /
Refresh pulse applied to the gate of Q44 (pulse VRE10 on refresh lines RE10-RE40)
VRE40; see FIG. 14) except that the generation timings thereof are different from each other. These refresh pulses are applied to the refresh decoder DR1.
It is generated by 0.

FIG. 7 is a block diagram for explaining the schematic structure of a dynamic SRAM according to the fourth embodiment of the present invention. The configuration of FIG. 7 has a sense amplifier group SAn.
The configuration is the same as that of FIG. 6 except that the arrangement of the bit line decoder DB10 is changed.

FIG. 8 shows a schematic structure of a dynamic SRAM according to the fifth embodiment of the present invention. here,
The parasitic capacitance of the corresponding bit line BLn / BLn * is substituted for the function of the capacitor pair CL1 / CL2, and the magnitude of the charging current with respect to these parasitic capacitances of the bit lines is determined by the resistance element r.
11 / r12 to r41 / r42 are appropriately suppressed (when there are resistance elements R11 / R12 to R41 / R42 described later, the resistance elements r11 / r12 to r41 / r42 can be omitted).

The intermittent charging for the bit line parasitic capacitance having the function of the capacitor pair CL1 / CL2 is turned on / off by the refresh pulse RE0, and the transistor pair Q11 / Q12 to Q41 / Q42 and the resistance element R11 are controlled.
/ R12 to R41 / R42 via the charging voltage of the power supply voltage fluctuation absorbing capacitor Css of the power supply line Vdd.

The magnitude of the intermittent charging current with respect to the bit line parasitic capacitance having the function of the capacitor pair CL1 / CL2 is determined by the resistance elements R11 / R12 to R41 / R42 and /.
Alternatively, it can be arbitrarily controlled by the values of the resistance elements r11 / r12 to r41 / r42 (including the case of substantially zero ohms).

In the configuration of FIG. 8, if the values of the resistance elements R11 / R12 to R41 / R42 and / or the resistance elements r11 / r12 to r41 / r42 are increased in order to suppress the intermittent charging current, the resistance elements and the bits are set. The time constant with the line parasitic capacitance increases. Then, to charge up the bit line parasitic capacitance (compared to the embodiment such as FIG. 1).
It will take time. Therefore, the embodiment of FIG. 8 is suitable for an application in which the refresh time of the drain capacitors C1 and C2 inside the dynamic SRAM cell can be set to a large value. (When it is desired to refresh the drain capacitors C1 and C2 inside the dynamic SRAM cell relatively frequently, the configuration of FIG. 1 or the like is suitable.) FIG. 9 shows a dynamic SRAM according to a sixth embodiment of the present invention. A schematic configuration is shown. In FIG. 9, bit line pairs BL1 / BL1 * to BL4 / BL in the first to fourth columns
4 * are respectively connected to the sense amplifiers SA1 to SA4 (the asterisk attached to the reference numeral of the bit line *)
Refers to having the opposite logic level to the one without *).

Bit line pair BL1 / BL1 * in the first column
Are connected to the cells CEL11 to CEL41, and the bit lines BL2 / BL2 * in the second column are connected to the cells CEL12 to CEL12.
CEL42 is connected and bit line pair BL3 of the third column
The cells CEL13 to CEL43 are connected to / BL3 *, and the cells CEL14 to CEL44 are connected to the bit line pair BL4 / BL4 * in the fourth column.

The first word line WL1 and the first refresh line RE1 are connected to the cells CEL11 to CEL14, and the second word line WL is connected to the cells CEL21 to CEL24.
2 and the second refresh line RE2 are connected, and the cell C
A third word line WL3 and a third refresh line RE3 are connected to EL31 to CEL34, and cells CEL41 to
The fourth word line WL4 and the fourth refresh line RE4 are connected to the CEL 44.

The word lines W1 to W4 are word line decoders D
The sense amplifiers SA1 to SA4 are connected to W10 and are connected to the bit line decoder DB10.

The refresh lines RE1 to RE4 are
It is connected to the corresponding refresh line capacitors CLs via the transistors Q102 to Q402 which are on / off controlled by the drive pulse (VRE1X described later) of the refresh pulse line RE1X. These capacitors CLs are connected to the power supply line Vdd via the transistors Q101 to Q401 which are on / off controlled by the drive pulse (VRE0X described later) of the refresh pulse line RE0X.

Refresh pulse lines RE0X and RE
The 1X drive pulse (VRE0X, VRE1X) is output from the refresh decoder DR10.

FIG. 10 shows an example of the internal structure of each cell of FIG. 9 (1
Cell 6 transistor) is shown for cell CEL 11 (same for other cell configurations).

That is, the sources (lightly-doped drain LDD structure) of the Nch transistors Q1 and Q2 are connected to the ground line Vss. The polysilicon gate of the transistor Q1 is connected to the drain (lightly-doped drain LDD structure) of the transistor Q2 via the wiring L1. Similarly, the polysilicon gate of the transistor Q2 is connected to the drain (lightly doped drain LDD structure) of the transistor Q1 via the line L2. In this way, the flip-flop circuit (Q1 + Q2) whose gates are cross-connected (cross-coupled) constitutes the information storage section (cell structure of SRAM) of the cell CEL11.

This flip-flop circuit (Q1 + Q2)
Has a pair of output nodes that output the stored contents whose logic levels are opposite to each other. One output node is connected to the source (or drain) of the Nch (or Pch) transistor Q3 via the wiring region (diffusion layer) AR1. The drain (or source) of the transistor Q3 is
It is connected to one of the bit line pairs BL1 / BL1 * BL1.

Similarly, the flip-flop circuit (Q1 + Q
The other output node of 2) is the wiring region (diffusion layer) AR2.
Is connected to the source (or drain) of the Nch (or Pch) transistor Q4. The drain (or source) of the transistor Q4 is connected to the other BL1 * of the bit line pair (metal wiring layer) BL1 / BL1 *. The polysilicon gates of transistors Q3 and Q4 are connected to word line (polysilicon layer) WL1.

One output node of the flip-flop circuit (Q1 + Q2) is connected to the source (or drain) of the Nch transistor Q5 via the wiring area AR1. The drain (or source) of the transistor Q5 is
It is connected to the power supply line Vdd (about +1.5 to + 5V).

Similarly, the flip-flop circuit (Q1 + Q
The other output node of 2) is N through the wiring area AR2.
It is connected to the source (or drain) of the ch transistor Q6. The drain (or source) of the transistor Q6 is connected to the power supply line Vdd. Transistor Q5
The polysilicon gates of Q6 and Q6 are connected to the refresh line (polysilicon layer) RE1.

A drain capacitor C1 is provided between the wiring region AR1 (the drain output of the transistor Q1) and the ground line Vss, and a drain capacitor C1 is provided between the wiring region AR2 (the drain output of the transistor Q2) and the ground line Vss. C2 is provided.

The capacitor C1 or C2 is charged with the voltage of the power supply line Vdd at the moment when the transistors Q5 and Q6 are rendered conductive by the refresh pulse on the refresh line RE1. For example, when the transistor Q1 is off and the transistor Q2 is on, the power supply line Vdd voltage is + 3V.
If so, the capacitor C1 may have, for example, +1 to +1 depending on the high level period of the refresh pulse and its repetition period.
It is charged to about + 2.5V. Also, the transistor Q2
Is off and the transistor Q1 is on, the capacitor C2 is charged to, for example, about +1 to +2.5 V according to the high level period of the refresh pulse and its repetition period.

Turning on the transistors Q1 and Q2
In the off state (contents of SRAM cell CEL11), when both capacitors C1 and C2 are completely discharged,
Lost. In order to prevent the loss of the stored contents, the capacitors C1 and C2 are connected to the power source voltage V through the transistors Q5 and Q6 which are intermittently turned on by the refresh pulse.
It is adapted to be appropriately charged by dd. (The capacitors C1 and C2 can be considered as switched capacitors in view of the circuit operation of being intermittently charged by the transistor switch.) Furthermore, between the power supply line Vdd and the ground line Vss,
Total capacitance of capacitors C1 and C2 (eg 10f
A power supply voltage fluctuation absorbing capacitor Css (for example, about 100 fF to 10 pF) that is sufficiently larger than F) is connected. Since the relative large-capacity capacitor Css is constantly charged with the power supply voltage Vdd, the power supply voltage of the cell CEL11 does not drop drastically the instant the relative small-capacity capacitors C1 and C2 are refresh-charged.

FIG. 11 shows transistors Q1 to Q of FIG.
FIG. 6 is a plan view illustrating a deformed integrated circuit structure in the case where all 6 are composed of NchMOS transistors on a P substrate or a P well.

For example, the cell formation region of the P substrate (3 to 4 μm
N-type impurities (phosphorus, etc.) in an area of about mx 4-5 μm)
Is thermally diffused to form drain and source regions of the transistors Q1 to Q6 (in this region, a small amount of P-type impurity such as boron is ion-implanted in advance, which becomes a lightly doped drain LDD region). . Concurrently with the formation of the drain / source LDD regions, connection wiring regions (diffusion layers) AR1 and AR2 for connecting the electrodes of the transistors Q1 to Q6 as shown in FIG. 2 and power supply lines (diffusion layer) Vdd. And are formed.

After the diffusion layer is formed, the gate regions of the transistors Q1 to Q6 are formed through a silicon oxide layer (not shown).
The word line WL1 and the refresh line RE1 are formed by a one-step polysilicon layer.

After the polysilicon layer is formed, the metal wiring 1 of the ground line Vss is interposed via a silicon oxide layer (not shown).
Is formed. A part of this Vss metal wiring pattern is parallel to the connection wiring regions AR1 and AR2 and the Vdd diffusion layer via the silicon oxide layer. Then, a capacitor C1 having a silicon oxide layer as a dielectric is formed between the area AR1 and the Vss metal wiring, and a capacitor C2 having a silicon oxide layer as a dielectric is formed as the areas AR2 and V2.
A capacitor Css formed between the ss metal wiring and having a silicon oxide layer as a dielectric is formed between the region AR1 and the Vdd diffusion layer. In this case, since the capacitor Css has a relatively large area, the capacitance of the capacitor Css is
It is possible to make the capacitance larger than the total capacitance of the capacitors C1 and C2.

Although not shown, the capacitor C of FIG.
Ls can be made with the same structure as the capacitor C1 or C2 in FIG.

After the metal wiring layer 1 is formed, a bit line pair BLn / BLn * orthogonal to the word line WL1 is formed by the metal wiring 2 via a silicon oxide layer (not shown). In addition, a square mark in the drawing indicates a contact hole.

In the configuration shown in FIG. 11, one type of polysilicon (polysilicon layer having a relatively low resistance) may be used. Therefore, a conventional SRAM using two types of polysilicon (one type for low resistance wiring, another type for polysilicon) Seeds are less expensive to manufacture than high resistance flip-flop load resistors). Further, since the polysilicon high resistance having a large temperature change is not used, it is possible to obtain a flip-flop memory cell having excellent temperature stability in the storage state.

FIG. 12 shows the transistors Q1 and Q of FIG.
2, Q5 and Q6 are NchMO in P substrate or P well
FIG. 9 is a plan view illustrating a deformed example of an integrated circuit structure including S transistors and transistors Q3 and Q4 including PchMOS transistors in an N well.

FIG. 12 shows the Nch transistor Q of FIG.
Pch transistor Q in which 3 and Q4 are housed in N well
3 and Q4, other structures are shown in FIG.
Is similar to.

In the embodiment of FIG. 11 or 12, the capacitors C1, C2 and Css all have a parallel plate capacitor structure in which silicon oxide is used as a dielectric. However, these capacitors may be ferroelectric capacitors or PN junction capacitors as long as the required capacitance can be obtained and the leakage current can be reduced to a level that poses no practical problem.

The capacitors C1 and C2 and the capacitors CL1 and CL2 may have a trench structure or a multi-fin structure.

FIG. 13 shows refresh line drive voltages (refresh pulses) VRE0 and VRE1 when the capacitors C1 and C2 in all cells of the memory cell matrix of FIG. 1 or FIG. 5 are collectively (simultaneously) refreshed (intermittently charged). FIG. 6 is a timing chart diagram for explaining how to generate?

First, the word line (WLm, for example, WL
Before 1) becomes active, the drive voltage (pulse) VRE0 of the refresh line RE0 is generated (time t0
1). During the generation period of this drive voltage VRE0 (time t01
~ T02) refresh transistor pair Q11 / Q1
2 to Q41 / Q42 turn on, and bit line capacitor pair C
L1 / CL2 is charged by the power supply voltage Vdd (charging voltage of the capacitor Css). (At this time transistor Q
13 / Q14 to Q43 / Q44 are off. ) Subsequently, for example, the word line drive voltage (pulse) VW is applied to the word line WL1.
When L is applied (time t03) and data is written (or read) in the cell CEL11, the refresh line drive voltage (pulse) VRE1 is applied to the refresh line RE1 in parallel with this. (Time t03). Then, the transistors Q13 / Q1
4 to Q43 / Q44 simultaneously conduct, and cell C
The bit line select transistors Q3 / Q4 of EL11 are rendered conductive (time t03 to t04). (At this time, the transistors Q11 / Q12 to Q41 / Q42 are turned off.) If the cell storage contents at that time are the transistor Q1 off and the transistor Q2 on, the capacitor C1 is on the charging potential (approximately Vdd) side of the bit line capacitor CL1. Circuit state of being charged (refreshed) and transistor Q1 off and transistor Q2 on (first information storage state)
Is guaranteed.

If the cell memory contents at that time are the transistor Q2 off and the transistor Q1 on, the capacitor C2 charges the bit line capacitor CL2 to the charging potential (approximately Vd).
d) is charged (refreshed) to the transistor Q2
The circuit state of turning off the transistor Q1 on (second information storage state) is guaranteed.

Capacitor C associated with reading and writing of the above data
After refreshing 1 and C2, when the word line drive voltage VWL is applied to the word line WL1 again (time t07), data is written (or data is read) to the cell CEL11.

Reading and writing of the above data is repeated, and the charging voltage of the bit line capacitor pair CL1 / CL2 becomes the first,
At the time when the second information storage state falls near a level where it cannot be guaranteed, the drive voltage pulse V of the refresh line RE0
RE0 occurs again (time t11 to t12). After the bit line capacitor pair CL1 / CL2 is recharged in this way, when a pulse of the refresh line drive voltage VRE1 is applied to the refresh line RE1 (time t13 to t1).
4), the transistors Q13 / Q14 to Q43 / Q44 and the transistors Q3 / Q4 are simultaneously turned on, and the capacitors C1 and C2 in the memory cell are refreshed again.

In this way, the bit line capacitor pair CL1 / CL is passed between the memory accesses (when VWL occurs).
2 is intermittently charged (t01 to t02; t11 to t12)
At the same time, the in-cell capacitors C1 and C2 are refreshed (t03 to t04; t13 to t14) between the intermittent charges of the bit line capacitor pair CL1 / CL2, without damaging the reading speed of the SRAM. The storage state of the SRAM cell (circuit state of the flip-flop) is dynamically maintained.

In the above example (FIG. 13), the word line drive pulse (VWL) and the refresh pulse (VRE0, VRE).
Although 1) has a phase shift synchronous relationship, the capacitors C1 and C2 in FIG. 2 can be refreshed at other timings. That is, as long as the stored contents of the cell can be maintained, the refresh pulse (VRE0, VRE
The period of 1) is the period of the word line drive pulse (VWL) (T
W) may be multiple times, and the number of refreshes may be relatively reduced. If the refresh times of the capacitors C1 and C2 are reduced, the power consumption current of the cell is correspondingly reduced (the power supply current decrease per cell is small, but when the cells are collected for several tens of megabytes or more, the power supply current decrease is reduced. The amount is not stupid).

The refresh drive voltage VR shown in FIG.
The waveform of E0 is shown when the transistors Q11 to Q42 are enhancement type. If transistor Q1
When the depletion type is used for 1 to Q42, the potential level of the refresh drive voltage VRE0 is shifted in parallel so that the transistors Q11 to Q42 are turned off during the period without memory access and refresh (in the case of Nch transistor, shift to the negative potential side). Need to let.

FIG. 14 collectively (simultaneously) refreshes the capacitors C1 and C2 in all the cells (four-transistor configuration) of the memory cell matrix of FIG. 6 or 7 (intermittent charging).
Drive line drive voltage (refresh pulse) VRE01 to VRE04 and VRE10 to VR
It is a timing chart figure explaining other examples of how to generate E40.

In the example of FIG. 13, a plurality of cells are simultaneously refreshed in units of a plurality of word lines, but in the example of FIG. 14, the refresh timing is shifted by one pulse for each word line (eg, WL1).

For example, immediately before the memory cell CEL11 of FIG. 6 is accessed (before the time ts1), the refresh pulse VRE01 is applied to the transistor pair Q11 / Q1.
2 turns on, and the capacitor pair CL1 / CL2 is the power source Vdd
Will be charged. After that, refresh pulse VRE1
When 0, the transistor pair Q13 / Q14 is turned on, and the bit line pair BL1 / BL1 * becomes the capacitor pair CL1 / CL.
2 is precharged by the charging voltage of 2 (time ts1 to
ts2). When the word line drive pulse VWL1 is applied to the memory cell CEL11 concurrently with the bit line precharge (time ts1 to ts2), the memory cell CEL
11, data is read and written, and capacitors C1 and C2 in the memory cell CEL11 (see FIG.
Refresh), transistor pair Q1 /
This is performed by the flip-flop circuit operation of Q2 (FIG. 2).

Further, immediately before the memory cell CEL12 of FIG. 6 is accessed (before time ts2), the transistor pair Q21 / Q22 is turned on by the refresh pulse VRE02, and the capacitor pair CL1 / CL2 is charged by the power supply Vdd. After that, the transistor pair Q23 / Q24 is turned on by the refresh pulse VRE20, and the bit line pair BL2 / BL2 * is precharged by the charging voltage of the capacitor pair CL1 / CL2 (time ts2-ts).
3). When the word line drive pulse VWL1 is applied to the memory cell CEL12 simultaneously with the bit line precharge (time ts2 to ts3), the memory cell CEL12
Data is read from and written to and the capacitors C1 and C2 (FIG. 2) in the memory cell CEL12 are refreshed by the flip-flop circuit operation of the transistor pair Q1 / Q2 (FIG. 2).

Similarly, immediately before the memory cell CEL13 or CEL14 of FIG. 6 is accessed (before time ts3 or ts4), the refresh pulse VRE03 or VRE04 turns on the transistor pair Q31 / Q32 or Q41 / Q42, and the capacitor pair CL1. / CL2
Are charged by the power supply Vdd. After that, the transistor pair Q33 / Q34 or Q43 / Q44 is turned on by the refresh pulse VRE30 or VRE40, and the bit line pair BL3 / BL3 * or BL4 / BL4 * is precharged by the charging voltage of the capacitor pair CL1 / CL2 (( Time ts3 to ts4 or time ts4 to ts
5). At the same time as the bit line precharge, the word line drive pulse VWL1 is applied to the memory cells CEL13 and CEL.
14 (time ts3 to ts4 or time t
s4 to ts5), the memory cell CEL13 or CEL1
4, data is read / written, and refreshing is performed on the capacitors C1 and C2 (FIG. 2) in the memory cell CEL13 or CEL14 by the flip-flop circuit operation of the transistor pair Q1 / Q2 (FIG. 2).

At time ts1 in FIG. 14, the word line W
Regarding L1, this corresponds to t03 in FIG.

According to the method of FIG. 14, the number of refreshes simultaneously performed at one time is smaller than that of FIG. 13 from the viewpoint of the entire memory, so that the peak value of the cell current accompanying the refresh can be significantly reduced. That is, since the refresh timing is shifted for each word line, the magnitude of power supply voltage fluctuation (or ground line potential fluctuation) accompanying refresh can be further reduced.

FIG. 15 is a timing chart for explaining an example of the operation in the case of collectively (simultaneously) refreshing (intermittent charging) the capacitors C1 and C2 in all the cells (6 transistor structure) of the memory cell matrix.

FIG. 15 (6 transistor cell operation in FIG. 10) shows the first memory cell access (time t01 to t0).
Up to 4), it is similar to the case of FIG. 13 (four-transistor cell operation of FIG. 2), but the content is different. Hereinafter, for example, memory cells on the word line WL1 (CEL11 to CEL1
Reading and writing for 4) will be explained.

First, the refresh decoder DR10
The drive voltage pulse VRE0X is output to the refresh line RE0X (time t01 to t02). As a result, the transistor Q101 is turned on, and the capacitor CLs becomes the power source Vdd.
Is charged.

Then, the refresh decoder DR10
Drive voltage pulse VRE1 to refresh line RE1X
X is output (time t03 to t04). Then, the transistor Q102 turns on (the transistor Q101 turns off).
Then, the refresh line RE1 becomes high level due to the charging voltage of the capacitor CLs. As a result, the in-cell transistor pair Q5 / Q6 of FIG. 10 is turned on, and the in-cell capacitors C1 and C2 are charged to the power supply Vdd to the capacitor Cs.
It is charged by the charging voltage of s. Thus the capacitor C
By charging 1 and C2, the transistor pair Q5
Even after / Q6 is turned off (that is, after the current supply from the power supply Vdd to the in-cell flip-flop is cut off), the storage state of the cell (flip-flop transistor pair Q1 /
The on / off circuit state of Q2) is maintained.

In parallel with this, the word line decoder DW1
0 to word line WL1 word line drive voltage pulse VWL
1 is output and the memory cell (CEL
11 to CEL14) correspond to a pair of bit lines (BL1 / B
L1 * to BL4 / BL4 *) (time t03)
~ T04).

As a result, the stored contents of the memory cells (CEL11 to CEL14) on the word line WL1 are read by the sense amplifiers (SA1 to SA4) or the bit line pair (BL1 / BL1) is read to these memory cells (CEL11 to CEL14). Information on BL1 * to BL4 / BL4 *) is written.

Thus, the first memory access (time t
01 to t04), after the refresh line RE1 is precharged to a certain voltage level, refresh line drive voltage pulses VRE0X and VRE1X are output from the refresh decoder DR10 between memory access (immediately before reading / writing of the corresponding memory cell). t05 to t0
6), meanwhile, the capacitor pair C1 / C2 in the memory cell
Is intermittently charged by the charging voltage of the capacitor Css.
After the in-cell capacitor pair C1 / C2 is thus charged (time t07), the memory cell (for example, CEL11)
Is read and written.

Such intermittent charging (time t05 to t0
6) are memory cells (CEL11 to CEL11) on the word line WL1.
The process is repeated until the reading / writing of CEL14) is completed.

FIG. 16 is a timing chart for explaining another example of the operation in the case of collectively (simultaneously) refreshing (intermittently charging) the capacitors C1 and C2 in all the cells (6 transistor structure) of the memory cell matrix.

In the example of FIG. 16, the generation timings of the refresh line drive voltage pulses VRE0X and VRE1X in FIG. 15 are shifted (time t05 to t in FIG. 15).
06 corresponds to time t03 to t06 in FIG. 16). As a result, the refresh line capacitance (C
(Including Ls) is also reduced, and the voltage fluctuation of the power supply Vdd due to the simultaneous precharge is reduced.

FIG. 17 shows a modification of the generation timing of the refresh line drive voltage pulses VRE0X and VRE1X of FIG. 15, and FIG. 18 shows a modification of the generation timing of the refresh line drive voltage pulses VRE0X and VRE1X of FIG. ing.

In both cases of FIG. 17 and FIG. 18, it is possible to reduce the voltage fluctuation of the power supply Vdd due to the simultaneous precharge.

[0112]

According to the present invention, the flip-flop (Q) which constitutes the memory cell (CEL 11 in FIG. 2) of the SRAM.
1, Q2) is charged to the bit line voltage corresponding to the power supply voltage (Vdd) instead of the high load resistance 1
A pair of capacitors (C1, C2) is used. This capacitor can be formed around the flip-flop circuit using, for example, a silicon oxide film as a dielectric and a semiconductor diffusion layer or a metal wiring layer as an electrode. The temperature coefficient of such a capacitor can be reduced by one digit from the temperature coefficient of high resistance polysilicon. Therefore, it is possible to obtain a memory in which increase in current consumption and occurrence of error are unlikely to occur with respect to temperature changes.

Further, unlike the ordinary DRAM which requires the bit line precharge at the time of reading the stored information, the present invention does not require such bit line precharge, and various storages are possible from the load circuit capacitors (C1, C2). It does not read the contents and write them back. For this reason, there is no memory access for a moment (for example, t05 to t0 in FIG. 15).
6) to utilize a common bit line (eg BL1 / BL
Batch refresh (C1, C1 + C2) for load circuit capacitors (many capacitor pairs C1 + C2) of all cells on 1 *)
Simultaneous charging of C2) is possible. Therefore, in the present invention, the information reading operation (memory access) is not delayed by the refresh.

Further, as long as the circuit state (on / off state) of the flip-flop can be maintained, the charging voltage of the load circuit capacitors (C1, C2) may be within an arbitrary range to some extent. Therefore, if the charge voltage of the load circuit capacitors (C1, C2) immediately after refreshing is set sufficiently high, no error occurs even if refreshing (charging / discharging) is not performed as frequently as in a normal DRAM that stores information in the cell capacitors. . Therefore, the refresh cycle can be made longer than that of the DRAM of the same scale, and the current consumption due to the refresh can be reduced (the current consumption per cell can be 1 nanoampere or less).

The circuit state of "keep the charging voltage of the load circuit capacitors (C1, C2) immediately after refreshing sufficiently large" is the load circuit capacitors (C1, C2).
This can be realized without holding the charging circuit (2) (the other bit line BLn in FIG. 1 or the refresh line REm in FIG. 9) in the always charged state (precharged state). In the present invention, this circuit state is realized by intermittently charging the charging circuit for the load circuit capacitors (C1, C2) (the other bit line BLn in FIG. 1 or the refresh line REm in FIG. 9). By this intermittent charging, the load circuit capacitor (C
1, C2) the charging circuit (the other bit line BLn in FIG. 1 or the refresh line REm in FIG. 9) is repeatedly charged with less time integration value (compared to the case without intermittent charging),
The power consumption of the dynamic SRAM of the present invention can be further reduced.

Further, since the formation of the high resistance polysilicon layer (load resistance of the flip-flop), which requires a separate step, is not necessary, the polysilicon forming step in the memory cell manufacturing is the gate polysilicon forming of the MOS transistor. Only one step is required. Therefore, the integrated circuit of the dynamic SRAM of the present invention can be manufactured with a small number of masks.

[Brief description of drawings]

FIG. 1 is a dynamic S according to an embodiment of the present invention.
FIG. 3 is a block diagram for explaining a schematic configuration of a RAM.

FIG. 2 is a circuit diagram illustrating an internal configuration of each cell in FIG.

FIG. 3 is a plan view showing a deformed example of an integrated circuit structure in the case where transistors Q1 to Q4 of FIG. 2 are all formed of NchMOS transistors on a P substrate or P well.

FIG. 4 is a deformation of an integrated circuit structure in which the transistors Q1 and Q2 of FIG. 2 are composed of NchMOS transistors in a P substrate or a P well, and the transistors Q3 and Q4 are composed of PchMOS transistors in an N well. The top view which illustrates.

FIG. 5 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a second embodiment of the present invention.

FIG. 6 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a third embodiment of the present invention.

FIG. 7 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an internal configuration of each cell of FIG.

FIG. 11 is a deformed plan view illustrating an integrated circuit structure in which all the transistors Q1 to Q6 in FIG. 10 are NchMOS transistors on a P substrate or a P well.

12 is a circuit diagram of transistors Q1, Q2, Q5, Q of FIG.
6 is a plan view illustrating a deformed integrated circuit structure when 6 is composed of an NchMOS transistor in a P substrate or a P well and transistors Q3 and Q4 are composed of PchMOS transistors in an N well. FIG.

FIG. 13 is a timing chart diagram illustrating an example of an operation in the case of collectively (simultaneously) refreshing (intermittent charging) the capacitors C1 and C2 in all cells (four-transistor configuration) of the memory cell matrix.

FIG. 14 is a timing chart illustrating another example of the operation in the case of collectively (simultaneously) refreshing (intermittently charging) the capacitors C1 and C2 in all cells (four-transistor configuration) of the memory cell matrix.

FIG. 15 is a timing chart for explaining an example of an operation in the case of collectively (simultaneously) refreshing (intermittent charging) the capacitors C1 and C2 in all cells (6 transistor configuration) of the memory cell matrix.

FIG. 16 is a timing chart diagram for explaining another example of the operation in the case of collectively (simultaneously) refreshing (intermittently charging) the capacitors C1 and C2 in all cells (6 transistor configuration) of the memory cell matrix.

FIG. 17 is a timing chart diagram for explaining still another example of the operation in the case of collectively (simultaneously) refreshing (intermittently charging) the capacitors C1 and C2 in all cells (6 transistor configuration) of the memory cell matrix.

FIG. 18 is a timing chart diagram for explaining still another example of the operation in the case of collectively (simultaneously) refreshing (intermittently charging) the capacitors C1 and C2 in all the cells (6 transistor configuration) of the memory cell matrix.

[Explanation of symbols]

CELmn ... Memory cell; DW10 ... Word line decoder; DB10 ... Bit line decoder; DR10 ... Refresh decoder; SAn ... Sense amplifier; WLm ... Word line; RE0, RE1 ... Refresh line; RE0X, RE1X ... Refresh pulse line; BLn / BLn * ... bit line pair; Q1, Q2 ... Nch flip-flop transistor pair (flip-flop circuit / information storage unit); Q3, Q4 ... Nch (or Pch) transistor (bit line connecting means); C1, C2 ... drain capacitor (first 1 capacitor portion); CL1, CL2 ... bit line capacitor (second capacitor portion); CLs ... refresh line capacitor (second capacitor portion); Q11 / Q12 to Q41 / Q42 ... Nch transistors (CL1, CL2 for intermittent charging / In Figure 8 Is for C1 and C2 refresh charging); Q13 / Q14 to Q43 / Q44 ... Nch transistors (for refresh charging C1 and C2); Q101 to Q401 ... Nch transistors (for intermittent charging of CLs); Q102 to Q402 ... Nch transistors (For charging the refresh line REm in FIG. 9); R11 to R42 ... Current limiting resistance; r11 to r42 ... Current limiting resistance; Css ... Power supply voltage fluctuation absorbing capacitor; Vss ... Ground line; Vdd ... Power supply line; Wiring region (diffusion layer); VWL ... Word line drive voltage (pulse); VRE0, VRE1, VRE0X, VRE1X, VRE
01 / VRE10 to VRE04 / VRE40 ... Refresh line drive voltage (pulse).

Claims (5)

[Claims] 1. A memory device having a matrix structure in which a plurality of memory cells are arranged at intersections of a plurality of pairs of bit lines and a plurality of word lines, wherein each of the memory cells is formed, and is opposite to each other. A flip-flop circuit having a pair of output nodes for outputting storage contents having a logic level of; and a flip-flop to the pair of bit lines by selectively conducting in accordance with a signal level of the word line. Bit line connecting means for connecting a pair of output nodes of the circuit, respectively; and a first capacitor section for applying a circuit operating voltage of a predetermined value or more to the flip-flop circuit so that the stored contents of the memory cell are held. Secondly selectively connected to the bit line and charged to a voltage corresponding to the circuit operating voltage
A capacitor section; first intermittent charging means for intermittently charging the second capacitor section to a voltage corresponding to the circuit operating voltage at a first timing; and at a second timing different from the first timing, Second intermittent charging means for intermittently charging the bit line using the voltage charged in the second capacitor part; and charging by the second intermittent charging means at a third timing different from the first timing. And a third intermittent charging means for intermittently charging the first capacitor section by using the charging voltage of the bit line. 2. A memory device having a matrix structure in which a plurality of memory cells are arranged at intersections of a plurality of pairs of bit lines and a plurality of word lines, wherein each of the memory cells is formed and is opposite to each other. A flip-flop circuit having a pair of output nodes for outputting storage contents having a logic level of; and a flip-flop to the pair of bit lines by selectively conducting in accordance with a signal level of the word line. Bit line connecting means for respectively connecting a pair of output nodes of the circuit; a capacitor section for applying a circuit operating voltage of a predetermined value or more to the flip-flop circuit so that the stored contents of the memory cell are held; Bit line intermittent charging means for intermittently charging the bit line to a voltage corresponding to the circuit operating voltage at timing 1; and charging at second timing. And a capacitor section intermittent charging means for intermittently charging the capacitor section by using the charging voltage of the bit line. 3. The dynamic SR according to claim 2, further comprising a resistance circuit for suppressing a current flowing into the bit line when the bit line intermittent charging means is intermittently charged.
AM. 4. A memory device having a matrix structure in which a plurality of memory cells are arranged at intersections of a plurality of pairs of bit lines and a plurality of word lines, wherein each of the memory cells is formed and is opposite to each other. A flip-flop circuit having a pair of output nodes for outputting storage contents having a logic level of; and a flip-flop to the pair of bit lines by selectively conducting in accordance with a signal level of the word line. Bit line connecting means for connecting a pair of output nodes of the circuit, respectively; and a first capacitor section for applying a circuit operating voltage of a predetermined value or more to the flip-flop circuit so that the memory content of the memory cell is held ; Conducting at a first timing so that the circuit operating voltage is maintained at or above the predetermined value,
First switch means for intermittently charging the first capacitor section; second capacitor section selectively connected to the first switch means and charged to a predetermined voltage; conductive at a second timing, and Second switch means for intermittently charging the second capacitor portion to the predetermined voltage; conducting at a third timing different from the second timing, and
A dynamic SRAM, comprising: a third switch means for making the first switch means conductive by the voltage charged in the capacitor part. 5. A memory cell including a flip-flop for storing information and a first capacitor section for applying a circuit operation voltage to the flip-flop so that the stored content is held; and a signal line to which the plurality of memory cells are connected. A second capacitor portion that is selectively connected to the second capacitor portion and that is charged to the circuit operating voltage;
A first intermittent charging means for intermittently charging the capacitor portion to a voltage corresponding to the circuit operating voltage; and a second intermittent charging means for intermittently charging the signal line using the voltage charged in the second capacitor portion at a second timing. A dynamic SRAM, comprising: intermittent charging means; and third intermittent charging means for intermittently charging the first capacitor section using the charging voltage of the signal line at a third timing.