JPH09246974A - System and method for encoding control data to clock signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To encode picture control signals to picture element clock signals by providing an encoding circuit for positioning a second transition inside at least one clock cycle to the variable position of a first transition in response to control data. SOLUTION: In this system for encoding control signals to clock signals, 0-114 are given five falling positions 116-120 between voltage levels. In the meantime, the rising position of picture element clocks is only one in each clock cycle. Since control bits are decoded from the picture element clocks, the picture element clocks are sampled at a speed which is 6-folds of the picture element clocks from a PLL(phase locked loop) and the falling position for one of the five combinations of control bits is decided. Thus, it is guaranteed that the rise is present at the same position inside the clock cycle at all times.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to encoding image control signals into pixel clock signals.

[0002]

BACKGROUND OF THE INVENTION Without intending to limit the scope of the invention, its background will be described by way of example in the context of a color display panel having an image size of 768.times.1024 pixels at a frame rate of 60 Hz. The 768 × 1024 pixels are just the active observable area. Besides this, there are blank areas around the observable area and horizontal and vertical sync pulses. The blank area has an additional 180 pixels per line and an additional 32 lines, resulting in an effective image size of 800 x 1204 pixels. Besides this, there are 136 more pixels per line during horizontal sync and 6 more lines during vertical sync. Therefore, the effective image size is 806 × 1340. At a refresh rate of 60 Hz, an 806 × 1340 pixel has 64,8 per second.
A pixel speed of 02,400 pixels is required. A color image with 8 bits for each of red, green and blue, and 3 bits for three control lines is about 65 MHz for a 768 x 1024 image on a notebook computer.
It requires transferring 27 bits / pixel across the hinge.

[0003]

SUMMARY OF THE INVENTION Generally speaking, in one form of the invention, a system for encoding control data into a clock signal includes at least one clock cycle in the clock signal and at least one clock cycle in the clock signal. Within one clock cycle, from the first voltage level to the second
A first transition in a first position within the at least one clock cycle and a second transition from a second voltage level in the at least one clock cycle. A second transition having a variable position within the clock cycle, the encoding circuit locating the second transition at a variable position in response to control data. Have.

[0004]

DESCRIPTION OF THE PREFERRED EMBODIMENT Corresponding reference numerals and characters refer to the same parts throughout the drawings unless otherwise specified.

The architecture of the preferred embodiment of the send and receive function of the image data transfer is shown in FIG. FIG. 1 includes a transmitter 126 and a receiver 128. Transmission device 1
26, 6-bit latches 130-134, serializers 135-139, stepping up the pixels by a factor of 6, respectively.
X PLL 142, control bit encoder 144 for converting three control bits into a set of six bits, differential driver 1
46-150, image data input lines 152-155 each including six parallel lines, pixel clock line 157, control line 159 including three control lines, and latches 130-133 are coupled to a serializer 146-149. In addition, the lines 161-164 including the six lines and the control bit encoder 144 are connected to the serializer 1 respectively.
Coupled to 39, includes line 166 containing six lines, 6X clock line 168 and five LVDS pairs 170-174. The receiver 128 includes differential amplifiers 180-184,
Deserializer 186-190, Latch 192-196, 6
XPL 198, control signal decoder 200, deserializer 186-189 are coupled to latches 192-195, and lines 202-205, each containing six lines, deserializer 190 are coupled to decoder 200. Line 207, which includes four lines, and decoder 200 coupled to latch 196.
Lines 209 including 6 lines, 6X clock lines 211, 6 each
Image data output lines 213-216 including parallel lines of books,
Control signal output line 218 including three lines, pixel clock
Refresh amplifier 220 and pixel clock output line 22
2 inclusive.

The preferred embodiment architecture of FIG. 1 uses a low voltage differential signal (LVD) to move image data across a notebook computer hinge.
S) Use serial lines 170-174. LVDS is a difference because it is more immune to noise and easier to shield. Since the LVDS has a small signal fluctuation and the rise time is controlled, the data can be transferred at a data rate higher than that of the TTL. The preferred embodiment system uses four LVDS lines 170-173 to carry 24 bits across the hinge. By operating at 6 times the pixel clock speed (for example, 6 × 65 MHz is 390 MHz), each LVD
6 bits are transmitted by the S line. In addition, a pixel clock is transmitted across the hinge on one LVDS line 174.
For this reason, a total of 5 LVDS lines are required, of which 4 are
A book carries data at 390 Mbaud, one book at 65
It has a clock of MHz.

24-bit image data is latched in the circuit of FIG. 1 by the pixel clock. Phase locked loop 14
2 steps up the pixel clock by a factor of 6. 65
For pixel clocks operating at MHz, the phase-locked loop steps up the frequency to 390 MHz. The stepped up clock rate is used to clock a bank of four 6-bit parallel-to-serial converters (serializers) 135-138. Each serializer 135-138
Converts parallel 6 bits into a serial 6 bit stream. LVD with 4 serial streams and pixel clock
It is delivered via the S driver 146-150.

To receive LVDS serial pixel data and convert it to parallel 24 bits at pixel clock rate,
The process described above is reversed. 4 LVDS pairs 170-
Each of 173 is received and sent to one of the serial-to-parallel converters (deserializers) 186-189. Upon receiving the LVDS pixel clock, PLL 198 steps up the pixel clock by a factor of six. The stepped up clock speed clocks the deserializer 186-189,
These deserializers feed four sets of 6-bit parallel data pins at the pixel clock rate.

The preferred embodiment of FIG. 1 encodes 3 bits of control information into the pixel clock. The three control bits encoded in the pixel clock represent horizontal sync, vertical sync and data enable. (The inverse of the data capability is also called erase.) There are 8 possible combinations of 3 bits, but only 5 of them are used for 3 control bits. The five combinations for data enable, horizontal sync and vertical sync are 000, 001, 010, 0 in this order.
11 and 111. The other three combinations (100, 1
01 and 110) are not used.

The time diagram of FIG. 2 shows a typical timing relationship for the three control bits. The timing signal 100 is vertical synchronization. The timing signal 102 is horizontal synchronization. The timing signal 104 is data enabled. As shown in FIG. 2, the data enable signal 104 is the vertical sync 100.
And only while the horizontal sync 200 is inactive. Therefore, there are only 5 valid combinations of 3 control bits.

In the preferred embodiment, five combinations of three control bits (horizontal sync, vertical sync and data enable) are encoded in the LVDS pixel clock. PL on the receiving side
Since the L 198 phase detector is designed to work on the rising edge of the pixel clock, the duty cycle of the pixel clock is irrelevant. The falling edge of the pixel clock can be anywhere within the clock cycle. By choosing five discrete positions within the pixel clock cycle that fall, one can easily encode five combinations of three control bits into the pixel clock.

FIG. 3 shows five different positions 116 on the trailing edge.
5 pixel clock cycles 110 with -120-
114 is shown. As shown in FIG. 3, there is only one rising edge of the pixel clock in each clock cycle. To decode the control bits from the pixel clock,
The pixel clock can be sampled at six times the rate of the pixel clock from PLL 198 to determine the falling position for one of the five control bit combinations.

The preferred embodiment encoding circuit 144 is shown in FIG. The circuit of FIG. 4 has an "and" gate 230,
232, 234, "or" gates 236, 238, 24
0 and 242 (one-input “OR” gate 242 is a buffer), data enable input line 244, vertical sync input line 2
46, horizontal sync input line 248, six parallel output lines 250
-255, V (high) node 258 and V (low) node 260. The last of the 6 bits to serialize (clause 260) is always low, and the first of the 6 bits (clause 258) is always high. This ensures that the rising edge is always in the same position in the clock cycle. The circuit of FIG.
1 of 5 positions to place the falling edge of the VDS pixel clock
It only decides one. If any of the three invalid combinations of control bits is applied to the circuit of FIG. 4, the encoding is "111" (data enable is active, horizontal sync is inactive, vertical sync is inactive). State) is a valid combination.

Three control bits are provided by 1159 to the sign circuit 144. Encoding circuit 144 provides encoded control signals on six parallel lines 166. The serializer 139 converts the parallel 6 bits into a serial 6 bit stream. This serial stream is the LVDS driver 150
Sent out through.

The decoding circuit 200 of the preferred embodiment is shown in FIG. The circuit of FIG. 5 has an "and" gate 280,
282, inverter 284, "or" gate 286, 2
88, 290, data enable output line 292, vertical synchronization output line 294, horizontal synchronization output line 296, and input line 300-3.
Including 03. The data on the input lines 300-303 correspond to the data on lines 251-254 shown in FIG. 4, respectively.

A deserializer 190 deserializes the LVDS pixel clock and outputs the encoded control signal to the four parallel lines 2.
07. The control signal decoder 200 converts the 4 bits from the pixel clock deserializer 190 into the 3 control bits on line 209.

One advantage of the preferred embodiment is that 6X P
In LL, a pixel clock of 65 MHz only requires a speed of 390 Mbaud on the LVDS line. This is within the capabilities of current 3-volt LVDS technology.

The foregoing has described some preferred embodiments.
It should be understood that the scope of the present invention is different from the one described above, but also includes the embodiments included in the claims. For example, the control signal may be composed of one line instead of three. The control data for a single line can be encoded in the clock signal as described in the preferred embodiment. One control line can be transmitted as a subset of three control lines. With vertical and horizontal synchronization disabled, one control line can be input to the data enable input line. This allows the two states of one control line to be encoded in the pixel clock using the circuit described above for the preferred embodiment.

The clock encoder circuit of FIG. 4 and the clock decoder circuit of FIG. 5 are just one of many possible forms for implementing the desired clock encoding and decoding. The five states of the control signal can be assigned to one position on the falling edge of the clock signal in any desired order.

Although the present invention has been described with reference to embodiments, this description should not be construed as limiting the invention.
From the above description, various modifications and combinations of the illustrated embodiments, as well as other embodiments of the invention, will be readily apparent to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover such modifications or embodiments.

In connection with the above description, the following items will be further disclosed. (1) In a system for encoding control data into a clock signal, at least one clock cycle of the clock signal and a first voltage level to a second voltage within the at least one clock cycle A transition to a level at a first position in the at least one clock cycle and a transition from a second voltage level to a first transition in the at least one clock cycle. A second transition having a variable position within the clock cycle that is a transition to a voltage level, and an encoding circuit that positions the second transition at the variable position in response to control data. System to have. (2) The system according to item 1, wherein the first voltage level is lower than the second voltage level. (3) The system according to the item (1), wherein the control data is composed of three control bits. (4) The system according to the third item, wherein the three control bits have five valid combinations. (5) The system according to item 4, wherein the variable position is one of five discrete positions. (6) The system of claim 5, wherein each of the five valid combinations is encoded in a corresponding one of the five discrete positions.

(7) In a device for transmitting a video signal, a video signal bit having parallel image data bits and at least one control bit, and at least one image converting the parallel image data bit into serial data. A serializer, an encoding circuit for converting the at least one control bit into parallel clock encoded data, a control signal serializer for generating an encoded clock signal, the at least one image serializer and a control signal And a clock signal for clocking the serializer. (8) In the device according to item 7, the at least 1
An apparatus having at least one differential driver for receiving corresponding serial data from one image serializer. (9) The apparatus of claim 7 having at least one latch coupling said parallel image data bits to at least one corresponding image serializer. (10) A device according to claim 7, which has a differential driver for receiving an encoded clock signal. (11) The apparatus according to item 7, which has a phase locked loop for generating the clock signal. (12) The apparatus according to item 7, wherein the image serializer converts 6 parallel image bits into serial data.

(13) In a method of encoding a control signal into a clock signal, the clock signal has at least one clock cycle, each clock cycle from a first voltage level to a second voltage level. Has a first transition to a second voltage level and a second transition from a second voltage level to a first voltage level and holds the first transition of each clock cycle in one position, A method comprising encoding a control signal into a clock signal by changing position. (14) In a method of transferring a video signal, control data is encoded into a clock signal to generate an encoded clock signal, parallel video data is converted into serial data, and the serial data and the encoded clock signal are differentiated. A method comprising the steps of: transferring over a transmission line, converting serial data on the differential line into parallel data, and decoding the encoded clock signal to obtain control data and a clock signal. (15) A system for encoding control data into a clock signal has at least one clock
A cycle and a first voltage level transition within the at least one clock cycle from a first voltage level to a second voltage level in a first position of the at least one clock cycle. A transition and the at least one
A second transition from a second voltage level to a first voltage level within one clock cycle and having a variable position within the clock cycle, and in response to the control data, And a coding circuit for positioning the second transition at a variable position.

[Brief description of drawings]

FIG. 1 is a preferred embodiment architecture for image data transfer.

FIG. 2 is a time diagram of an image data control signal.

FIG. 3 is a diagram of a pixel clock signal having five different falling positions.

FIG. 4 is a logic circuit diagram of the control signal encoder of FIG.

5 is a logic circuit diagram of the control signal decoder of FIG.

[Explanation of symbols]

 100, 102, 104 control bits 110-114 rising 116-120 falling 144 coding circuit

Claims (3)

[Claims] 1. A system for encoding control data into a clock signal, wherein at least one clock cycle of the clock signal and within the at least one clock cycle from a first voltage level to a second voltage level. A first transition in a first position within the at least one clock cycle and a second transition from a second voltage level in the at least one clock cycle. A second transition having a variable position in the clock cycle and a second transition having a variable position in the clock cycle and positioning the second transition at the variable position in response to control data. A system having and. 2. A device for transmitting a video signal, wherein a video signal bit having parallel image data bits and at least one control bit and at least one image serial converting said parallel image data bit into serial data. A coding circuit for converting the at least one control bit into parallel clock coded data; a control signal serializer for generating a coded clock signal;
An image serializer and a clock signal for clocking the control signal serializer. 3. A method of encoding a control signal into a clock signal, wherein the clock signal has at least one clock cycle, each clock cycle being a first clock cycle.
Has a first transition from a second voltage level to a second voltage level and a second transition from a second voltage level to a first voltage level, and has a first position of each clock cycle in one position. By keeping the transition and changing the position of the second transition,
A method comprising encoding a control signal into a clock signal.