JPH09231122A - Processor system - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To guarantee the normality of access to a dual port memory of a processor that does not have a function of waiting for memory access. When a processor 2 executes a memory access, it reads the state of SRFF8 from an input terminal 11. SRFF8
Is set by a signal from the! BUSY terminal 6L of DPRAM1 indicating an access conflict. Processor 2 is SRFF8
If the state is set, the value in SRFF8 is reset by the output from the output terminal 12, and the same area of DPRAM1 is accessed again. The input of the R /! W terminal of DPRAM1 is set while SRFF8 is set by OR9.
Fixed to Hi to prevent writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access technique in a system in which one processor shares one memory.

[0002]

2. Description of the Related Art As a system for sharing one memory between two processors, there are a multiprocessor system and a gateway device for converting a communication protocol between different networks.

In such a system, a dual port memory (hereinafter referred to as DPRAM) which can be simultaneously accessed by two processors is often used as a memory shared by the two processors. However, even with such a DPRAM, two processors cannot access the same address area at the same time.

Therefore, in many cases, the DPRAM is provided with a function of issuing a busy signal to the later-arriving processor indicating that the access is impossible when two processors read or write the same address area in duplicate. Using such a DPRAM and two processors with the function to delay and delay the memory access according to the busy signal from the DPRAM, normal memory can be used even when access to the same address area of the DPRAM conflicts. A system capable of accessing can be realized.

However, there are cases where it is necessary to use a processor that does not have a memory access wait function for applying a wait to the memory access and delaying it. This is the case where one of the processors needs a special function, and as a processor having such a special function, only a processor having no memory access wait function is realized and supplied.

If a processor without such a memory access wait function is used, normal memory access cannot be guaranteed as it is.

Therefore, in Japanese Unexamined Patent Publication No. 5-20212, DPRAM
Generates an error signal based on the busy signal to the processor that does not have the memory access wait function and notifies the processor that does not have the memory access wait function.
It has been proposed to prohibit that memory access.

[0008]

SUMMARY OF THE INVENTION
In the system described in Japanese Patent Laid-Open No. 5-20212, it is not possible to completely eliminate contention for memory access to DPRAM. busy
During the time lag between the signal being output and the processor itself that does not have the memory access wait function disabling that memory access, memory access to DPRAM remains in conflict, and erroneous data is stored in DPRAM during this time.
May be written to.

In the system disclosed in Japanese Patent Laid-Open No. 5-20212, the memory access to the DPRAM can be eliminated to some extent, but the normality of the memory access of the processor without the memory access wait function is guaranteed. Not done. This is because no means has been taken to guarantee the normality of the prohibited memory access.

Therefore, the present invention is a system in which one memory is shared between two processors, and the normality of memory access is ensured even when a processor having no function of waiting for memory access is used as the processor. It is an object to provide a processor system that can be guaranteed.

[0011]

In order to achieve the above object, the present invention comprises two processors and two ports for respectively accepting the accesses of the two processors, and when the accesses accepted by the two ports compete with each other. And a dual port memory that outputs a busy signal for notifying access conflict from a port that has accepted the access later, and a busy signal is output from one of the two ports. In this case, a processor that has a holding circuit that holds the busy signal and that receives access to the dual port memory at one of the ports is held by the holding circuit after the processor accesses the dual port memory. Read the contents, and the contents held by the holding circuit are busy signals. In some cases, to provide a processor system and having a retry means for accessing the dual port memory described above again.

According to the processor system of the present invention, the access is retried depending on the presence / absence of the busy signal held in the holding circuit even if the processor does not have the function of waiting the memory access. Normal memory access to the dual port can be performed.

Further, the dual port memory is responsive to a write instruction signal input from a processor whose access is accepted to the two ports.
In the case of a dual port memory that accepts write access to the dual port memory at the port to which the write instruction signal is input, if the content held in the holding circuit is a busy signal, If a suppressor circuit that suppresses the input of the write instruction signal output from the processor that accepts access to the dual port memory to the one port is provided, immediately suppress the write access of the last arrival in the case of access conflict. It is possible to prevent erroneous data from being written to DPRAM.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a processor system according to the present invention will be described below.

First, a first embodiment will be described.

FIG. 1 shows the configuration of a processor system according to the first embodiment.

In FIG. 1, a dual port memory (hereinafter referred to as "DPRAM") 1 has a port on the right side in the drawing,
Processor 3 with wait function for memory access
Are connected by an address bus 4R and a data bus 5R. An R /! W signal output terminal 16 of the processor 3 is connected to a read / write instruction signal (hereinafter referred to as "R /! W signal") input terminal 15 of the right port. Also,
When two processors 2 and 3 access the same address area and the processor 3 arrives last, the BUSY signal (Low signal) is output from the right port.
! The BUSY terminal 6R has a memory ready (MR) for the processor 3.
It is connected to the terminal 10. Memory ready (MR) terminal 10
When the! BUSY signal (Low signal) is input to the processor 3, the processor 3 causes the memory access to wait. However, in this specification, before the input / output terminal of the signal that treats the Low signal (logical value 0) as significant, which is represented by an overline in the drawing, due to a technical problem in writing a sentence ,! It is indicated by adding.

On the other hand, the port on the left side of the DPRAM 1 in the figure is
A processor 2 having no wait function for memory access is connected by an address bus 4L and a data bus 5L. When the two processors 2 and 3 access the same address area and the processor 2 arrives last, the! BUSY signal (Low signal) is output from the left port! BUSY terminal. 6L and left port R
The /! W terminal 14 is connected to the! BUSY signal holding circuit 7.

The! BUSY signal holding circuit 7 is a set-reset flip-flop (hereinafter referred to as "SRF") capable of holding a signal.
8) and an OR gate 9. ! BU
The SY terminal 6L is connected to the set input terminal (! S) of the SRFF 8, and the SRFF 8 is set by the! BUSY signal when there is a memory access conflict. Also, SRFF8 output terminal (Q)
Is connected to the input terminal 11 of the processor 2 so that the contents held by the SRFF 8 can be taken from the processor 2. In addition, the output terminal 12 of the processor 2
, And the reset input terminal (! R) of SRFF8 is connected,
Processor 2 can optionally reset SRFF8.

The R /! W signal output terminal 1 of the processor 2
3 is connected to the OR gate 9 together with the output terminal (Q) of the SRFF 8, and the output of the OR gate 9 is connected to the R /! W signal input terminal 14 of the left port of the DPRAM 1.

The operation of memory access in such a processor system will be described below.

First, FIG. 2 shows a procedure of memory access to the DPRAM 1 of the processor 2 having no wait function for memory access.

As shown in the figure, the processor 2 having no wait function first executes memory access (20).
0). In this memory access, a single address of the DPRAM 1 may be accessed, or a plurality of addresses may be continuously accessed. Then, SRFF8 from the input terminal 11 to confirm whether the execution was normal.
(201). At this time, if a memory access conflict occurs in the DPRAM 1 and the processor 2 arrives later, the SRFF 8 is set by the Low signal output to the! BUSY terminal 6L.

If the input terminal 11 is High (logical value 1), the memory access may not have been performed normally, so the value in SRFF8 is set to the output terminal 12 of the processor 2.
After resetting by the output from (202), memory access is performed again for the same area (200).

The above processing is repeated until the value of the input terminal 11 is Low (logical value 0) in step 201, and the value of the input terminal 11 is Low (logical value 0).
If it is determined that the process proceeds to the next process (203), the memory access procedure shown in FIG. 2 can be realized by a program shown in FIG. 3, for example.

The first line of this program shows the process of writing the SRC data to the address DST of the DPRAM 1, and the second line is the third line while the value of the input terminal 11 is High (logical value). It indicates that the processing of the fourth and fourth rows is repeated. Then, in the third line, the process of outputting Low (logical value 0) from the output terminal 12 and resetting SRFF8 is performed.
The row shows the processing of writing the SRC data to the address DST of the DPRAM 1 as in the first row.

As described above, in the present embodiment, since the processor 2 does not have the memory access wait function, it is necessary to add to the processing performed by the processor 2 that the processor not having the memory access wait function. The access processing to the DPRAM 1 of No. 2 is only the procedure shown in FIG. Further, for example, if the program of FIG. 3 is prepared as a module that receives SRC and DST as arguments that are called when the DPRAM 1 is accessed, the burden of creating the program for realizing the procedure of FIG. Can be made smaller.

Now, FIG. 4 shows a time chart of access to the DPRAM 1 in the processor system according to the present embodiment.

If the memory access of the processor 3 is performed to the same address while the processor 3 is performing the memory access as shown in (1) and (2) of FIG. 4, (3)
To the! BUSY terminal 6L on the processor 2 side as shown in!
BUSY signal (LOW) is output. This! BUSY signal is held by SRFF8, and the output signal of SRFF8 becomes as shown in (4). Processor 2 gets the output of SRFF8, and
The signal is detected, SRFF8 is reset, and memory access is again performed to the same address as described above.

Here, depending on the memory access timing of the processor 2, if access to the DPRAM of the processor 2 is allowed immediately after the! BUSY signal 6L is released, when writing to the memory, the There is a risk of writing abnormal data such as the shaded area in 2). Therefore, in the first embodiment, the signal obtained by ORing the! BUSY signal held by the SRFF 8 by the OR gate 9 and the R /! W signal of the processor 2 shown in (5) is used as the R /! W signal of the DPRAM 1. Input terminal 14
Give to. This causes memory access contention! BUS
DPRAM from Y signal output to writing at retry
Inhibit writing to 1.

The first embodiment of the present invention has been described above.

The second embodiment of the present invention will be described below.

FIG. 5 shows the configuration of the processor system according to the second embodiment.

As shown in the figure, in the processor system according to the second embodiment, the connection between the processor 3 having the memory wait function and the DPRAM 1 is the same as that of the processor system according to the first embodiment (see FIG. 1). Processor 3
And DPRAM1 connection is the same.

Further, the processor 2 having no memory wait function and the DPRAM 1 are connected as follows.

That is, the processor 2 having no wait function for memory access is connected to the port on the left side of the DPRAM 1 in the figure by the address bus 4L and the data bus 5L.

The! BUSY terminal 6L of the left port of the DPRAM 1 is connected to the set input terminal (! S) of the set / reset flip-flop (SRFF) 8. SRFF8 output
(Q) is connected to the uppermost terminal (D7) of the data bus of the processor 2 via the tristate buffer 25. The reset input terminal (! R) of the SRFF 8 is also connected to the uppermost terminal (D7) of the data bus of the processor 2 via the tristate buffer 24.

The tristate buffers 24 and 25 are ANDed
The address that the processor 2 outputs to the address bus 4L via the gates 21, 22, and 23, and the processor 2 outputs R /! W.
A signal output to the output terminal 13 controls a state in which the output has a high impedance and a state in which the output is performed according to the input (for convenience, referred to as “through state”). Although not shown in the figure, the seven terminals (D0-D7) except the highest-order terminal (D7) of the data bus of the processor 2 are respectively
Hi (logical value 1) is connected through seven tristate buffers controlled to the same state as the tristate buffer 25.

The operation of memory access in such a processor system will be described below.

First, FIG. 6 shows a procedure of memory access to the DPRAM 1 of the processor 2 having no wait function for memory access.

The processor 2 first executes memory access (601). Then, since it is unknown whether or not the execution was normal, access is made so as to read the data at the address of D000 (602). Then, in FIG. 5, the upper 4 bits of the address bus (A15, A14, A13, A
The output of the 4-input AND gate 21 connected to (12) (A13 is inverted) becomes Hi. The least significant bit (A0) of the address bus and the R /! W signal are connected to the 3-input AND gate 22 together with the output of the 4-input AND gate 21, and the address D0
When 00 is read, the output of the 3-input AND gate 22 becomes Hi. On the other hand, the least significant bit (A0) of the 3 address buses and R /! W
The signal is inverted and output with the AND gate 21 with 4 inputs
Since it is connected to the 3-input AND gate 23, the output of the 3-input AND gate 23 when the address D000 is read
It goes low. As a result, the tristate buffer 25 is in the through state, the tristate buffer 24 is in the high impedance state, the output of the SRFF 8 is input to the uppermost terminal of the data bus, and the processor 2 can recognize the output state of the SRFF 8.

Here, if the processor 2 is the last one at the time of contention for memory access, the! BUSY terminal (Q) is set to Lo.
w is output, and the signal is the set input terminal (! S) of SRFF8.
And set SRFF8. Therefore, if the data read from the address D000 by the processor 2 in step 602 is 255, it can be determined that the memory access may not have been normally performed. On the contrary, if the data read from the address D000 is 127, it can be determined that the memory access is normally executed.

Then, next, it is judged whether or not the data read in step 602 is 255 (603), 2
If it is not 55, it is determined that the memory access is normally performed, and the process proceeds to the next process.

On the other hand, when the data read in step 602 is 255, 127 is written in the address D001 (604). By this writing, the output of the 4-input AND gate 21 becomes Hi. The output of the 3-input AND gate 22 becomes low. On the other hand, the 3-input AND gate 23 becomes High. As a result, the tristate buffer 24 is in the through state, the tristate buffer 25 is in the high impedance state, and the state of the highest-order terminal of the data bus is SRFF.
8 is input to the reset terminal (! R) and SRFF8 is reset.

Then, memory access is performed again to the same address of DPRAM1 (601).

Further, like the first embodiment described above,
The signal obtained by ORing the! BUSY signal held by the SRFF 8 by the OR gate 9 and the R /! W signal of the processor 2 with the DPRAM 1
The R /! W signal input terminal 14 is used to prevent writing to the DPRAM 1 from output of the! BUSY signal due to memory access conflict to writing at the time of retry.

The memory access procedure shown in FIG. 6 can be realized by a program shown in FIG. 7, for example.

In the first line of this program, the variable Y
Is defined as 127. The second line shows the process of writing the SRC data to the address DST of the DPRAM 1, and the third line shows the process of reading the data from the address D001 and setting this value as the value of the variable X. The fourth line indicates that the processes of the fifth and sixth lines are repeated while the value of X is 255. The fifth line shows the process of writing Y (127) to the address D001 and resetting SRFF8, and the sixth line shows the process of writing the SRC data to the address DST of DPRAM1 as in the first line. There is.

As described above, also in the second embodiment, the normality of the memory access can be guaranteed in the processor system using the processor having no memory access wait function, as in the first embodiment.
The second embodiment can be realized even when the input / output terminals other than the data bus of the processor having no memory access wait function cannot be used as in the first embodiment.

Although the case where only one of the two processors does not have the memory access wait function has been described above, even if both of the two processors do not have the memory access wait function, The two embodiments described above can be similarly applied. That is, in this case, the connection between each processor and the DPRAM may be made in the same manner as the connection between the processor and the DPRAM in the first and second embodiments.

[0051]

As described above, according to the present invention, even in a system in which one memory is shared between two processors and a processor having no memory access wait function is used, A processor system capable of guaranteeing normality of memory access can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a processor system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a procedure of memory access according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a program that realizes a memory access according to the first embodiment of the present invention.

FIG. 4 is a time chart showing memory access timing in the processor system according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a processor system according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a memory access procedure according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a program for realizing a memory access according to the second embodiment of the present invention.

[Explanation of symbols]

1 ... Dual port memory, 2 ... Processor without wait function, 3 ... Processor with wait function, 4
L, 4R ... Address bus, 5L, 5R ... Data bus, 6
L, 6R ...! BUSY signal output terminal, 7, 20 ...! BUSY signal holding circuit, 8 ... Set / reset flip-flop, 9 ... 2
Input OR gate, 10 ... Memory ready terminal, 11 ... Input terminal, 12 ... Output terminal, 13, 14 ... R /! W signal output terminal,
21 ... 4-input AND gate, 22, 23 ... 3-input ND gate, 24, 25 ... Tristate buffer

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Koji Ikeda 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (5)

[Claims] 1. A processor comprising two processors and two ports for respectively accepting the accesses of the two processors, and when the accesses accepted by the two ports conflict, the conflict of the access is accepted from the port accepting the access later. A processor system including a dual port memory that outputs a busy signal for notification, comprising a holding circuit that holds the busy signal when the busy signal is output from one of the two ports. The processor that accepts the access to the dual port memory at the one port reads the content held by the holding circuit after the execution of the access to the dual port memory by the processor, and holds the content held by the holding circuit. If the content is a busy signal, the dual port memory Processor system and having a retry means for performing re-access to. 2. The processor system according to claim 1, wherein the processor accepting an access to the dual port memory at the one port receives the holding data after executing the access to the dual port memory of the processor. A processor system comprising means for initializing the content held by the holding circuit when the content held by the circuit is a busy signal. 3. The processor system according to claim 2, wherein the dual port memory is configured to be a dual port memory in response to a write instruction signal input from a processor whose access is accepted to the two ports. Is a dual-port memory that accepts the write access of at the port to which the write instruction signal is input, and when the content held in the holding circuit is a busy signal, the one port writes to the dual-port memory. A processor system comprising: a suppressor circuit that suppresses an input of a write instruction signal output from a processor to which access is accepted to the one port. 4. The processor system according to claim 2, wherein the content held in the holding circuit is initialized in response to an access to a specific address of the processor, which accepts access to the dual port memory at the one port. In response to a read access to a specific address of the processor that accepts access to the dual port memory at the one port and an initialization circuit to be converted, the content held in the holding circuit is used as read data for the read access by the processor. A processor system comprising a relay circuit for sending. 5. The processor system according to claim 2 or 3, wherein the processor accepting access to the dual port memory at the one port has an input terminal for reading the content held by the holding circuit, A processor system comprising: an output terminal for outputting a signal for initializing a holding circuit, separately from a terminal used for accessing the dual port memory.