JPH09200035A - Level conversion circuit - Google Patents

Abstract

(57) An object of the present invention is to provide a level conversion circuit for level shifting both H level and L level between different power supply systems. A digital signal Vin from a power supply system 1 is received by an N-channel MOS transistor Q3 and a P-channel MOS transistor Q4. Vin = "1" (V
CC1), Q3 is turned on and P channel M
When the OS transistor Q2 is turned on, VCC2 (power supply system 2
"1" level) is output as Vout.
On the other hand, when Vin = “0” (VSS1), Q4 is turned on, the N-channel MOS transistor Q6 is turned on, and VSS2 (“0” level in the power supply system 2) is V
Output as out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit for converting a logic level of a digital signal. For example, in a dynamic semiconductor memory device, when a boosted voltage and a negative voltage generated from an external power supply are used as a word line drive signal for the purpose of reducing current consumption during standby, improving data retention time, etc. Used.

[0002]

2. Description of the Related Art As a conventional level conversion circuit of this type, there is one shown in FIG. 3 as disclosed in, for example, Japanese Patent Laid-Open No. 3-98314. The disclosure is for transmitting a digital signal of a high voltage power supply system from a digital signal of a low voltage power supply system. What is shown in FIG.
It is formed of a MOS circuit, and in the figure, Q23, Q
Reference numeral 24 denotes N-channel MOS transistors Q21 and Q22 for receiving the digital signal Vin from the low voltage power supply system.
Is a P-channel MOS transistor. To each gate of the MOS transistors Q23 and Q24, a digital signal on the low voltage power supply side, that is, a signal having a binary level between VCC1 and VSS is inverted and inputted.
The sources of the OS transistors Q23 and Q24 are grounded (V
SS) has been done. In addition, the MOS transistor Q23,
Each output side of Q24, that is, each drain and high-voltage power supply V
The MOS transistors Q21 and Q2 are connected to CC2.
2 is inserted, and the gates of the MOS transistors Q21 and Q22 are set to the MOS transistor Q24,
It is connected to each drain of Q23. And MOS
A digital signal on the high voltage power supply side, that is, a signal having a binary level between VCC2 and VSS is taken out as an output Vout from the drain of the transistor Q24. Here, each of the MOS transistors Q21 to Q2
For 4, the capacity ratio is set as follows. That is, when the MOS transistor Q23 is turned on and the MOS transistor Q23 is turned on, the potential of the node N1 needs to be lowered to such an extent that the MOS transistor Q22 is turned on.
Since the OS transistor Q24 is in the off state, the gate potential of the MOS transistor Q21 rises, the MOS transistor Q21 gradually turns off, and eventually, the digital signal between different power supply voltages can be transmitted. Similar condition is M
The same applies to the OS transistors Q22 and Q24. Therefore, in order to satisfy such a condition, the MOS transistor Q
It is only necessary to set the driving capabilities of 21, 21 and Q22 relatively weak and the capabilities of the MOS transistors Q23 and Q24 relatively strong.

[0003]

The above-mentioned prior art is not limited to the conversion of a digital signal in a low voltage power supply system into a digital signal in a high voltage power supply system, but is obviously in a high voltage power supply system. It is also possible to convert a digital signal into a digital signal of a low voltage power supply system. However, it was limited to the conversion of the "1" logic level, and the "0" logic level was not converted.

The present invention provides a level conversion circuit capable of level conversion of both "1" and "0" logic levels.

[0005]

Power supply system 1 having power supply voltages of VCC1 (high voltage side) and VSS1, and VCC2
(High voltage side) and power supply system 2 having a power supply voltage of VSS2
Regarding the conversion of the logic level between the different power supply systems, "1" logic level VCC1 and "0" logic level VSS1 in the power supply system 1 to "1" logic level VCC2 and "0" logic level V in the power supply system 2, respectively.
In order to convert to SS2, an active element that receives a digital signal output from the power supply system 1 is composed of a third N-channel MOS transistor and a fourth P-channel MOS transistor, and the third N-channel MOS transistor and the fourth N-channel MOS transistor
The digital signal output from the power supply system 1 is input to each gate of the P-channel MOS transistor of, the source of the third N-channel MOS transistor is connected to the power supply VSS1 on the low voltage side of the power supply system 1, and the drain is connected to the power supply system 2. Connected to the drain of the first P-channel MOS transistor inserted between the high-voltage side power supply VCC2 and the source of the first P-channel MOS transistor connected to the high-voltage side power supply VCC2 of the power supply system 2. The gate is connected to the drain of the second P-channel MOS transistor inserted between the power supply VCC2 on the high voltage side of the power supply system 2 and the output to the power supply system 2, and the source of the second P-channel MOS transistor is the power supply. It is connected to the power supply VCC2 on the high voltage side of system 2 and the gate is connected to the drain of the first P-channel MOS transistor. The source of the fourth P-channel MOS transistor is connected to the power supply VCC1 on the high voltage side of the power supply system 1,
The drain is connected to the drain of the fifth N-channel MOS transistor inserted between the low-voltage power supply VSS2 of the power supply system 2 and the source of the fifth N-channel MOS transistor is the low-voltage power supply of the power supply system 2. The sixth N-channel MO is connected to VSS2 and has a gate inserted between the power supply VSS2 on the low voltage side of the power supply system 2 and the output of the power supply system 2.
The drain of the sixth N-channel MOS transistor is connected to the drain of the S-transistor, the source of the sixth N-channel MOS transistor is connected to the power supply VSS2 on the low voltage side of the power supply system 2, and the gate is the fifth N-channel M.
The digital signal of the power supply system 2 is output from the node connected to the drain of the OS transistor and the drain of the second P-channel MOS transistor and the drain of the sixth N-channel MOS transistor.

According to the above invention, the third and fourth MOSs are provided.
A digital signal on the power supply system 1 side is input to each gate of the transistor, and one of the third and fourth MOS transistors is turned off and the other is turned on, whereby each gate potential of the second and sixth MOS transistors is turned on. Is controlled,
The second and sixth MOS transistors are turned on or off, and the digital signal level of the power supply system 2 is determined. That is, a voltage of VCC2 is output as the "1" logic level and a voltage of VSS2 is output as the "0" logic level.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 shows a "1" logic level V in the power supply system 1.
It is an embodiment of a level conversion circuit for converting from CC1 and “0” logic level VSS1 to “1” logic level VCC2 and “0” logic level VSS2 in the power supply system 2, respectively. In this figure, Q1, Q2 and Q4 are P channel MOS transistors, and Q3, Q5 and Q6 are N channel MOS transistors. A digital signal from the power supply system 1, that is, a signal Vin having a binary level between VCC1 and VSS1 is input to the gates of the MOS transistors Q3 and Q4, and the source of Q3 is the power supply system 1.
Of the power supply system 2 is connected to the VSS1 of
Connect to the drain of Q1 inserted between CC2 and
The source of is connected to VCC2 of power supply system 2, the gate of Q1 is connected to the drain of Q2 inserted between VCC2 of power supply system 2 and the output Vout, and the source of Q2 is connected to VCC2 of power supply system 2. , Q2 have their gates connected to the drain of Q1. The source of Q4 is connected to VCC1 of the power supply system 1, the drain of Q4 is connected to the drain of Q5 inserted between VSS2 of the power supply system 2, and the source of Q5 is the power supply system 2
Of the power supply system 2 is connected to VSS2 of
Connected to the drain of Q6 inserted between S2 and the output Vout, the source of Q6 is connected to VSS2 of the power supply system 2,
The gate of Q6 is connected to the drain of Q5, and a level-converted digital signal is output from the node at which the drain of Q2 and the drain of Q6 are connected.

When the digital signal from the power supply system 1 is "1" logic level, that is, the VCC1 voltage, Q3 is turned on and the node N1 is pulled down to VSS1, so Q2 is turned on and the output voltage of the power supply system 2 is VCC2, That is, the logical level becomes "1". Other MOS transistors Q1, Q
4, Q6 is off and Q5 is on. On the contrary, the digital signal from the power supply system 1 is the logic level "0", that is, VS.
In the case of the S1 voltage, since Q4 is turned on and the node N5 is pulled up to VCC1, Q6 is turned on and the output voltage Vout of the power supply system 2 becomes VSS2, that is, the logic level “0”. The other MOS transistors Q2, Q3, Q5 are off,
Q1 is on. Here, the MOS transistor Q1,
The drive capacity of Q5 is relatively weak and the MOS transistor Q
The capacities of 3 and Q4 may be set relatively strong. As a result, it is possible to provide a sufficient margin for process variations in a wide power supply voltage range. Further, the through current does not constantly flow. Further, since only six MOS transistors are required, the number of transistors does not increase as compared with the conventional one, and level conversion can be performed between different power supply voltages in a wider range. That is, it is apparent that the present invention can be applied to the case where VSS1 is equal to VSS2 (level conversion only on the high voltage side), so that the present invention is a circuit configuration having a wide adaptation range including the conventional circuit configuration (FIG. 3). I can say. Furthermore, the present invention can be applied to the level conversion only when the VSS1 and the VSS2 are different and the VCC1 and the VCC2 are the same, that is, only the low voltage side.

Here, the logic amplitude (VCC before level conversion)
1-VSS1) to the logical amplitude (VCC2 after level conversion)
-VSS2) is large (VCC2> VCC1, VS
S2 <VSS1), the following problems occur. A voltage larger than that of the MOS transistors in other circuits is applied to the MOS transistor in the level conversion circuit shown in FIG. 1 between the gate and the source. That is, the maximum of the MOS transistors in other circuits is (VCC1-VSS
While only 1) is applied, (VCC2-VSS2) is applied at maximum in the level conversion circuit shown in FIG. As it is, the total gate oxide film thickness is limited by the MOS transistor in the level conversion circuit shown in FIG.

The circuit shown in FIG. 2 solves this problem. P-channel MOS transistor Q2 of FIG.
A P-channel MOS transistor Q7 is inserted between the output and Vout, the gate of Q7 is connected to VSS1, the source is connected to the drain of Q2, and the drain is connected to Vout. In addition, the N-channel MOS transistor Q6 of FIG.
And an output Vout, an N-channel MOS transistor Q8 is inserted. The gate of Q8 is connected to VCC1, the source is connected to the drain of Q6, and the drain is connected to Vout. When the output Vout becomes VSS2, the source N2 of the P-channel MOS transistor Q7 becomes (VSS
1-VTP), the voltage of (VCC2-VSS2) was applied to the P-channel MOS transistor Q2 in FIG. 1, whereas in FIG.
Only VSS1 + VTP) is applied. Output Vou
When t becomes VCC2, the source N6 of the N-channel MOS transistor Q8 rises only to (VCC1-VTN), and in FIG. 1, the voltage (VCC2-VSS2) is applied to the N-channel MOS transistor Q6. On the other hand, in FIG. 2, (VCC1-VTN-VSS
Only 2) is applied. Therefore, in either case, the voltage applied to the MOS transistor is reduced.

Next, an example in which the level conversion circuit is applied to a word line drive circuit of a dynamic semiconductor memory device will be described. Normally, a VPP level obtained by boosting an external voltage is applied to a word line when selected, and a ground level (VSS) is applied when it is not selected. However, there is a problem that the data retention time of the memory cell is shortened because the change of the memory cell increases the leak current of the memory cell. In response to this problem, it becomes necessary to lower the word line level when not selected to the ground potential or lower. One example in that case is shown in FIG. In FIG. 4, 1 is a word line selection circuit and 2 is a level conversion circuit of the present invention. The binary output from the word line selection circuit 1, that is, the levels of VCC and VSS are converted into the levels of VPP and VNN by the level conversion circuit 2. VPP and VNN
Are the boost level and the negative voltage level generated from VCC. Q11 and Q12 are large-sized P-channel and N-channel MOS transistors, respectively, and the sources of Q11 and Q12 are VPP and V, respectively.
Connected to NN. Since the word line 3 is directly driven by the inverter constituted by Q11 and Q12, the boosted VPP level is applied when selected, and the VNN level below the ground potential is applied when not selected.

As shown in FIG. 4, word line 3 is connected to the gate of memory cell transistor Q13, and the drain and source of Q13 are connected to bit line 4 and storage node N13 of memory cell capacitor C, respectively. The other node of the memory cell capacitor C is 1 of VCC
Connected to a potential of / 2. "0" data is stored in the memory cell capacitor, that is, storage node N
When the potential of 13 is the ground potential, the subthreshold current of Q13 can be drastically reduced by applying a level below the ground potential to the word line, and the data retention time of the memory cell can be increased.

The power supply system 1 (VCC1, VSS in FIG. 1)
The range in which the level can be converted from 1) to the power supply system 2 (VCC2, VSS2) is VCC1> VSS2 + VTN and VSS.
It is a range of 1 <VCC2-VTP.

[0014]

According to the present invention, only the conversion of the "1" logic level between different power supply systems can be handled in the past, but according to the present invention, in addition to the conversion of the "1" logic level, the conversion of the "0" logic level is performed. Conversion is also possible. That is, the conventional circuit configuration can be applied only when the "0" logic level is the same between different power supply systems, whereas in the present invention, "0" and "0" are provided in the configuration of the same number of transistors as the conventional one. It is applicable even when both of the 1 "logic levels are different.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional level conversion circuit.

FIG. 4 is a circuit diagram when the level conversion circuit of the present invention is applied to a word line drive circuit of a dynamic semiconductor memory device.

[Explanation of reference signs] Q1, Q2, Q4, Q7 P-channel MOS transistors Q3, Q5, Q6, Q8 N-channel MOS transistors

Claims (3)

[Claims] 1. In a logic level conversion circuit between different power supply systems, an active element for receiving a digital signal output from the power supply system 1 is composed of a third N-channel MOS transistor and a fourth P-channel MOS transistor. Then, the digital signal output from the power supply system 1 is input to the gates of the third N-channel MOS transistor and the fourth P-channel MOS transistor, and the source of the third N-channel MOS transistor is connected to the power supply system. 1 is connected to the power supply VSS1 on the low voltage side, and the drain is connected to the drain of the first P-channel MOS transistor inserted between the power supply system 2 and the power supply VCC2 on the high-voltage side. The source of the transistor is connected to the power supply VCC2 on the high voltage side of the power supply system 2,
The gate is a second P channel M inserted between the power supply VCC2 on the high voltage side of the power supply system 2 and the output to the power supply system 2.
It is connected to the drain of the OS transistor, the source of the second P-channel MOS transistor is connected to the power supply VCC2 on the high voltage side of the power supply system 2, and the gate is connected to the first P-channel.
The source of the fourth P-channel MOS transistor is connected to the power supply VCC1 on the high voltage side of the power supply system 1, and the drain of the fourth P-channel MOS transistor is connected to the power supply VSS2 on the low voltage side of the power supply system 2. It is connected to the drain of the fifth N-channel MOS transistor inserted in between, the source of the fifth N-channel MOS transistor is connected to the power supply VSS2 on the low voltage side of the power supply system 2, and the gate is the power supply system. Power source VS on the low voltage side of 2
The sixth N inserted between S2 and the output to the power supply system 2
The drain of the sixth N-channel MOS transistor is connected to the drain of the sixth N-channel MOS transistor, the source of the sixth N-channel MOS transistor is connected to the power source VSS2 on the low voltage side of the power source system 2, and the gate is connected to the drain of the fifth N-channel MOS transistor. A level conversion circuit configured to output a digital signal of the power supply system 2 from a node where the drain of the second P-channel MOS transistor and the drain of the sixth N-channel MOS transistor are connected. . 2. The level conversion circuit according to claim 1, wherein the power supply VSS1 on the low voltage side of the power supply system 1 is connected to the gate between the drain and the output of the second P-channel MOS transistor. 7th P-channel MOS
A transistor is inserted and the sixth N-channel MO
Between the drain and the output of the S-transistor, the gate is connected to the power supply VCC1 on the high voltage side of the power supply system 1 described above.
2. A level conversion circuit in which an N-channel MOS transistor is inserted. 3. The level conversion circuit according to claim 1 or 2 is provided between the word line selection circuit and the word line drive buffer so that the word line selection circuit side operates at the logic level of the power supply system 1. A dynamic semiconductor memory device characterized in that the word line drive buffer side operates at the logic level of the power supply system 2.