JPH09200006A - Shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shaping circuit by which a voltage level of a transmission line is kept stable and a voltage change width of the transmission line is reduced to reduce noise radiation or the like even when a transmission signal is unstable. SOLUTION: An input terminal of a noninverting buffer 2 is connected to a digital signal transmission line 1 and a series circuit consisting of 1st and 2nd impedance elements 3, 4 connects to an output terminal and an intermediate connecting point is connected to the digital signal transmission line 1. When a transmission signal reaches an unstable state from a low level, the digital signal transmission line 1 is pulled down via the 1st and 2nd impedance elements 3, 4. When the transmission signal is at a high level, the voltage level of the digital signal transmission line 1 does not reach the power supply voltage by the series connection of the 1st and 2nd impedance elements 3, 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission path waveform shaping circuit. In particular, it is useful when the transmission signal of the transmission line such as a bus line has an indefinite state.

[0002]

2. Description of the Related Art Conventionally, in a digital signal transmission line having an indefinite state such as a bus line, the voltage level of the digital signal transmission line is fixed to a level such as a high level or a low level with a low impedance. A pull-up resistor, a pull-down resistor, etc. were connected.

Further, in a matching circuit for a digital signal transmission line, in addition to Thevenin termination, it is also disclosed in Japanese Patent Laid-Open No. 3-11621.
As described in Japanese Patent Laid-Open No. 4 and Japanese Patent Application Laid-Open No. 6-61836, there are some which can fix the voltage of the digital signal transmission line to a high level or a low level according to the voltage level of the digital signal transmission line.

FIG. 3 is an explanatory diagram of a digital signal transmission line using a conventional pull-up circuit. In the figure, 1 is a digital signal transmission line, 21 is a pull-up resistor, and 22 is a stray capacitance. The digital signal transmission line 1 is pulled up by the pull-up resistor 21, and the stray capacitance 22 and the pull-up resistor 21 of the digital signal transmission line 1 are R.
A C charge / discharge circuit is formed. When the signal level of the digital signal transmission line 1 changes from low to an indefinite state, the signal level gradually rises due to the time constant determined by the pull-up resistor 21 and the stray capacitance 22.

FIG. 4 is a voltage waveform diagram of a conventional digital signal transmission line when the stray capacitance is large. Vt is a threshold level of a receiving end element such as an input buffer. When the capacitance value of the stray capacitance 22 shown in FIG. 3 is large and the time constant is large, when the digital signal transmission line 1 changes from the low level output state to the high impedance state as at the time point A in FIG. The voltage level of the transmission line 1 rises relatively slowly and slowly passes through the threshold level Vt of the receiving end element.

Therefore, as compared with the time when the normal low level output changes to the high level output as at the time point C in the figure,
The consumption current flowing between the power supply terminal and the ground terminal of the receiving end element increases, which causes the power supply voltage to bounce, resulting in an increase in malfunction and common mode noise.

FIG. 5 is a voltage waveform diagram of a conventional digital signal transmission line when the stray capacitance is small. When the capacitance value of the stray capacitance 22 shown in FIG. 3 is small and the time constant is small, the voltage level of the digital signal transmission line 1 changes relatively quickly, but as at the time point B in the figure,
Although not shown, when returning from a high-impedance state to a low-level output, overshoot or undershoot occurs, and extra high-level and low-level fluctuations are added, resulting in a kind of noise increase.

In the above description, the circuit in which the digital signal transmission line 1 is pulled up by the resistor has been described.
The same can be said for a circuit pulled down to the ground terminal by a resistor. Further, the above-mentioned Japanese Patent Laid-Open No. 3-11621
In the techniques described in Japanese Patent Laid-Open No. 4 and Japanese Patent Laid-Open No. 6-61836, although the stray capacitance is taken into consideration,
The voltage amplitude is large, and it is necessary to reduce the voltage amplitude to reduce noise.

FIG. 6 is an explanatory diagram of a digital signal transmission line using a conventional active element. In the figure, 1 is shown in FIG.
1 is a digital signal transmission line similar to 1 and 11 is a first C
-MOS inverter, 12 is a second C-MOS inverter, and 31 is a resistor. The input terminal of the first C-MOS inverter 11 is connected to the digital signal transmission line 1, and the second C-MOS inverter 1 is connected to the output terminal thereof.
Two input terminals are connected. First and second C-MO
Power supply terminals and ground terminals of the S inverters 11 and 12 are connected to a power supply (not shown). The output terminal of the second C-MOS inverter 12 is connected to one end of the resistor 31, and the other end of the resistor 31 is connected again to the digital signal transmission line 1.

In the case of the circuit using the active element, when the state of the transmission signal of the digital signal transmission line 1 changes from the high level to the indefinite state or from the low level to the indefinite state, the pull-up shown in FIG. Up resistance 2
Unlike the case of only 1, the undefined state does not cause noise or adversely affect the circuit. However, when the transmission signal of the digital signal transmission line 1 is in the high level state, the output voltage of the second C-MOS inverter 12 is
It becomes almost the power supply voltage, and this power supply voltage is supplied to the digital signal transmission line 1 via the resistor 31.

As a result, the signal voltage of the digital signal transmission line 1 changes between the ground level and the power supply voltage supplied to the first and second C-MOS inverters 11 and 12. More specifically, the low level of the transmission signal of the digital signal transmission line 1 is usually about the ground level. However, the high level of the transmission signal is set lower than the power supply voltage. For example, when the TTL is lowered to the vicinity of the minimum high level of 2.4 V, the width of the signal voltage change of the digital signal transmission line 1 becomes larger than the designed value due to the provision of the active element.

Further, this signal voltage change width has an adverse effect such as generation of radiation noise or crosstalk on the digital signal transmission line 1 as it is. Therefore, in order to reduce the radiation noise and the like, this voltage change width is as much as possible. Need to be reduced.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and keeps the voltage level of the transmission line stable even when the transmission signal is in an indefinite state, and An object of the present invention is to provide a shaping circuit that reduces a signal voltage change width to reduce radiation noise and crosstalk.

[0014]

According to the present invention, in a shaping circuit, a non-inverting output buffer whose input is connected to a transmission line, and a first serially connected output between the buffer and a ground point are provided. , A second impedance element, the first,
The connection point of the second impedance element and the transmission line are connected.

[0015]

1 is a block diagram of an embodiment of the present invention. In the figure, 1 is a digital signal transmission line similar to 1 of FIG. 3, 2 is a non-inverting buffer, 3 is a first impedance element, and 4 is a second impedance element. The digital signal transmission line 1 has a non-inverting buffer 2
Of the first impedance element 3 and the second impedance element 4 are connected in series to the output terminal of the non-inverting buffer 2. The intermediate connection point of this series circuit is again connected to the digital signal transmission line 1.

When the transmission signal of the digital signal transmission line 1 is low level, the output terminal of the non-inverting buffer 2 becomes the ground voltage, and the first impedance element 3 is equivalently grounded. Therefore, the digital signal transmission line 1 is pulled down via the first impedance element 3 and the second impedance element 4.

From this state, the digital signal transmission line 1
, The digital signal transmission line 1 is pulled down through the first impedance element 3 and the second impedance element 4, so that the low level continues to be input to the non-inverting buffer 2 as it is.
The output terminal of the non-inverting buffer 2 results in holding the ground voltage. As described above, even if the transmission signal of the digital signal transmission line is in an indefinite state, unnecessary noise emission and circuit malfunction do not occur.

Next, when the transmission signal of the digital signal transmission line 1 becomes high level, the output terminal of the non-inverting buffer 2 becomes the power supply voltage, and the first impedance element 3 and the second impedance element 4 become equivalent. Will be connected in series between the power supply terminal and the ground terminal. As a result, the digital signal transmission line 1 is pulled up by the first impedance element 3 and pulled down by the second impedance element 4, and the voltage level of the digital signal transmission line 1 does not rise to the power supply voltage. In addition, the voltage settles at a predetermined voltage level that is mainly determined by the first impedance element 3 and the second impedance element 4.

As a result, the fluctuation range of voltage amplitude on the digital signal transmission line can be suppressed to a low level, and radiation noise and crosstalk can be reduced. After that, even if the transmission signal of the digital signal transmission line 1 is changed from the high level to the indefinite state, the voltage level is continuously maintained.

FIG. 2 is a circuit diagram of a specific example of the embodiment shown in FIG. In the figure, the same parts as those in FIG. 1 and FIG. Reference numeral 13 is a first resistor, 14 is a second resistor, and 15 is a capacitor. A non-inverting buffer composed of first and second C-MOS inverters 11 and 12 is connected to the digital signal transmission line 1 as in the circuit shown in FIG. 6, and an output terminal of the non-inverting buffer is connected to the non-inverting buffer. , One end of the first resistor 13 is connected, and one end of a parallel circuit of the second resistor 13 and the capacitor 15 and the digital signal transmission line 1 are connected to the other end. The other end of the parallel circuit of the second resistor 13 and the capacitor 15 is connected to the ground terminal.

When this shaping circuit is used for a digital signal transmission line inside a semiconductor integrated circuit, this shaping circuit can be formed on the same semiconductor substrate as the semiconductor integrated circuit, or can be provided separately.

The overall operation of this circuit is shown in FIG.
The operation of the capacitor 15 will be described, though the operation is similar to that of the block diagram of FIG. The capacitor 15 connected in parallel with the second resistor is not essential. However, the impedance between the digital signal transmission line 1 and the ground terminal can be lowered at a high frequency while the direct current flowing between the digital signal transmission line 1 and the ground terminal is reduced. As a result, it functions to suppress the excessive harmonic components generated in the digital signal transmission line 1 while suppressing the power consumption due to the direct current.

Alternatively, a capacitor (not shown) may be connected in parallel with the first resistor 13, and this may be used together with the capacitor 15 connected in parallel with the second resistor described above. The specific capacitance value of the capacitor 15 is designed in consideration of the stray capacitance.

The non-inverting buffer 2 shown in FIG.
The first and second C-MOS inverters 1 shown in FIG.
It is not limited to the combination of 1 and 12. For example, one CM
The OS inverter includes a series connection of individual P-channel MOSFETs and N-channel MOSFETs, and P-channel MOSFETs.
It can be replaced with a combination of an NP transistor and an NPN transistor. Further, as the non-inverting buffer 2, it is also possible to use a comparator realized by an operational amplifier, which identifies a low level and a high level of a transmission signal transmitted on the digital signal transmission line 1.

The shaping circuit of the present invention can be connected to any point on the digital signal transmission line 1. But,
It is preferable to replace the pull-up resistor and the pull-down resistor in the conventional digital signal transmission line 1 with these resistors at the point where they are connected. Further, it is also preferable that it is provided at the end of the conventional digital signal transmission line 1 so that it also serves as a termination circuit. in this case,
In order to prevent the reflection of the signal waveform, it is necessary to consider the characteristic impedance of the digital signal transmission line 1. For example, the first and second resistors 13 and 14 and the capacitor 15
Etc., the combined impedance of these seen from the digital signal transmission line 1 is as much as possible.
It is preferable to design so as to have a value close to the characteristic impedance of.

In the above description, the shaping circuit of the present invention is
The description has been made on the premise of a digital signal transmission line. That is,
It can be used inside a semiconductor integrated circuit composed of a TTL or C-MOS logic circuit or the like, or as a digital signal transmission line in a signal wiring line or the like on a printed circuit board. It does not have to be a bus line and can be used for a transmission line in which the transmission signal does not have an indefinite state, but is preferably used for a transmission line having an indefinite state. Further, even if it is not a digital data transmission line, it can be similarly used in a transmission line having a state in which a pulse signal whose low level and high level are regulated is transmitted and the transmission signal becomes indefinite. Can be played.

[0027]

As is apparent from the above description, according to the invention described in claim 1, between the buffer of the non-inverting output whose input is connected to the transmission line and the output of this buffer and the ground point. Since the first and second impedance elements connected in series with each other are provided and the connection point of the first and second impedance elements is connected to the transmission line, even if there is a state where the transmission signal becomes indefinite, There is an effect that the voltage level of the line can be kept stable, the signal amplitude change width can be suppressed, and the radiation noise and the like can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a specific example of the embodiment shown in FIG.

FIG. 3 is an explanatory diagram of a conventional digital signal transmission line using a pull-up circuit.

FIG. 4 is a voltage waveform diagram of a conventional digital signal transmission line when the stray capacitance is large.

FIG. 5 is a voltage waveform diagram of a conventional digital signal transmission line when the stray capacitance is small.

FIG. 6 is an explanatory diagram of a conventional digital signal transmission line using an active element.

[Explanation of symbols]

1 ... Digital signal transmission line, 2 ... Non-inverting buffer, 3
... first impedance element, 4 ... second impedance element, 21 ... pull-up resistor, 22 ... stray capacitance, 11
... first C-MOS inverter, 12 ... second C-MO
S inverter.

Claims (1)

[Claims] 1. A non-inverting output buffer having an input connected to a transmission line, and first and second impedance elements connected in series between an output of the buffer and a ground point. A shaping circuit in which a connection point of a second impedance element and the transmission line are connected.