JPH09187001A - Arithmetic unit and arithmetic method - Google Patents

Abstract

(57) Abstract: It is possible to prevent an error from being added to an image by a countermeasure against an IDCT mismatch. SOLUTION: The output of an inverse discrete cosine transform calculation circuit 24 is directly output via a rounding circuit 32, and ± CO
Data for preventing IDCT mismatch is added by the S (*) COS (*) output circuit 30 by the adder 31 and stored in the frame memory 27. Then, the adder 26 outputs the data from the inverse discrete cosine transform calculation circuit 24. Add to output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device and an arithmetic method, and more particularly, to an arithmetic operation including rounding and accumulation.
The present invention relates to an arithmetic device and an arithmetic method for converting data.

[0002]

2. Description of the Related Art Currently, MPEG (Moving Picture Experts) is the most widely used video compression method.
Group) 1 and MPEG2. MPEG1 and MPEG
2 is ISO (International Organization for Stand)
ardization: International Standardization Organization) proposed video compression method. For details, refer to document ISO / IEC11172-2,
And ISO / IEC 13818-2.

In the MPEG1 or MPEG2 system, an encoding apparatus performs two-dimensional discrete cosine (DCT) conversion of an original image and transmits it by a transmission medium or records it on a recording medium and then two-dimensionally by a decoding apparatus. Inverse Discrete Cosine Transform (IDCT) is applied to decode the original video.

When the IDCT operation is performed on the DCT coefficient, a decimal part is generated in the operation result, so that the decimal part is rounded to an integer. If the result of the IDCT operation is “integer + 0.5” (if the decimal part is 0.5),
When rounding up by rounding 0.5 up and when rounding down, the result will differ by "1" depending on the rounding.

It was possible to specify whether to round by rounding up or rounding down, but in reality, MP
Before the EG is standardized, multiple manufacturers' DCTs, IDs
Since the CT chip was already on the market, it could not be standardized. As a result, the rounding method is different for each manufacturer's chip, and so-called IDCT mismatch occurs when chips of different manufacturers are used.

In the MPEG1 or MPEG2 system, inter-frame prediction processing is performed for coding, and at the time of coding, the decoded image is temporarily stored as a predicted image for decoding the next frame. ing. Therefore, the error due to the IDCT mismatch is accumulated through the predicted image.

Therefore, in order to prevent the occurrence of IDCT mismatch, for example, in MPEG1, "+1" or "-1" is applied to even data other than "0" of the data (DCT coefficient) before the IDCT calculation. , And forcibly converted to an odd number, and the result of the IDCT operation is “integer + 0.
It prevents it from becoming 5 ".

In MPEG2, the DCT coefficient (8 ×
When the sum of the 64 coefficients forming the 8-pixel block is an even number, the (7,7) component (the component in which the row and the column are 7 and 7 when the DCT coefficients are arranged in an 8 × 8 matrix, respectively) ) Is added with “+1” or “−1”, and the result of the IDCT operation is “integer + 0.5” as in the case of MPEG1.
Are prevented from becoming.

FIG. 5 is a block diagram showing an example of the configuration of a conventional MPEG1 system encoding device (encoder) and decoding device (decoder). In this figure, the subtractor 10 of the encoder 1 performs subtraction between the current image input and the predicted image input via the local decoder. Discrete Cosine Transform (DCT)
The sform) arithmetic circuit 11 is adapted to perform a discrete cosine transform on the output data of the subtractor 10. A quantizer (Q) circuit 12 quantizes the image data that has been subjected to the discrete cosine transform, and sends it out as a bit stream.

Inverse quantization (IQ; Inverse Qu) of the decoder 2
The antization circuit 20 dequantizes the bitstream sent from the encoder 1. The discrimination circuit 21
The output data (DCT coefficient) of the inverse quantization circuit 20 is "0".
It is determined whether or not it is an even number, and the determination result is output to the ± 1 output circuit 22. The ± 1 output circuit 22 is the discrimination circuit 2
If the DCT coefficient is an even number other than "0", the output of "+1" or "-1" whose sum with the DCT coefficient is closer to "0" is output.

For example, for the DCT coefficient "4",
"-1" is output, and "+1" is output for the DCT coefficient "-6".

The adder 23 adds the output of the inverse quantization circuit 20 and the output of the ± 1 output circuit 22 and outputs the result. The inverse discrete cosine transform (IDCT) arithmetic circuit 24 performs the inverse discrete cosine transform on the output data of the adder 23,
Output the result. The rounding circuit 25 rounds the data subjected to the inverse discrete cosine transform into an integer. The adder 26 adds the image signal (predicted image) recorded in the frame memory 27 and the data output from the rounding circuit 25, and outputs the result.

The output of the adder 26 is stored in the frame memory 27 as a predicted image, and also the CRT (not shown).
(Cathode Ray Tube) It will be input to a display and will be displayed as an image.

In an actual configuration, the output data of the quantization circuit 12 of the encoder 1 is variable length coded, and then output as a bit stream, before being input to the inverse quantization circuit 20 of the decoder 2, the variable length data is output. Although they are coded, they are omitted here to simplify the description.

According to the above configuration, the decoder 2 forcibly changes the DCT coefficient to an odd number, so that the fractional part of the output data of the inverse discrete cosine transform arithmetic circuit 24 becomes "0.5". Is almost gone. Therefore, a rounding error is not generated in the rounding circuit 25 and the error is not accumulated in the frame memory 27.
The occurrence of mismatch can be suppressed.

In the above example, the MPEG1 system encoder and decoder have been described as an example.
Even in the case of the decoder of the system, the occurrence of IDCT mismatch can be suppressed with the same configuration.

In the MPEG2 system decoder,
The discrimination circuit 21 discriminates whether or not the total value of the 64 DCT coefficients is an even number, and when discriminating that the total value is an even number, "+1" is added to the (7, 7) component of the DCT coefficient. "" Or "-1" is added.

That is, the discrimination circuit 21 discriminates that the total value of the DCT coefficients is an even number, and further the DCT coefficients (7,
7) ± 1 output circuit 2 when it is determined that the components are even
2 outputs "+1", and "1" is added to the (7,7) component of the DCT coefficient. In addition, the DCT coefficient (7,
7) When it is determined that the component is odd, the ± 1 output circuit 22 outputs “−1”, and the DCT coefficient (7, 7) is output.
Add "-1" to the component.

Further, when the discriminating circuit 21 discriminates that the total value of the DCT coefficients is an odd number, the ± 1 output circuit 22 is controlled so as not to output.

According to the above example, even in the MPEG2 system decoder, "integer ++" in the rounding circuit 25 is used.
It is possible to prevent an error caused by a difference in handling of 0.5 ″ data (difference between devices). As a result, it is possible to suppress the occurrence of IDCT mismatch.

[0021]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, the IDC
T mismatch is a phenomenon in which errors are accumulated in the frame memory 27 when inter-frame prediction is continuously performed. Therefore, for the data (I picture or P picture) stored in the frame memory 27 and used for inter-frame prediction, the ± 1 output circuit 22 corrects the DCT coefficient (“+1”) to prevent the accumulation of errors. Or "-1"
Must be added).

The correction of the DCT coefficient by the ± 1 output circuit 22 is to prevent an error from being accumulated in the frame memory 27. However, as a result of these operations,
Since the DCT coefficient causes a deviation (error) from the original value by "+1" or "-1", the output data also includes an error. That is, the DCT coefficient is D
And the value output from the ± 1 output circuit 22 is T, the error E added to the output data is expressed as follows from the linearity of the IDCT operation. E = IDCT × (D + T) −IDCT × D = IDCT × T (1)

As described above, in the conventional decoder, the ID generated by the error accumulated in the frame memory 27
The input data was corrected to prevent CT mismatch, but as a result, the ID shown in equation (1)
There is a problem that an error of CT × T is added to the video data.

The present invention has been made in view of the above circumstances, and is intended to reduce an error contained in output data of an MPEG data decoder.

[0025]

According to a first aspect of the present invention, there is provided an arithmetic device for performing a predetermined arithmetic operation on data, and a first adding means for adding a predetermined value to an arithmetic result obtained by the arithmetic means. And an accumulating means for accumulating the calculation result obtained by the first adding means, a second adding means for adding the output of the accumulating means and the calculation result of the calculating means.

According to a fourth aspect of the present invention, a predetermined arithmetic operation is performed on data, a predetermined value is added to the obtained arithmetic result, the obtained arithmetic results are accumulated, and the arithmetic results are accumulated. It is characterized by adding the value and.

An arithmetic unit according to a fifth aspect of the present invention is a first addition means for adding a predetermined value to data, and a first calculation means for performing a predetermined calculation including rounding on the calculation result of the first addition means. Arithmetic means, second arithmetic means for performing a predetermined arithmetic operation including accumulation on the arithmetic result of the first arithmetic means, third arithmetic means for performing a predetermined arithmetic operation including rounding of data, and second arithmetic means It is characterized in that it is provided with a second addition means for adding the calculation result of the calculation means and the calculation result of the third calculation means.

According to a seventh aspect of the present invention, a predetermined value is added to data, a predetermined calculation including rounding is performed on the addition result, and a predetermined calculation including accumulation is performed on the calculation result. It is characterized in that a predetermined operation including rounding is performed on the data and the result is added to an operation result of a predetermined operation including accumulation.

In the arithmetic unit according to the first aspect, the arithmetic means performs a predetermined arithmetic operation on the data, and the arithmetic operation result obtained by the arithmetic means adds a predetermined value to the first addition means to obtain the first arithmetic operation. The accumulating means accumulates the calculation results obtained by the adding means, and the output of the accumulating means and the calculation result of the calculating means are added by the second adding means.

In the operation method according to the fourth aspect, a predetermined operation is performed on the data, a predetermined value is added to the obtained operation result, the obtained operation result is accumulated, and the operation result is accumulated. And the value added.

In the arithmetic unit according to the fifth aspect, the first adding means adds a predetermined value to the data, and the predetermined arithmetic operation including rounding is performed on the arithmetic result of the first adding means. The second calculation means performs a predetermined calculation including accumulation on the calculation result of the first calculation means, and the third calculation means performs a predetermined calculation including rounding of the data. The second addition means adds the calculation result of the calculation means and the calculation result of the third calculation means.

In the operation method according to claim 7, a predetermined value is added to the data, a predetermined operation including rounding is performed on the addition result, and a predetermined operation including accumulation is performed on the operation result. , Data is subjected to a predetermined operation including rounding, and the result is added to an operation result of a predetermined operation including accumulation.

[0033]

1 is a block diagram showing the configuration of an embodiment of an arithmetic unit according to the present invention. In this figure,
Since the parts corresponding to those of the decoder 2 shown in FIG. 5 are denoted by the corresponding reference numerals, the description thereof will be omitted as appropriate.

The output of the inverse quantization circuit 20 is supplied to the inverse discrete cosine transform arithmetic circuit 24 (arithmetic means) and
It is supplied to the discrimination circuit 21. The output of the discrimination circuit 21 is ± C
It is supplied to the OS (*) COS (*) output circuit 30. The output of the inverse discrete cosine transform calculation circuit 24 is supplied to the adder 26, is added to the output of the frame memory 27 (accumulation means), and is output to the adder 31 and the rounding circuit 32.

± COS (*) COS (*) output circuit 30
The (storage means) refers to the output of the discriminating circuit 21 and outputs a predetermined value described later. Adder 31
The (first adding means) is configured to add the output of the ± COS (*) COS (*) output circuit 30 and the output of the adder 26 (second adding means). The output of the adder 31 is supplied to the frame memory 27 via the rounding circuit 25, delayed, and then output to the adder 26.

The rounding circuit 32 rounds the output data (real value) of the adder 26 and outputs integer data. The output signal of the rounding circuit 32 is
It has been input to a CRT display (not shown) and will be output as an image.

In this embodiment, the ± 1 output circuit 22 shown in FIG. 5 is omitted and replaced with ± COS (*) C.
The OS (*) output circuit 30 is added on a loop including the frame memory 27 (a loop formed by the adder 26, the adder 31, the rounding circuit 25, and the frame memory 27). The process of deriving this embodiment from the conventional example will be described below.

FIG. 2 is a block diagram showing a process for deriving the present embodiment from the conventional decoder 1 shown in FIG.

FIG. 2A is a block diagram showing a conventional decoder 1. In this figure, before the inversely quantized bit stream is input to the inverse discrete cosine transform operation circuit 24, the correction data (= ± 1) output from the ± 1 output circuit 22 (not shown) is added. Then, the DCT coefficient is corrected.

In order to perform this correction immediately after the inverse discrete cosine transform calculation circuit 24, the inverse discrete cosine transform is applied to the correction data (= ± 1) as shown in FIG. 2B. Value obtained as a result ± COS (*) COS
(*) (* Will be described later) may be added by the adder 31 to the data subjected to the inverse discrete cosine transform.

Correction data added by the adder 31 ±
COS (*) COS (*) can be expressed as follows. COS (*) COS (*) = COS {iπ (2k + 1) / 16} COS {jπ (2h + 1) / 16} (2)

Here, i, j is the DCT coefficient (i, j) for which ± 1 is added (when the DCT coefficients are arranged in an 8 × 8 matrix, the i-th row and the j-th column) I) and (h) and (k) are DCTs.
This corresponds to the data h, k arranged in the h-th row and the k-th column of the real space data obtained when the coefficient (i, j) is subjected to the inverse discrete cosine transform.

Through the above process, as shown in FIG. 2B, the adder 31 adds ± COS (*) COS (*) to the output of the inverse discrete cosine transform arithmetic circuit 24, A block diagram for supplying to the rounding circuit 25 is obtained.

Next, from the block diagram shown in FIG.
Adder 31 and ± COS (*) COS (*) not shown
The output circuit 30 is a loop including the frame memory 27 (in FIG. 2B, the frame memory 27 and the adder 2
6)).

In FIG. 2 (b), the output of the inverse discrete cosine transform arithmetic circuit 24 is a, ± COS (*) CO not shown.
It is assumed that the output of the S (*) output circuit 30 is b, the output of the adder 31 is c, the output of the rounding circuit 25 is d, and the output (or output signal) e of the adder 26.

At this time, the output of the adder 26 can be expressed as follows. e = e ^-1 + d (3)

Here, e ⁻¹ represents the output e of the adder 26 delayed by the frame memory 27. Equation (3) can be expressed as follows using the output c of the adder 31. e = e ^-1 + d = e ^-1 + round (c) (4)

Note that round (c) means that rounding processing is performed on c.

Further, in the equation (4), the output a of the inverse discrete cosine transform arithmetic circuit 24 and ± COS (*) COS (not shown) are used.
(*) It can be expressed as follows using the output b of the output circuit 30. e = e ^-1 + round (a + b) (5)

Here, since e ^-1 is an integer, this is r
The expression (5) can be modified as follows by including it in the parentheses of found (). e = round (a + b + e ⁻¹ ) (6)

FIG. 2C is a modification of FIG. 2B based on this equation. In this block diagram, the adder 3
1 and the rounding circuit 25 are inserted in a loop containing the frame memory 27.

Here, the value ± COS is calculated by the adder 31.
The reason why (*) COS (*) is added is to prevent the error from being accumulated in the frame memory 27 as described above. However, as shown in FIG. 2C, since the correction data ± COS (*) COS (*) is added to the output of the adder 26, this value is also added to the output signal e. Will be done. This can be seen from the fact that the value b is included in the equation (6).

Therefore, the output point is set between the adder 26 and the point where the output data is taken out (point P indicated by a black circle in the figure (hereinafter abbreviated as output point P)). P and frame memory 2
Moving during 7 results in the block diagram of the embodiment shown in FIG.

Therefore, the frame memory 27 in FIG.
To the frame memory 27 shown in FIG. 2A, the input signal to the frame memory 27 shown in FIG. 2B, and the input signal to the frame memory 27 shown in FIG. e, the input signal to the frame memory 27 shown in FIG. 2C, and the frame memory 27 shown in FIG.
The input signals to all have the same value. This means that in the configuration shown in FIG. 1 as well, similar to the configuration shown in FIG. 5, accumulation of errors due to IDCT mismatch does not occur in the frame memory 27.

Then, in the embodiment shown in FIG. 1, the output signal f of the rounding circuit 32 is expressed by the following equation. f = round [a + g] (7)

In this equation, g is the output signal of the frame memory 27, that is, the data delayed by the frame with respect to the data for which the IDCT mismatch countermeasure has been taken. Therefore, pure DC without the error IDCT × T shown in equation (1)
The value a obtained by performing the inverse discrete cosine transform on the T coefficient (output data of the inverse quantization circuit 20) and the value g are added, and then the rounded value f is output.

Next, the operation of this embodiment will be described.

The bit stream sent from the encoder (not shown) is input to the dequantization circuit 20, dequantized, and then output to the inverse discrete cosine transform calculation circuit 24 and the discrimination circuit 21. The inverse discrete cosine transform calculation circuit 24 performs an inverse discrete cosine transform on the dequantized data and outputs it to the adder 26.

The adder 26 adds the data (I picture or P picture as a predicted image) stored in the frame memory 27 and the output data of the inverse discrete cosine transform arithmetic circuit 24. The output of the adder 26 is the rounding circuit 32.
Is supplied to the adder 31.

The adder 31 uses ± COS (*) COS
(*) The output data of the output circuit 30 and the output data of the adder 26 are added. Note that ± COS (*) COS
(*) The output circuit 30 refers to the output of the discrimination circuit 21,
Output a predetermined value.

That is, the discriminating circuit 21 first discriminates whether the bit stream input to the inverse quantizing circuit 20 is an I picture or a P picture. Then, the input bit stream is I picture or P
When it is determined that it is a picture, it is further determined whether or not the DCT coefficient is an even number other than "0". As a result, "0"
If it is determined to be an even number, “+1” or “−”
Of the 1's, the one whose sum with the DCT coefficient is closer to "0" is selected, and the value is multiplied by COS (*) COS (*) (= + COS (*) COS (*) or -COS ( *)
The output circuit 30 outputs COS (*).

As a result, for the even number data other than "0" among the DCT coefficients of the I picture or P picture, the adder 31 causes the + COS (*) COS (*) or -COS (*) COS ( *) Will be added.

The output of the adder 31 is rounded by the rounding circuit 25, converted into integer data, and stored in the frame memory 27. This data will then be read and output as a predicted image at a predetermined timing.

The output of the frame memory 27 is output to the adder 26 only when the input bit stream is a P picture or a B picture (which requires a prediction image). The output of the adder 26 is supplied to the rounding circuit 32, is subjected to rounding processing, and is then passed through a C (not shown).
It is output to an RT display or the like and output as a video. As a result, when the input bit stream is an I picture, the output data of the inverse discrete cosine transform operation circuit 24 is directly output from the adder 26 (without being added to the correction data for the IDCT mismatch countermeasure). Therefore, it is possible to display a video signal that does not include an error.

When a P picture or a B picture is input, the data stored in the frame memory 27 in which the error is not accumulated (data corrected for the IDCT mismatch countermeasure) and the inverse discrete data. The output data of the cosine transform calculation circuit 24 (a value obtained by purely performing inverse discrete cosine transform on the DCT coefficient) is added by the adder 26 and output, so that a video signal containing no error is displayed. can do.

The rounding circuit 32 is added for the purpose of converting real number data into an integer because the data input to a CRT display (not shown) is often 8-bit integer data. Therefore, this rounding circuit 32 can be omitted in some cases.

FIG. 3 is a block diagram showing another configuration of the embodiment of the present invention. In this figure, the parts corresponding to those in FIG. 1 are designated by the corresponding reference numerals, and the description thereof will be omitted as appropriate.

This embodiment is a decoder of the MPEG2 system, and a 1-bit cumulative adder 40 is newly added instead of the discrimination circuit 21 of FIG. Other configurations are shown in FIG.
Is the same as in the case of

The 1-bit cumulative adder 40 determines whether the input bit stream is an I picture or a P picture. When it is determined that the bit stream is an I picture or a P picture, the least significant bits of the 64 DCT coefficients that have been inversely quantized by the inverse quantization circuit 20 are cumulatively added.

When the cumulative addition result is "0", 6
It is determined that the value obtained by adding the four pieces of data is even, and whether or not the (7,7) component of the DCT coefficient is even is determined. If it is determined that the (7,7) component is an even number, + C is output from the ± COS (*) COS (*) output circuit 30.
OS (*) COS (*) is output, and the DCT coefficient is added to the data subjected to the inverse discrete cosine transform. When it is determined that the (7,7) component of the DCT coefficient is an odd number, the ± COS (*) COS (*) output circuit 30 outputs −COS (*) COS (*) so that the DCT coefficient is Add to the data obtained by inverse discrete cosine transform.

Here, COS (*) and COS (*) can be expressed as follows. COS (*) COS (*) = COS {7π (2k + 1) / 16} COS {7π (2h + 1) / 16} (8)

Here, h and k are (h, k of the data in the real space when the DCT coefficient is inverse discrete cosine transformed.
k) component is shown.

If the 1-bit cumulative adder 40 determines that the total value of the DCT coefficients is an odd number, ± COS
No output is made from the (*) COS (*) output circuit 30.

Since the other operations are the same as those in the embodiment shown in FIG. 1, description thereof will be omitted. According to the above embodiment, the error contained in the output video can be reduced even in the MPEG2 system decoder.

FIG. 4 is a block diagram showing still another configuration of the embodiment of the arithmetic unit of the present invention. In this figure, the parts corresponding to those in FIG.
Description is omitted as appropriate.

This embodiment is different from the conventional decoder 2 shown in FIG. 5 in that it has an inverse discrete cosine transform arithmetic circuit 24B (third embodiment).
2), a rounding circuit 25B (third calculating means), and an adder 50 (second adding means) are newly added. The rest of the configuration is the same as in FIG.

Next, the operation of this embodiment will be described.

The bit stream sent from the encoder (not shown) is inversely quantized by the inverse quantization circuit 20. The determination circuit 21 determines whether the dequantized data is an even number other than "0". as a result,
If it is determined to be an even number other than "0", then one of "+1" or "-1" whose sum with the dequantized data is closer to "0" is selected, and the value is selected as ± 1 output circuit. 22 to output. If it is determined that the inversely quantized data is odd or "0", the ± 1 output circuit 2
2 does not output.

The output of the ± 1 output circuit 22 is the adder 23.
It is added to the output of the inverse quantization circuit 20 by (first adding means) and output to the inverse discrete cosine transform arithmetic circuit 24A (first arithmetic means). Inverse discrete cosine transform arithmetic circuit 2
4A performs an inverse discrete cosine transform on the output of the adder 23, and then outputs the calculation result to the rounding circuit 25A (first calculation circuit). The rounding circuit 25A rounds the output data of the inverse discrete cosine transform calculation circuit 24A, converts it into an integer, and then adds it to the adder 26 (second calculation means).
Output to

The adder 26 includes a frame memory 27 (second
The data stored in the calculation means) is added to the output of the rounding circuit 25A. When the input bit stream is a B picture, the output of the adder 26 is not supplied to the frame memory 27 because the switch (not shown) is in the “OFF” state. As a result, the data stored in the frame memory 27 is only I pictures or P pictures.

On the other hand, the output of the inverse quantization circuit 20 is also supplied to the inverse discrete cosine transform arithmetic circuit 24B, subjected to the inverse discrete cosine transform, and then output to the rounding circuit 25B.
The rounding circuit 25B rounds the data that has been subjected to the inverse discrete cosine transform into an integer. The adder 50 adds the data stored in the frame memory 27 and the output of the rounding circuit 25B and outputs the result to a CRT display (not shown) or the like.

The output of the frame memory 27 is supplied to the adder 50 by a switch (not shown) which is turned on only when the input bit stream is a P picture or a B picture. Therefore, when the I picture is input, the output of the rounding circuit 25B is directly supplied to the CRT display (not shown) (without being added to the output from the frame memory 27).

Further, since the data stored in the frame memory 27 is corrected by the ± 1 output circuit 22 as a countermeasure against the IDCT mismatch, no error is accumulated due to the IDCT mismatch. Further, the data output via the inverse discrete cosine transform arithmetic circuit 24B is also
Since the correction data is not added, the data is close to the original image without error due to the correction data.

Considering the above points, considering a case where an I picture is input, in this case, the data for which the IDCT mismatch countermeasure is not taken (the error is not added) is directly output from the rounding circuit 25B. To be done. When a P picture is input, the error-free data stored in the frame memory 27 and the output data without error due to the correction data of the rounding circuit 25B are added,
Is output. When a B picture is input, P
Similar to the case of the picture, the output of the frame memory 27 and the output of the rounding circuit 25B are added and output.
Therefore, in any of the pictures, a video signal close to the original video with a small error can be obtained.

Further, the inverse discrete cosine transform arithmetic circuit 24A
(Or 24B) is a rounding circuit 25A (or 25B)
Together with the same LSI (Large Scale Integrated Circui
In many cases, the above configuration makes it possible to obtain a video signal with a small error even when using such an LSI.

The above embodiment is an example of the structure of the MPEG1 system decoder. However, by replacing the discrimination circuit 21 with the 1-bit cumulative adder 40 shown in FIG.
A G2 type decoder can be obtained.

The ± COS (*) COS (*) output circuit 30 in the embodiment shown in FIG. 1 or 3 calculates these values in advance and stores them in a memory as a look-up table. If necessary, these may be read and used. With such a configuration, it is not necessary to repeatedly execute complicated calculations.

[0088]

According to the arithmetic unit of the first aspect and the arithmetic method of the fourth aspect, a predetermined arithmetic operation is performed on the data and a predetermined value is added to the obtained arithmetic operation result. Since the calculation result is accumulated and the calculation result and the accumulated value are added, it is possible to obtain data with less error.

An arithmetic unit according to claim 5 and claim 7
According to the calculation method described in (1), a predetermined value is added to the data, a predetermined calculation including rounding is performed on the addition result, a predetermined calculation including accumulation is performed on the calculation result, and the data is rounded. Since the predetermined arithmetic operation including the calculation is performed and the result is added to the calculation result of the predetermined arithmetic operation including the accumulation, it is possible to configure the arithmetic device with less error by using the arithmetic circuit (LSI) including the rounding.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an arithmetic unit according to the present invention.

FIG. 2 is a diagram showing a process of obtaining an arithmetic device of the present invention from a conventional arithmetic device.

FIG. 3 is a block diagram showing another configuration of the embodiment of the arithmetic unit of the present invention.

FIG. 4 is a block diagram showing still another configuration of the embodiment of the arithmetic unit of the present invention.

FIG. 5 is a block diagram showing an example of a configuration of a conventional encoder and decoder.

[Explanation of symbols]

10 Subtractor 11 Discrete Cosine Transform Operation Circuit (Calculation Means) 12 Quantization Circuit 20 Inverse Quantization Circuit 21 Discrimination Circuit 22 ± 1 Output Circuit 23 Adder (First Addition Means, Second Addition Means) 24 Inverse Discrete Cosine Conversion arithmetic circuit (first arithmetic means,
Third calculation means) 25 Rounding circuit (first calculation means, third calculation means) 26 Adder (second calculation means) 27 Frame memory (accumulation means, second calculation means) 30 ± COS (* ) COS (*) output circuit (storage means) 31 adder (first addition means) 32 rounding circuit 40 1-bit cumulative adder 50 adder (second addition means)

Claims (7)

[Claims] 1. A calculation means for performing a predetermined calculation on data, a first addition means for adding a predetermined value to a calculation result obtained by the calculation means, and a calculation obtained by the first addition means. An arithmetic unit comprising: an accumulating means for accumulating results; and an second adding means for adding the output of the accumulating means and the calculation result of the calculating means. 2. The arithmetic unit according to claim 1, wherein the data is data in a frequency space, and the arithmetic unit applies an inverse discrete cosine transform to the data. 3. The arithmetic unit according to claim 1, wherein the predetermined value is stored in a storage means. 4. A predetermined operation is performed on the data, a predetermined value is added to the obtained operation result, the obtained operation result is accumulated, and the operation result and the accumulated value are added. The calculation method characterized by. 5. A first addition means for adding a predetermined value to the data, a first calculation means for performing a predetermined calculation including rounding on the calculation result of the first addition means, and the first calculation means. Second arithmetic means for performing a predetermined arithmetic operation including accumulation on the arithmetic result of the arithmetic operation means, third arithmetic means for performing a predetermined arithmetic operation including rounding on the data, and arithmetic operation of the second arithmetic means An arithmetic unit comprising: a result and a second addition means for adding the calculation result of the third calculation means. 6. The data according to claim 6, wherein the data is data in a frequency space, and the first and third arithmetic means perform an inverse discrete cosine transform on the input data. Computing device. 7. A predetermined value including a rounding is added to the data, a predetermined operation including rounding is performed on the addition result, a predetermined operation including accumulation is performed on the operation result, and a predetermined operation including rounding is performed on the data. An arithmetic method characterized by performing an arithmetic operation and adding it to an arithmetic operation result of a predetermined arithmetic operation including the accumulation.