JPH09160831A - Information processing device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To realize a protection function by judging whether data access is possible or not depending on a space where a data access instruction is located. A circuit having a circuit for decoding an address and setting a level at the time of instruction fetch and a circuit for comparing an instruction level delayed by a CPU at the time of data access and a level of a data address are provided. A protection circuit having a function of inhibiting data transfer between memories is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access protection function in a microprocessor or a system using the same.

[0002]

2. Description of the Related Art In the case of implementing a data protection function in a microprocessor or a system using the same, it is determined whether or not the level is internally violated when an instruction is executed, and the level is violated. The data protection function is realized by generating an exception in some cases. Alternatively, in the case of a processor having a memory management mechanism, the access level for the translated page is also read at the time of address translation, and when the instruction in the page violates the level, the access is interrupted to provide a data protection function. To be realized.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to enable protection by distinguishing the data protection function according to the address space in which the instruction itself that accesses the data is located. That is, it is possible to protect in advance depending on the type of memory in the space where the program is located, and to protect the memory that is not particularly desired to be read, such as the contents of ROM or RAM.

It is another object of the present invention to generate an exception and notify a protection violation when reading or writing in a state where the protected data does not have the right to access, and whether the exception is generated. We have implemented two methods to operate as if the access was normally completed.
By using the latter method, it is possible to enhance the security function because the protected address is not known outside.

[0005]

A protection circuit is provided as a means for realizing a protection function. A command for distinguishing between instruction access and data access and an address to be accessed are passed as inputs to the protection circuit, and the protection circuit decodes the address and returns the level to the CPU.
If the access from the CPU is an instruction fetch CPU
Receives a level with an opcode. The level received here is held until the data access stage of the instruction, and is passed to the protection circuit together with the data access command and address. The protection circuit judges that the command is a data access, compares the level received from the CPU with the level of the address to be accessed, and gives permission for the data access.

When data read access is not permitted, there are a method of generating an exception and a method of not returning an exception and returning wrong data to the CPU as if the data was normally read. There are two methods, that is, a method of generating an exception even when the data write access is not permitted, and a method of operating as if writing was performed without generating an exception and not actually writing. This realizes data protection.

The determination of the level by the address can be made variable by a built-in register.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, this information processing apparatus comprises a CPU and a protection circuit, and protects access to a memory or peripheral circuits. An instruction fetch / data access request is issued from the command issuing circuit of the CPU on the bus 1.
Issued through 01 to the protection circuit. The addresses for these requests are transferred from the ALU to the protection circuit through the bus 102, and the access level setting circuit decodes the address and transfers the level for each address to the CPU through 103.

When the command is an instruction fetch, the CPU holds the address level corresponding to the instruction using the access level delay circuit until the execution stage of the instruction, and at the same time as the data access, the access level of the protection circuit through the bus 105. Transfer to the judgment circuit.

The access level judgment circuit judges whether or not the data access is made by using the command sent from the CPU through the bus 101, and if it is the data access, the level of the data access itself sent through the bus 104 and the data access through the bus 105 are sent. Compare the level of the instruction itself that issues the data access. When access is permitted by this determination circuit, the CPU is accessed through the bus 106.
And drives the buses 107 and 108 connecting the memory and peripheral circuits.

FIG. 2 shows a protocol between the CPU and the protection circuit that realizes this protection function. It is assumed that an instruction is represented by 201 in a 5-stage pipeline. Each stage of the pipeline has an I-Stage for instruction fetch, a D-Stage for decoding, an E-Stage for execution, and an A-Sta for memory access.
ge, S-Stage of register store. I
In -Stage, the instruction fetch command (204) and the instruction fetch address (20
5) is passed to the protection circuit.

The protection circuit generates a level from the address 205 and returns the level of the instruction to the CPU through the signal path 207. Since the reading of the instruction fetched data (instruction code) itself is not protected, the instruction code is in signal path 2
It is passed to D-Stage of CPU through 06. When the decoded instruction is a data access, the instruction and address of the data access are passed to the protection circuit through the signal paths 209 and 210 in A-Stage. At the same time, the level of the instruction held by the delay circuit 208 is passed from the CPU to the protection circuit.

These signals are processed by the access level determination circuit of the protection circuit, and the transfer of data is protected through 213. This is a case where the pipeline has five stages, but even if there are two or more E-Stages, it can be dealt with by increasing the delay circuit 208.

FIG. 3 shows an example of address space allocation. In FIG. 3A, it is assumed that the address space is divided into 301, space 1, space 2, and space 3. In this case, it is possible to deal with access to the three spaces as shown in FIG. 303 is the space where the instruction is located,
Reference numeral 304 represents a data space accessed by the instruction 303. Here, the instructions of space 3 can read the space 3 and read / write the spaces 1 and 2. Further, the instructions in the space 2 can read / write the spaces 1 and 2, but the access in the space 3 is prohibited. Further, the instruction of the space 1 is given only the read / write permission of the space 1, and the access of the spaces 2 and 3 is prohibited.

[0015]

According to the present invention, when the information processing apparatus has a memory which is not desired to be read out to the outside, for example, an internal ROM or RAM, it is possible to protect only by the addresses assigned to those memories. It will be possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the relationship between a protection circuit that realizes a protection function, a CPU, and a memory.

FIG. 2 is a block diagram showing a protocol between a CPU and a protection circuit when realizing a protection function.

FIG. 3 is an explanatory diagram showing an example of address allocation when a protection function is realized.

[Explanation of symbols]

301 ... Address space, 302 ... Instruction / data access correspondence table, 303 ... Instruction location space, 304 ... Data location space

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuaki Tamaki 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Shigezumi Matsui Josui, Kodaira-shi, Tokyo 5-20-1 Honmachi, Hitachi, Ltd. Semiconductor Business Division (72) Inventor Katsuharu Takakubo 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Ltd. (72) Inventor Hashimoto Koji 5-22-1, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Ken Tatezawa 5-22-1 Kamisuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System ( 72) Inventor Mikio Furuyama 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (6)

[Claims] 1. An execution level determination circuit having an instruction level setting circuit for setting a level according to a logical address space in which an instruction for accessing data is located, and determining whether data can be read or written according to the level. An information processing apparatus having: 2. An information processing apparatus having a circuit for holding the level generated by the instruction level setting circuit according to claim 1 until the instruction is executed. 3. An information processing apparatus that interrupts execution by generating an exception when an access occurs at a level without the right to access. 4. An exception is not generated when an access occurs at a level without the right to access, a fixed value is always read at the time of reading, and actual writing is not performed at the time of writing. An information processing device, characterized in that an address without a right to access is made unknown by completing the operation as if it had ended. 5. An information processing apparatus having a circuit capable of generating an instruction level setting using an arbitrary position of an address by a built-in register or a substitute thereof. 6. An information processing apparatus capable of setting whether to use a data protection function or not by using a built-in register or a substitute thereof.