JPH09160076A5

JPH09160076A5 -

Info

Publication number: JPH09160076A5
Application number: JP1996260572A
Authority: JP
Filing date: 1996-10-01
Publication date: 2005-07-28
Anticipated expiration: 2016-10-01

Description

請求項１に係る発明は、基板上に配置されゲート電極領域を含む複数本の走査線及び前記走査線と略平行な補助容量線と、この上に配置される第１絶縁膜、少なくとも前記ゲート電極領域上に配置される半導体膜、前記半導体膜に電気的に接続されるソース電極及びドレイン電極とを含む薄膜トランジスタと、前記薄膜トランジスタ上に配置される第２絶縁膜と、前記ドレイン電極に電気的に接続されると共に前記走査線と略直交する信号線と、前記ソース電極と電気的に接続される画素電極とを備えた表示装置用アレイ基板において、前記第１絶縁膜を介して前記補助容量線と略直交する方向に配線された束ね配線を含み、前記補助容量線と前記束ね配線とを導電層を介して電気的に接続する補助容量線連結部を含むことを特徴とする表示装置用アレイ基板である。The invention of claim 1 is an array substrate for a display device comprising: a plurality of scanning lines and auxiliary capacitance lines arranged on a substrate, each including a gate electrode region; a first insulating film arranged thereon; a semiconductor film arranged at least on the gate electrode region; a thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; a second insulating film arranged on the thin film transistor; a signal line electrically connected to the drain electrode and approximately perpendicular to the scanning lines; and a pixel electrode electrically connected to the source electrode, the array substrate for a display device comprising: a bundling wiring routed via the first insulating film in a direction approximately perpendicular to the auxiliary capacitance lines; and an auxiliary capacitance line connecting portion electrically connecting the auxiliary capacitance lines and the bundling wiring via a conductive layer.

請求項５に係る発明は、基板上に配置されゲート電極領域を含む複数本の走査線及び前記走査線と略平行な補助容量線と、この上に配置されるゲート絶縁膜、少なくとも前記ゲート電極領域上に配置される半導体膜、前記半導体膜に電気的に接続されるソース電極及びドレイン電極とを含む薄膜トランジスタと、前記薄膜トランジスタ上に配置される層間絶縁膜と、前記ドレイン電極に電気的に接続されると共に前記走査線と略直交する信号線と、前記ソース電極と電気的に接続される画素電極とを備えた表示装置用アレイ基板において、前記ゲート絶縁膜を介して前記補助容量線と略直交する方向に配線された束ね配線を含み、前記補助容量線と前記束ね配線とを導電層を介して電気的に接続する補助容量線連結部を含むことを特徴とする表示装置用アレイ基板である。The invention of claim 5 is an array substrate for a display device comprising: a plurality of scanning lines and auxiliary capacitance lines arranged on a substrate, each including a gate electrode region; a gate insulating film arranged thereon; a semiconductor film arranged at least on the gate electrode region; thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film arranged on the thin film transistor; a signal line electrically connected to the drain electrode and approximately perpendicular to the scanning lines; and a pixel electrode electrically connected to the source electrode, the array substrate for a display device comprising: a bundling wiring routed via the gate insulating film in a direction approximately perpendicular to the auxiliary capacitance lines; and an auxiliary capacitance line connecting portion electrically connecting the auxiliary capacitance lines and the bundling wiring via a conductive layer.

請求項７に係る発明は、基板上に配置されゲート電極領域を含む複数本の走査線及び前記走査線と略平行な補助容量線と、この上に配置される第１絶縁膜、少なくとも前記ゲート電極領域上に配置される半導体膜、前記半導体膜に電気的に接続されるソース電極及びドレイン電極とを含む薄膜トランジスタと、前記薄膜トランジスタ上に配置される第２絶縁膜と、前記ドレイン電極に電気的に接続されると共に前記走査線と略直交する信号線と、前記ソース電極と電気的に接続される画素電極とを備えたアレイ基板を有した液晶表示装置において、前記第１絶縁膜を介して前記補助容量線と略直交する方向に配線された束ね配線を含み、前記補助容量線と前記束ね配線とを導電層を介して電気的に接続する補助容量線連結部を含むことを特徴とする液晶表示装置である。The invention of claim 7 is a liquid crystal display device having an array substrate including a plurality of scanning lines and auxiliary capacitance lines arranged on a substrate, each including a gate electrode region, and each substantially parallel to the scanning lines, a first insulating film arranged thereon, a semiconductor film arranged at least on the gate electrode region, thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film, a second insulating film arranged on the thin film transistor, a signal line electrically connected to the drain electrode and substantially perpendicular to the scanning lines, and a pixel electrode electrically connected to the source electrode, the liquid crystal display device including a bundling wiring routed via the first insulating film in a direction substantially perpendicular to the auxiliary capacitance lines, and a bundling wiring connecting electrically the auxiliary capacitance lines and the bundling wiring via a conductive layer.

請求項１１に係る発明は、基板上に配置されゲート電極領域を含む複数本の走査線及び前記走査線と略平行な補助容量線と、この上に配置されるゲート絶縁膜、少なくとも前記ゲート電極領域上に配置される半導体膜、前記半導体膜に電気的に接続されるソース電極及びドレイン電極とを含む薄膜トランジスタと、前記薄膜トランジスタ上に配置される層間絶縁膜と、前記ドレイン電極に電気的に接続されると共に前記走査線と略直交する信号線と、前記ソース電極と電気的に接続される画素電極とを備えたアレイ基板を有した液晶表示装置において、前記ゲート絶縁膜を介して前記補助容量線と略直交する方向に配線された束ね配線を含み、前記補助容量線と前記束ね配線とを導電層を介して電気的に接続する補助容量線連結部を含むことを特徴とする液晶表示装置である。The invention of claim 11 is a liquid crystal display device having an array substrate including: a plurality of scanning lines and auxiliary capacitance lines arranged on a substrate, each including a gate electrode region; a gate insulating film arranged thereon; a semiconductor film arranged at least on the gate electrode region; thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film arranged on the thin film transistor; a signal line electrically connected to the drain electrode and approximately perpendicular to the scanning lines; and a pixel electrode electrically connected to the source electrode, the liquid crystal display device including a bundled wiring routed via the gate insulating film in a direction approximately perpendicular to the auxiliary capacitance lines, and an auxiliary capacitance line connecting portion electrically connecting the auxiliary capacitance lines and the bundled wiring via a conductive layer.

Claims

an array substrate for a display device, comprising: a plurality of scanning lines arranged on a substrate, each including a gate electrode region; auxiliary capacitance lines substantially parallel to the scanning lines; a first insulating film arranged thereon; a semiconductor film arranged at least on the gate electrode region; thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film; a second insulating film arranged on the thin film transistors; signal lines electrically connected to the drain electrodes and substantially perpendicular to the scanning lines; and pixel electrodes electrically connected to the source electrodes;
a bundling wiring wired in a direction substantially perpendicular to the storage capacitance line via the first insulating film;
an auxiliary capacitance line connecting portion that electrically connects the auxiliary capacitance line and the bundled wiring via a conductive layer;

the bundled wiring is made of the same material as the signal lines,
2. The array substrate for a display device according to claim 1 , wherein the conductive layer is made of the same material as the pixel electrodes.

2. The array substrate for a display device according to claim 1, wherein a low-resistance semiconductor film is interposed between the semiconductor film and the source electrode and the drain electrode, and a low-resistance semiconductor layer made of the same material as the low-resistance semiconductor film is interposed between the signal line and the semiconductor layer in the intersection region.

2. The display array substrate according to claim 1 , wherein the semiconductor film is mainly made of amorphous silicon.

an array substrate for a display device, comprising: a plurality of scanning lines arranged on a substrate, each including a gate electrode region; auxiliary capacitance lines substantially parallel to the scanning lines; a gate insulating film arranged thereon; a semiconductor film arranged at least on the gate electrode region; thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film arranged on the thin film transistor; signal lines electrically connected to the drain electrodes and substantially perpendicular to the scanning lines; and pixel electrodes electrically connected to the source electrodes;
a bundled wiring wired in a direction substantially perpendicular to the auxiliary capacitance line via the gate insulating film;
a storage capacitance line connecting portion that electrically connects the storage capacitance line and the bundling wiring via a conductive layer;
1. An array substrate for a display device comprising:

the bundled wiring is made of the same material as the signal lines,
The conductive layer is made of the same material as the pixel electrode.
6. The array substrate for a display device according to claim 5.

a first insulating film disposed on the thin film transistors, a semiconductor film disposed at least on the gate electrode region, a thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; a second insulating film disposed on the thin film transistors; a signal line electrically connected to the drain electrode and approximately perpendicular to the scanning lines; and a pixel electrode electrically connected to the source electrode.
a bundling wiring wired in a direction substantially perpendicular to the storage capacitance line via the first insulating film;
a storage capacitance line connecting portion that electrically connects the storage capacitance line and the bundling wiring via a conductive layer;
A liquid crystal display device characterized by:

the bundled wiring is made of the same material as the signal lines,
The conductive layer is made of the same material as the pixel electrode.
8. The liquid crystal display device according to claim 7.

A low-resistance semiconductor film is interposed between the semiconductor film and the source electrode and the drain electrode, and a low-resistance semiconductor layer made of the same material as the low-resistance semiconductor film is interposed between the signal line and the semiconductor layer in the intersection region.
8. The liquid crystal display device according to claim 7.

The semiconductor film is mainly made of amorphous silicon.
8. The liquid crystal display device according to claim 7.

a semiconductor film disposed on at least the gate electrode region; thin film transistors each including a source electrode and a drain electrode electrically connected to the semiconductor film; an interlayer insulating film disposed on the thin film transistors; a signal line electrically connected to the drain electrode and approximately perpendicular to the scanning lines; and a pixel electrode electrically connected to the source electrode.
a bundled wiring wired in a direction substantially perpendicular to the auxiliary capacitance line via the gate insulating film;
a storage capacitance line connecting portion that electrically connects the storage capacitance line and the bundling wiring via a conductive layer;
A liquid crystal display device characterized by:

the bundled wiring is made of the same material as the signal lines,
The conductive layer is made of the same material as the pixel electrode.
12. The liquid crystal display device according to claim 11.