JPH09168039A - Carrier recovery circuit - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To reduce the circuit scale. SOLUTION: Selectors 32 and 34 are controlled by a loop control circuit 12 to select a quadrature-detected complex signal and its delayed signal during an AFC period, respectively. Subtractor 35 and complex multiplier 36
Thus, the frequency error is detected from the outputs of the selectors 32 and 34. Further, the selectors 32 and 34 select the synchronously detected complex signal and its symbol determination result during the PLL period. As a result, the subtractor 35 and the complex multiplier 36 detect the phase error during the PLL period. The output of the complex multiplier 36 in the AFC period is supplied to the loop filter 7 in the AFC loop, and the output of the complex multiplier 36 in the PLL period is supplied to the loop filter 15 in the PLL loop. Thus, AFC
Subtractor 35 and complex multiplier in control and PLL control
36 is also used to reduce the number of circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier wave reproducing circuit suitable for reproducing a reproduced carrier wave of a multilevel quadrature amplitude demodulator.

[0002]

2. Description of the Related Art In recent years, high quality digital modulation has been developed in the transmission of video signals or audio signals. For example, in digital television (TV) broadcasting, CAT
In V (cable television), digital transmission using a multilevel QAM (quadrature amplitude modulation) system is under study.

FIG. 7 is a block diagram showing such a multilevel QAM demodulator.

An IF (intermediate frequency) signal is input to the input terminal 1. This IF signal is obtained by performing multi-level QAM modulation on a digital signal on the transmitting side and then performing quadrature modulation. IF (intermediate frequency) signal from input terminal 1 is A
It is given to the / D converter 2 and converted into a digital signal. The digital IF signal from the A / D converter 2 is given to the multipliers 3 and 4.

Multipliers 3 and 4, sin / cos converter 5,
A quadrature detection circuit is configured by the numerically controlled oscillator (hereinafter referred to as NCO) 6. The NCO 6 is controlled by the output of a loop filter 7 which will be described later, and outputs a numerical value for generating a reproduction carrier of a predetermined frequency to the sin / cos converter 5. The sin / cos converter 5 reproduces an in-phase axis (I axis) carrier of a predetermined frequency based on the numerical value from the NCO 6 and supplies it to the multiplier 3, and
An orthogonal axis (Q axis) carrier having a predetermined frequency is reproduced and given to the multiplier 4. The multiplier 3 multiplies the output of the A / D converter 2 by the in-phase axis carrier to obtain the in-phase axis detection output, and the multiplier 4
The output of the / D converter 2 is multiplied by the orthogonal axis carrier to obtain the orthogonal axis detection output. The outputs of the multipliers 3 and 4 are given to the roll-off filters 8 and 9, respectively.

The detection outputs of the I and Q axes are supplied to roll-off filters 8 and 9, respectively, and intersymbol interference is removed. The baseband QAM signals (complex signals) from the roll-off filters 8 and 9 are given to the complex multiplier 10 and the frequency error detector 11. Frequency error detection circuit 11
Detects the frequency error of the complex signal from the roll-off filters 8 and 9. The frequency error signal from the frequency error detection circuit 11 is smoothed by the loop filter 7 and then N
It is supplied to CO6. The NCO 6 oscillates according to the smoothed frequency error signal and outputs an oscillation output to the sin / cos converter 5. In this way, AFC control for controlling the carrier frequency is performed.

The complex multiplier 10 has sin / cos which will be described later.
The in-phase carrier and the quadrature-axis carrier from which the phase error has been removed are also provided from the converter 13. The complex multiplier 10 demodulates the QAM signal by synchronous detection using these carriers to obtain an I signal and a Q signal. These I and Q signals are given to the equalizer 16 and the interference such as reflection is removed and then output through the output terminals 18 and 19.

The output of the equalizer 16 is also given to the phase error detector 17. The phase error detector 17 detects a carrier phase error from the I and Q signals. The phase error signal from the phase error detector 17 is smoothed by the loop filter 15 and then NC.
Given to O14. The NCO 14 oscillates according to the smoothed phase error signal, and outputs the oscillation output from the sin / cos converter 13
Output to In this way, the PLL control is performed and the phase error of the reproduced carrier is removed.

The loop control circuit 12 includes loop filters 7 and 15
To control the AFC loop and the PLL loop. The loop control circuit 12 first controls the AFC loop at a first predetermined time to remove a frequency error, and then controls the PLL loop to establish phase synchronization. That is, the loop control circuit 12 measures the time and outputs control signals indicating the AFC period and the PLL period to the loop filters 7 and 15 respectively.
To supply.

The loop filter 7 operates on the basis of the control signal from the loop control circuit 12 during the AFC period and stops during the PLL period to hold the smoothed frequency error signal. The loop filter 15 starts operating based on the control signal from the loop control circuit 12 in the PLL period. Further, the loop filter 15 supplies the leak signal to the loop filter 7. If there is a residual frequency error after quadrature detection, the inter-symbol interference removal by the roll-off filters 8 and 9 cannot be performed sufficiently. Since the residual frequency error is accumulated in the loop filter 15, the loop filter 15 removes the residual frequency error by supplying the accumulated residual frequency error as a leak signal to the loop filter 7.

FIG. 8 is a block diagram showing a specific structure of the frequency error detector 11 shown in FIG.

The frequency error detection circuit 11 is supplied with the I- and Q-axis complex signals from the roll-off filter 8. These complex signals are input to the arctangent ROM 21 which operates as a phase detector. Arctangent ROM
21 obtains phase data θ by finding the arctangent of the complex signal of the I and Q axes. The phase data from the arctangent ROM 21 is given to the subtractor 23, and after being delayed by the delay unit 22, given to the subtractor 23. The subtractor 23 subtracts the delay signal from the phase data θ of the arctangent ROM 21. That is, the difference calculation by the delay unit 22 and the subtractor 23 corresponds to the time differential calculation of the phase data. The time derivative of the phase indicates the frequency component, and the subtractor 23 outputs the phase change of the complex signal of the I and Q axes, that is, the frequency error.

FIG. 9 is a block diagram showing a specific configuration of the phase error detector 17 in FIG. Further, FIG. 10 is a graph for explaining the phase error detection method on the IQ plane.

The phase error detector 17 is supplied with the I and Q signals synchronously detected from the equalizer 16. These I and Q signals are given to the symbol determiner 26, the subtractor 25 and the complex multiplier 27, respectively. The symbol determiner 26 determines the original symbol position of the input complex signal. Figure 11 shows 16-value QAM
5 is an explanatory diagram showing symbol positions on the IQ plane in FIG. A black circle in FIG. 11 indicates a symbol position, and the symbol determiner 26 indicates a black circle when the input I and Q signal values are values within each area indicated by the broken line in FIG. It is determined to be the value of the symbol position at the center of each area. The symbol determiner 26 outputs the determination result to the subtractor 25.

In FIG. 10, the positions of the input I and Q signals on the IQ plane are indicated by white circles, and the symbol determiner is used.
The symbol judgment position by 26 is indicated by a black circle. The detected I and Q signals and the original symbol are vector Vin and V.
And the angles are θ and φ, respectively, the obtained phase error is θ−φ, as shown in FIG. Also, the vector V
When the lengths of in and V are A, the vectors Vin and V are represented by the following equations (1) and (2).

Vin = Acosθ + jAsinθ (1) V = Acosφ tens jAsinφ (2) Further, Im [] represents an imaginary number component in [], and co
Letting nj () be a function for finding the conjugate complex number of the complex signal in parentheses, a value proportional to the phase error can be obtained by the following equation (3).

[0017] The subtractor 25 obtains V-Vin, which is the difference between the detected I and Q signals and the symbol position, and outputs it to the complex multiplier 27. The complex multiplier 27 performs complex multiplication of the output of the subtracter 25 and the input I and Q signals. As a result, the operation of the equation (3) is performed, and the complex multiplier 27 outputs a phase error signal proportional to the phase error shown on the right side of the equation (3).

Thus, in FIG. 7, the frequency error detector 11 and the phase error detector 17 are used to reproduce the carrier wave.
Is provided. However, the frequency error detector 11
And the phase error detector 17, as shown in FIGS. 8 and 9,
Since it has an arctangent ROM and a complex multiplier having a large circuit scale, there is a problem that the circuit scale is extremely large.

[0019]

As described above, the conventional circuit having the arctangent ROM and the complex multiplier has a problem that the circuit scale is extremely large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a carrier recovery circuit capable of reducing the circuit scale.

[0021]

A carrier recovery circuit according to claim 1 of the present invention comprises an automatic frequency control loop and a phase synchronization control loop for reproducing a reproduction carrier from a received signal, and the phase synchronization control loop. A phase error detecting means having a complex multiplier for detecting a phase error of the reproduced carrier wave and outputting a phase error signal; and the regenerated carrier wave formed by using the complex multiplier in the automatic frequency control loop. Frequency error detecting means for detecting a frequency error of the reproduced carrier and outputting a frequency error signal, and the complex multiplier used for detecting the frequency error during a predetermined automatic frequency control period for removing the frequency error of the reproduced carrier wave. The present invention further comprises control means for using the complex multiplier for detecting a phase error during a predetermined phase synchronization control period for removing a phase error of a carrier wave. The carrier wave regenerating circuit according to claim 1 is configured in the automatic frequency control loop and the phase synchronization control loop for regenerating the regenerated carrier wave from the received signal, and has a phase detection ROM and has a frequency error of the regenerated carrier wave. And a frequency error detecting means for detecting a frequency error signal and outputting the frequency error signal by detecting the phase error of the reproduced carrier wave using the phase detection ROM. Phase error detection means and predetermined phase synchronization control for removing the phase error of the reproduced carrier by using the phase detection ROM for detecting the frequency error during a predetermined automatic frequency control period for removing the frequency error of the reproduced carrier. And a control means for using the phase detection ROM for detecting a phase error during a period.

In claim 1 of the present invention, the phase error detecting means in the phase locked control loop is controlled by the control means to detect the phase error of the reproduced carrier wave using the complex multiplier during the phase locked control period. The control means uses a complex multiplier for frequency error detection during the automatic frequency control period. Accordingly, the frequency error detecting means in the automatic frequency control loop detects the frequency error by using the complex multiplier during the automatic frequency control period.

In claim 2 of the present invention, the frequency error detection means in the automatic frequency control loop is controlled by the control means to detect the frequency error of the reproduced carrier wave using the phase detection ROM during the automatic frequency control period. . The control means uses the phase detection ROM for phase error detection during the phase synchronization control period. As a result, the phase error detection means in the phase synchronization control loop detects the phase error using the phase detection ROM during the phase synchronization control period.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a multi-level QAM in which a carrier recovery circuit according to an embodiment of the present invention is incorporated.
It is a block diagram which shows a demodulator. In FIG. 1, the same components as those in FIG. 7 are denoted by the same reference numerals.

An IF (intermediate frequency) signal is input to the input terminal 1. This IF signal is, for example, multi-valued QAM-modulated digital signal, and then quadrature-modulated and transmitted on the transmitting side. The IF (intermediate frequency) signal from the input terminal 1 is given to the A / D converter 2. The A / D converter 2 is I
The F signal is converted into a digital signal and output to the multipliers 3 and 4.

Multipliers 3 and 4 are given in-phase and quadrature-axis carriers from a sin / cos converter 5, which will be described later, and perform quadrature demodulation by multiplication with an input signal.
The I-axis and Q-axis baseband QAM signals from the multipliers 3 and 4 are applied to roll-off filters 8 and 9, respectively. The roll-off filters 8 and 9 remove inter-code interference of the input QAM signal and output it to the complex multiplier 10.

The complex multiplier 10 has sin / cos which will be described later.
An in-phase axis carrier and a quadrature axis carrier are given from the converter 13, and synchronous detection is performed by multiplying the input I and Q axis complex signals by the in-phase axis carrier and the quadrature axis carrier, and I and Q axis detection. The output is output to the equalizer 16. The equalizer 16 removes interference such as reflection from the input signal and outputs I and Q signals to the output terminals 18 and 19, respectively.

In the present embodiment, the outputs of the roll-off filters 8 and 9 are also supplied to the delay device 31 and the selector 32. The selector 32 is also supplied with the I and Q signals from the equalizer 16. The delay device 31 delays the outputs of the roll-off filters 8 and 9 by a unit time T and selects the selector 34.
Output to The determination result from the symbol determiner 33 is also given to the selector 34. The symbol determiner 33 determines the symbol positions of the I and Q signals from the equalizer 16 and outputs the determination result to the selector 34.

The selectors 32 and 34 are controlled by the loop control circuit 12. The loop control circuit 12 is a loop filter 7,
By controlling 15, loop control of the AFC loop and the PLL loop is performed. That is, the loop control circuit 12 supplies the control signals indicating the AFC period and the PLL period to the loop filters 7 and 15, respectively, by measuring the time. In addition, the loop control circuit 12 controls the AFC period and the PLL.
The control signal indicating the period is also output to the selectors 32 and 34.

The selectors 32 and 34 select the outputs of the roll-off filters 8 and 9 or the output of the delay device 31 during the AFC period and the outputs of the equalizer 16 or the symbol during the PLL period based on the control signals. The output of the determiner 33 is selected. The output of the selector 34 is given to the subtractor 35, and the output of the selector 32 is given to the subtractor 35 and the complex multiplier 36.

The subtractor 35 subtracts the output of the selector 32 from the output of the selector 34 and outputs it to the complex multiplier 36. The complex multiplier 36 performs complex multiplication of the output of the selector 32 and the output of the subtractor 35. The complex multiplier 36 outputs the multiplication result of the AFC period to the loop filter 7 as a frequency error signal, and outputs the multiplication result of the PLL period to the loop filter 15 as a phase error signal. The loop filter 7 operates only in the AFC period by the control signal of the loop control circuit 12, smoothes the frequency error signal from the complex multiplier 36, and outputs N
Output to CO6. Further, the loop filter 15 is a PLL
During the period, the phase error signal from the complex multiplier 36 is smoothed and output to the NCO 14. Also, the loop filter 15
Supplies the residual frequency error to the loop filter 7 as a leak signal.

That is, in this embodiment, the AFC loop and the PLL loop share the subtractor 35 and the complex multiplier 36 by switching the inputs by the selectors 32 and 34.

Multipliers 3, 4, sin / cos converter 5,
A quadrature detection circuit is configured by the numerically controlled oscillator (hereinafter referred to as NCO) 6. The NCO 6 is controlled by the output of the loop filter 7 and outputs a numerical value for generating a reproduction carrier of a predetermined frequency to the sin / cos converter 5. The sin / cos converter 5 is an NCO 6
The I-axis carrier having a predetermined frequency is reproduced and given to the multiplier 3 and the Q-axis carrier having a predetermined frequency is reproduced and given to the multiplier 4 on the basis of the numerical value from. Further, the NCO 14 oscillates in response to the smoothed phase error signal and outputs the oscillation output as s
Output to the in / cos converter 13. The sin / cos converter 13 is based on the numerical value from the NCO 14
The axis carrier and the Q axis carrier are reproduced and given to the complex multiplier 10.

Next, the operation of the embodiment thus configured will be described with reference to the explanatory view showing the IQ plane of FIG.

The IF signal input through the input terminal 1 is converted into a digital signal by the A / D converter 2 and then given to the multipliers 3 and 4. The multipliers 3 and 4 are s
Quadrature detection is performed by multiplying the IF signal by the I-axis carrier or Q-axis carrier from the in / cos converter 5 and I,
The Q-axis baseband QAM signal is output to the roll-off filters 8 and 9. Inter-symbol interference is removed from the QAM signal by the roll-off filters 8 and 9 and given to the complex multiplier 10. The complex multiplier 10 performs complex detection by performing complex multiplication between the I / Q axis carrier from the sin / cos converter 13 and the input I / Q axis QAM signal. The I and Q signals from the complex multiplier 10 are waveform-equalized by the equalizer 16 and output through output terminals 18 and 19.

Regeneration of the carrier wave is performed by the AFC loop and the PLL loop. First, the loop control circuit 12
AFC control is performed by outputting a control signal indicating the FC period,
Next, the control signal indicating the PLL period is output to perform the PLL control. The operation during PLL control is almost the same as the conventional one.
During the PLL period, the selector 32 selects the output of the equalizer 16,
The selector 34 selects the output of the symbol determiner 33. The symbol determiner 33 determines the original symbol position of the detected I and Q signals, and the determination result is passed through a selector 34 to a subtractor 35.
Output to Also, the detected I and Q signals are selected by the selector 32.
Is given to the subtractor 35 as it is.

The subtractor 35 selects from the output of the selector 34
The output of 32 is subtracted and output to the complex multiplier 36. The complex multiplier 36 performs complex multiplication between the output of the selector 32 and the output of the subtractor 35. That is, the subtractor 35 and the complex multiplier 36 perform the calculation shown in the equation (3), and a phase error signal proportional to the phase error shown on the right side of the equation (3) is obtained. This phase error signal is supplied from the complex multiplier 36 to the loop filter 15, smoothed, and then supplied to the NCO 14. In this way, the PLL control is performed to remove the phase error.

On the other hand, the AFC control is performed by the AFC loop. When the control signal indicating the AFC period is output by the loop control circuit 12, the selector 32 selects the output of the roll-off filters 8 and 9, and the selector 34 selects the output of the delay device 31. The delay device 31 delays the outputs of the roll-off filters 8 and 9 by a unit time and supplies them to the selector 34.

The outputs of the selectors 32 and 34 are given to the subtractor 35. That is, the quadrature detection output before and after the unit time is given to the subtractor 35. Now, for example, a complex signal obtained by quadrature detection before a predetermined time is represented by a vector X in FIG. 2, and a complex signal obtained by quadrature detection after a predetermined time is represented by a vector Y in FIG. And Vector X
The complex signal represented by is supplied from the selector 34 to the subtractor 35, and the complex signal represented by the vector Y is represented by the selector 32.
Is given to the subtractor 35 via.

The subtractor 35 subtracts the vector X from the vector Y and outputs it to the complex multiplier 36. The complex multiplier 36 performs complex multiplication between the vector Y and the vector (Y−X). FIG.
Assuming that the angles of the vectors X and Y of θ are θ1 and θ2, respectively, the imaginary number component of the multiplication result of the complex multiplier 36 becomes a value proportional to θ2-θ1. That is, the output of the complex multiplier 36 represents the time derivative of the phase, that is, the frequency shift (error). In this way, AF
During the period C, the frequency error signal is supplied from the complex multiplier 36 to the loop filter 7, and AFC control is performed.

As described above, in the present embodiment, A
The circuits of the FC loop and the PLL loop can be partially shared, the arctangent ROM used for detecting the frequency error is omitted, and the subtractor 35 and the complex multiplier 36 are not only used for detecting the phase error, It can also be used for detecting a frequency error, and the circuit scale can be reduced.

FIG. 3 is a block diagram showing another embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the embodiment of FIG. 1, the subtractor 35 and the complex multiplier 36 are also used in the AFC control and the PLL control, but in this embodiment, the arc tangent ROM as the phase detector is shared so that the circuit This is an example in which the complex multiplier 36 having a large scale can be omitted.

In this embodiment, the delay unit 31 and the selector shown in FIG.
1 in that the arctangent ROM 41, the delay unit 42, the selector 43, the conversion table 44, and the subtractor 45 are provided by removing the 34, the subtractor 35, and the complex multiplier 36.

The output of the selector 32 is given to the arctangent ROM 41 as a phase detector. The arctangent ROM 41 outputs phase data indicating the phase of the output of the selector 32 to the delay device 42 and the subtractor 45. The delay device 42 delays the phase data from the arctangent ROM 41 by a unit time T and outputs it to the selector 43. The output of the symbol determiner 33 is given to the conversion table 44. The conversion table 44 converts the symbol position determined by the symbol determiner 33 into a phase, and outputs the phase data corresponding to the symbol position to the selector 43. The conversion table 44
In 16-value QAM, it is sufficient to hold 16 data, and the circuit scale is extremely small.

The selector 43 operates from the loop control circuit 12 to the AF
When the control signal indicating the C period is applied, the output of the delay device 42 is selected, and when the control signal indicating the PLL period is applied, the output of the conversion table 44 is selected and output to the subtractor 45. Has become. Subtractor 45 is Arctangent R
The output of the selector 43 is subtracted from the output of the OM41, the subtraction result is given to the loop filter 7 as the frequency error signal during the AFC period, and the subtraction result is output to the loop filter 15 as the phase error signal during the PLL period. There is.

Next, the operation of the embodiment configured as described above will be described.

The operations of the quadrature detection by the multipliers 3 and 4 and the synchronous detection by the complex multiplier 10 are the same as those in the embodiment of FIG. Now, it is assumed that the loop control circuit 12 specifies the AFC period. In this case, the selector 32 selects the output of the roll-off filters 8 and 9 and supplies it to the arctangent ROM 41, and the selector 43 selects the output of the delay device 42 and supplies it to the subtractor 45. That is, in this case, FIG.
A frequency error detector similar to is constructed. The arctangent ROM 41 outputs the input phase data of the quadrature detection output to the delay device 42 and the subtractor 45. The delay device 42 delays the input phase data by a unit time, and the selector 43
To the subtractor 45 via. The subtracter 45 obtains the difference between the phase data before and after the unit time, and outputs the difference as a frequency error signal to the loop filter 7.

Next, it is assumed that the PLL period is set by the loop control circuit 12. In this case, the selector 32
Is the output of the equalizer 16 and the arctangent ROM
Then, the selector 43 selects the output of the conversion table 44 and outputs it to the subtractor 45. The complex signal synchronously detected by the complex multiplier 10 is supplied to the symbol determiner 33 and the arc tangent R via the selector 32.
Given to OM41. The symbol determiner 33 determines the original symbol position and gives the determination result to the conversion table 44, and the conversion table 44 converts this determination result into phase data.
Further, the arctangent ROM 41 obtains the phase of the output of the equalizer 16.

Now, it is assumed that the complex signal from the equalizer 16 is represented by the vector Vin in FIG. 10 and the determination result of the symbol determiner 33 is represented by the vector V. In this case, the output of the arctangent ROM 41 corresponds to the phase θ of FIG. 10, and the output of the conversion table 44 corresponds to the phase φ of FIG. The output of the conversion table 44 is the subtractor via the selector 43.
Given to 45. The subtractor 45 is an arctangent ROM
The output of the conversion table 44 is subtracted from the output of 41. That is,
The output of the subtractor 45 becomes θ−φ, and the phase error is obtained. The phase error signal from the subtractor 45 is given to the loop filter 15.

The other operations are the same as those of the embodiment shown in FIG.

As described above, in the present embodiment, the complex multiplier used for phase error detection is omitted, and the arc tangent RO for phase detection used in frequency error detection is used.
The phase error is detected using M. Since the arctangent ROM is commonly used for the frequency error detection and the phase error detection, the circuit scale can be reduced.

In each of the above embodiments, the AF
In consideration of the case where the residual frequency error in the C control affects the demodulation performance, a leak signal was supplied from the loop filter 15 of the PLL loop to the loop filter 7 of the AFC loop to remove the residual frequency error. Depending on the system, the residual frequency error in the AFC control may not affect the demodulation performance. In this case, the loop filter of the AFC loop and the PLL loop can be used together, and the circuit scale can be further reduced.

FIG. 4 shows an example in which the loop filter is shared in this way. FIG. 4 corresponds to the embodiment of FIG. 4, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 4, the output of the complex multiplier 36 is given to the loop filter 51. The loop filter 51 is controlled by the loop control circuit 12 to have a filter characteristic for AFC control during the AFC period, to smooth the frequency error signal from the complex multiplier 36 and output it to the NCO 52 during the PLL period. Is set to the filter characteristic for PLL control, and the phase error signal from the complex multiplier 36 is smoothed and output to the NCO 53.

The NCO 52 is controlled by the loop control circuit 12 and operates only during the AFC period, and the NCO 53 is operated by the loop control circuit 12
It is controlled to operate only during the PLL period. NCO52, 53
Respectively generate oscillation outputs based on the frequency error signal or the phase error signal of the loop filter 51 and output them to the sin / cos converters 5 and 13.

It is clear that even with such a configuration, the same operation and effect as those of the embodiment shown in FIG. 1 can be obtained.

FIG. 5 shows an example in which the loop filter is shared in the embodiment shown in FIG. 5, the same components as those in FIGS. 3 and 4 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 5, the output of the subtractor 45 is given to the loop filter 51. The loop filter 51 is controlled by the loop control circuit 12 to have a filter characteristic for AFC control during the AFC period, to smooth the frequency error signal from the subtractor 45 and output it to the NCO 52, and during the PLL period. P
The phase error signal from the subtractor 45 is smoothed by being set to the filter characteristic for LL control and output to the NCO 53.

It is clear that even with such a structure, the same operation and effect as those of the embodiment shown in FIG. 3 can be obtained.

FIG. 6 is a block diagram showing another embodiment of the present invention. 6, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In each of the above embodiments, the loop control circuit 12 measures the time and switches between the AFC control and the PLL control, but in the present embodiment, the AFC control is performed by determining the convergence of the frequency error. This is applied to an example of switching between PLL control.

In FIG. 6, the output of the loop filter 7 is given to the loop control circuit 61. The loop control circuit 61 is
The output of the loop filter 7 determines the stability of the frequency error signal. When the loop control circuit 61 determines that the frequency error signal is stable, the loop control circuit 61 determines from the AFC control to the PL
The control signal is switched to the L control and a control signal indicating the PLL period is output. The control signal from the loop control circuit 61 is applied to the loop filters 7 and 15 and the selectors 32 and 34.

In the embodiment constructed as described above, first, the loop control circuit 61 performs AFC control. The control signal from the loop control circuit 61 is given to the loop filters 7 and 15, and the loop filter 7 is brought into an operating state. The quadrature-detected complex signal and its delayed signal are selected by the selectors 32 and 34, and the frequency error is detected. The frequency error signal from the complex multiplier 36 is supplied to the loop filter 7 where it is smoothed and then given to the NCO 6 for AFC control.

Further, the output of the loop filter 7 is also given to the loop control circuit 61. The loop control circuit 61 determines the stability of the frequency error signal from the output of the loop filter 7. When the frequency error signal converges and becomes stable, the loop control circuit 61 switches the control to the PLL control. That is, the loop control circuit 61 activates the loop filter 15 and
The selectors 32 and 34 are caused to select the outputs of the equalizer 16 and the symbol determiner 33, respectively.

As a result, the phase error signal is supplied from the complex multiplier 36 to the loop filter 15, and the PLL control is performed.

As described above, in the present embodiment as well, FIG.
The same effect as that of the embodiment can be obtained. In the embodiment of FIG. 1, the switching time from AFC control to PLL control is set in consideration of the case where the pull-in time of the AFC loop is relatively long, such as the case where C / N is deteriorated. Although necessary, in the present embodiment, the control is switched after determining the convergence of the frequency error.
There is an advantage that switching can be automatically performed according to the reception state.

It is obvious that this embodiment can be applied to the embodiment shown in FIG.

[0068]

As described above, according to the present invention, there is an effect that the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a multilevel QAM demodulator in which a carrier recovery circuit according to an embodiment of the present invention is incorporated.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a modification of the embodiment shown in FIG.

5 is a block diagram showing a modification of the embodiment of FIG.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a multilevel QAM incorporating a conventional carrier recovery circuit.
The block diagram which shows a demodulator.

8 is a block diagram showing a specific configuration of the frequency error detector shown in FIG.

9 is a block diagram showing a specific configuration of the phase error detector in FIG.

FIG. 10 is an explanatory diagram for explaining detection of a phase error.

FIG. 11 is an explanatory diagram for explaining symbol positions.

[Explanation of symbols]

7, 15 ... Loop filter, 12 ... Loop control circuit, 31 ... Delay device, 32, 34 ... Selector, 33 ... Symbol judger, 35 ... Subtractor, 36 ... Complex multiplier

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Sugita 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Multimedia Technology Laboratory

Claims (6)

[Claims] 1. An automatic frequency control loop and a phase-locked control loop for regenerating a regenerated carrier from a received signal, and a complex multiplier included in the phase-locked control loop to detect a phase error of the regenerated carrier. Phase error detecting means for outputting a phase error signal and a frequency error detecting means configured in the automatic frequency control loop for detecting the frequency error of the reproduced carrier wave using the complex multiplier and outputting the frequency error signal. And using the complex multiplier for detecting a frequency error during a predetermined automatic frequency control period for removing the frequency error of the reproduced carrier, and performing the complex multiplication during a predetermined phase synchronization control period for removing the phase error of the reproduced carrier. And a control means for detecting the phase error. 2. An automatic frequency control loop and a phase synchronization control loop for reproducing a reproduced carrier wave from a received signal, and an R for phase detection which is formed in the automatic frequency control loop.
A frequency error detecting means having an OM for detecting a frequency error of the reproduced carrier wave and outputting a frequency error signal; and a phase of the reproduced carrier wave constituted by the phase synchronization control loop and using the phase detecting ROM. Phase error detecting means for detecting an error and outputting a phase error signal; and the phase detecting ROM for detecting the frequency error during a predetermined automatic frequency control period for removing the frequency error of the reproduced carrier wave. And a control means for using the phase detecting ROM for detecting the phase error during a predetermined phase synchronization control period for removing the phase error. 3. The automatic frequency control loop comprises a first loop filter for removing high frequency components of the frequency error signal, and the phase locked control loop removes high frequency components of the phase error signal, A second loop filter for outputting a frequency error to the first loop filter during the phase synchronization control period is provided.
The carrier recovery circuit according to any one of 1. 4. The automatic frequency control loop and the phase synchronization control loop remove high frequency components of the frequency error signal during the automatic frequency control period, and remove high frequency components of the phase error signal during the phase synchronization control period. The carrier recovery circuit according to claim 1, further comprising a third loop filter that removes the third loop filter. 5. The control means has a time measuring device, and sets the automatic frequency control period and the phase synchronization control period based on the output of the time measuring device. 2. The carrier recovery circuit according to any one of 2. 6. The control means has a determination means for determining the stability of the frequency error signal, and sets the automatic frequency control period and the phase synchronization control period based on the output of the determination means. The carrier recovery circuit according to claim 1, wherein the carrier recovery circuit is a carrier recovery circuit.