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JPH09130169A - Converter for converting single-ended input into differential output signal, method for generating differential output signal dependently on input, and converter for converting differential input voltage into single-ended output voltage - Google Patents

Converter for converting single-ended input into differential output signal, method for generating differential output signal dependently on input, and converter for converting differential input voltage into single-ended output voltage

Info

Publication number
JPH09130169A
JPH09130169A JP8256335A JP25633596A JPH09130169A JP H09130169 A JPH09130169 A JP H09130169A JP 8256335 A JP8256335 A JP 8256335A JP 25633596 A JP25633596 A JP 25633596A JP H09130169 A JPH09130169 A JP H09130169A
Authority
JP
Japan
Prior art keywords
input
voltage
converter
input terminal
ended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8256335A
Other languages
Japanese (ja)
Inventor
Frederic M Stubbe
フレデリック・エム・スタッブ
Daryush Shamlou
ダリューシュ・シャムロウ
Kashif A Ahmed
カシフ・エイ・アメド
Guangming Yin
ガンミン・イン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of JPH09130169A publication Critical patent/JPH09130169A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45479Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45932Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by using feedback means
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45Indexing scheme relating to differential amplifiers
    • H03F2203/45528Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce in phase input requirement without causing excess power consumption and without increasing the complexity of components by changing precisely a resistance rate of input and feedback resistors. SOLUTION: The converter includes a complete differential amplifier whose one input terminal is coupled with a single end input and the other input terminal is coupled with a point of a fixed voltage (e.g. AGND). The converter includes a 1st receiver R1 connected between the single end input and a noninverting input terminal of the complete differential amplifier, a 2nd resistor R2 connected between a point of a fixed voltage (e.g. AGND) and an inverting input terminal of the complete differential amplifier, a 3rd resistor R3 coupled between the noninverting input terminal and the inverting input terminal of the complete differential amplifier, and a 4th resistor R4 coupled between the inverting input terminal and the noninverting input terminal. Then the resistance is selected by a relation of R3 /R1 ≠R4 /R2 .

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の分野】本発明は差動増幅器回路に関し、より特
定的には単終端−差動および差動−単終端コンバータに
関する。
FIELD OF THE INVENTION The present invention relates to differential amplifier circuits, and more particularly to single-ended-to-differential and differential-to-single-ended converters.

【0002】[0002]

【技術的背景】典型的な演算増幅器を図1に示す。当業
者には容易に認識されるように、出力信号と入力信号と
の間の関係は一般にVOUT /Vin=−R3 /R1 と表わ
される。増幅器への正入力は、典型的には正および負の
供給レール間の中途にあるアナログ接地(「AGN
D」)に接続されることに注目されたい。増幅はしたが
ってR3 対R1 の抵抗率によって規定される。
TECHNICAL BACKGROUND A typical operational amplifier is shown in FIG. As will be readily appreciated by those skilled in the art, the relationship between the output signal and the input signal is commonly expressed as V OUT / V in = −R 3 / R 1 . The positive input to the amplifier is typically an analog ground ("AGN") midway between the positive and negative supply rails.
Note that it is connected to D "). Amplification is thus defined by the resistivity of R 3 to R 1 .

【0003】ダイナミックレンジの高い応用について
は、図2で記号により示されるもののような差動回路が
所望される。差動回路の必要とするものは単純である。
ピーク間電圧が2vの入力電圧については、出力すなわ
ちINPおよびINMが、+2vから−2vの差動出力
範囲を生成し、これにより増幅器の電源電圧を増大させ
ることなく入力信号の有効なダイナミックレンジが2倍
になる。この、増幅器におけるより高いダイナミックレ
ンジは、低電力のオーディオまたは音声処理回路では極
めて望ましいものである。
For high dynamic range applications, a differential circuit such as that shown symbolically in FIG. 2 is desired. The need for a differential circuit is simple.
For an input voltage with a peak-to-peak voltage of 2v, the outputs, INP and INM, produce a differential output range of + 2v to -2v, which results in an effective dynamic range of the input signal without increasing the amplifier supply voltage. Doubles. This higher dynamic range in the amplifier is highly desirable in low power audio or voice processing circuits.

【0004】図3は、差動入力INMおよびINP、な
らびに差動出力OUTPおよびOUTMを備える典型的
な差動増幅器の回路図である。この回路の利得は一般
に、後に示す式(a)によって表わされる。
FIG. 3 is a circuit diagram of a typical differential amplifier having differential inputs INM and INP and differential outputs OUTP and OUTM. The gain of this circuit is generally represented by equation (a) shown below.

【0005】当業者には通常知られているように、同相
入力電圧VCM(≡(VA +VB )/2))は固定されて
おり、かつ完全な差動増幅器の場合には差動入力から独
立していることに注目されたい。
As is commonly known to those skilled in the art, the common mode input voltage V CM (≡ (V A + V B ) / 2)) is fixed and, in the case of a fully differential amplifier, differential. Note that it is independent of input.

【0006】従来の単終端−差動増幅器は、図4に示さ
れており、これは図2および3の組合せからもたらされ
るものである。正端子における増幅器への入力は、ここ
ではAGNDに接続されていることに注目されたい。こ
の図4の増幅器の利得は、INがAGNDに比例するの
で、やはり後に示す式(b)で表されるものである。
A conventional single-ended-differential amplifier is shown in FIG. 4, which results from the combination of FIGS. Note that the input to the amplifier at the positive terminal is now connected to AGND. Since IN is proportional to AGND, the gain of the amplifier of FIG. 4 is also represented by the equation (b) shown later.

【0007】しかしながら、同相入力電圧VCM、すなわ
ち(VA +VB )/2は、ここでは次の式(c)で示す
態様で入力電圧INとともに変化する。
However, the common mode input voltage V CM , that is, (V A + V B ) / 2, changes with the input voltage IN in the manner shown by the following equation (c).

【0008】[0008]

【数7】 (Equation 7)

【0009】したがって、INが減少した場合、VCM
そのOUTPとの関連のために減少するし、その反対も
ある。実際的な言い方をするならば、図4における差動
増幅器の同相入力電圧は、図3の完全な差動増幅器にお
ける差動入力からの独立性とは対照的に、入力信号に従
って変化する。
Thus, when IN decreases, V CM also decreases due to its association with OUTP and vice versa. In practical terms, the common mode input voltage of the differential amplifier in FIG. 4 varies according to the input signal, as opposed to the independence from the differential inputs in the fully differential amplifier of FIG.

【0010】この依存性は、特に2.7vなどの低い電
源電圧を伴う応用の場合には、単終端−差動増幅器のた
めに大きな同相入力範囲を要求する。大きな同相入力電
圧は、差動対のテール電流に用いられるトランジスタを
強制的に強反転領域の代わりに線形領域で動作させる。
したがって、従来の単終端−差動増幅器には、増幅器へ
の大きな同相入力信号に対処するための相補入力段が必
要であり、その結果余分な電力およびより多くの構成要
素をもたらすこととなっていた。
This dependence requires a large common mode input range for the single-ended-to-differential amplifier, especially for applications with low supply voltages such as 2.7v. The large common mode input voltage forces the transistors used for the tail currents of the differential pair to operate in the linear region instead of the strong inversion region.
Therefore, conventional single-ended-to-differential amplifiers require complementary input stages to handle large common mode input signals to the amplifier, resulting in extra power and more components. It was

【0011】ダイナミックレンジの高い応用について
は、余分な電力消費を生じさせたり構成要素の複雑性を
増したりすることなく同相入力要求の低い単終端−差動
増幅器を有することが望ましい。
For high dynamic range applications, it is desirable to have a single-ended-differential amplifier with low common mode input requirements without incurring extra power consumption or increasing component complexity.

【0012】[0012]

【発明の概要】同相入力要求の緩和されている、改良さ
れた単終端−差動コンバータが開示される。入力および
フィードバック抵抗器に対する抵抗率を正確に変化させ
ることにより、入力同相率はいかなる必要な値にも下げ
ることができる。特定的には同相入力電圧は、フィード
バック抵抗器対固定電圧(たとえばAGND)に接続さ
れた入力抵抗器の比率を、入力信号に接続された抵抗器
間の対応する比率よりもずっと大きいものとすることに
よって下げられる。
SUMMARY OF THE INVENTION An improved single-ended-to-differential converter with reduced common mode input requirements is disclosed. By accurately changing the resistivities for the input and feedback resistors, the input common mode ratio can be lowered to any desired value. Specifically, the common mode input voltage causes the ratio of the feedback resistor to the input resistor connected to a fixed voltage (eg, AGND) to be much greater than the corresponding ratio between the resistors connected to the input signal. Can be lowered.

【0013】本発明に従い、正および負の出力端子を介
して単終端入力VINを差動出力信号VOUT に変換するた
めのコンバータが開示される。このコンバータは、その
入力端子の一方が単終端入力に結合され、その他方入力
端子が固定電圧(たとえばAGND)に結合された完全
な差動増幅器を含む。コンバータはまた、単終端入力と
完全な差動増幅器の正入力端子との間に結合された第1
の抵抗器(「R1 」)、固定電圧(たとえばAGND)
と完全な差動増幅器の負入力端子との間に結合された第
2の抵抗器(「R2 」)、完全な差動増幅器の正入力端
子と負出力端子との間に結合された第3の抵抗器(「R
3 」)、および負入力端子と正出力端子との間に結合さ
れた第4の抵抗器(「R4 」)を有し、そのような抵抗
器の値は、R3 /R1 ≠R4 /R2 によって支配され
る。
In accordance with the present invention, a converter is disclosed for converting a single-ended input V IN to a differential output signal V OUT via positive and negative output terminals. The converter includes a fully differential amplifier with one of its input terminals coupled to a single-ended input and the other input terminal coupled to a fixed voltage (eg, AGND). The converter also includes a first terminal coupled between the single-ended input and the positive input terminal of the fully differential amplifier.
Resistor ("R 1 "), fixed voltage (eg AGND)
A second resistor (“R 2 ”) coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a second resistor (“R 2 ”) coupled between the positive input terminal and the negative output terminal of the fully differential amplifier. 3 resistors ("R
3 "), and a fourth resistor (" R 4 ") coupled between the negative input terminal and the positive output terminal, the value of such resistor being R 3 / R 1 ≠ R Governed by 4 / R 2 .

【0014】同じ原理を、差動−単終端コンバータにも
応用することができる。本発明のさらなる目的、特徴お
よび利点は、次に述べる詳細な説明から当業者には明ら
かとなるであろう。
The same principles can be applied to differential-to-single-ended converters. Further objects, features and advantages of the invention will be apparent to those skilled in the art from the detailed description that follows.

【0015】[0015]

【好ましい実施例の詳細な説明】本発明に従う単終端−
差動増幅器の回路図が示される、図5を参照する。入力
抵抗器はR1 として表わされ、フィードバック抵抗器R
3 が出力OUTMと増幅器の正端子との間に結合され
る。もう1つのフィード抵抗器R4 が、出力OUTPと
増幅器の負端子との間に結合され、一方で入力抵抗器R
2 が負端子とAGNDとの間に結合される。
Detailed Description of the Preferred Embodiment Single Termination According to the Invention-
Reference is made to FIG. 5, where a circuit diagram of a differential amplifier is shown. The input resistor is represented as R 1 and the feedback resistor R
3 is coupled between the output OUTM and the positive terminal of the amplifier. Another feed resistor R 4 is coupled between the output OUTP and the negative terminal of the amplifier, while the input resistor R 4
2 is coupled between the negative terminal and AGND.

【0016】従来の単終端−差動増幅器における同相入
力の要求の問題に対処するため、抵抗器R1 、R2 、R
3 およびR4 は、それらの従来の図4でのような対称性
が取除かれ、R3 /R1 ≠R4 /R2 となるように設定
される。
To address the problem of common mode input requirements in conventional single-ended-differential amplifiers, resistors R 1 , R 2 , R.
3 and R 4 are set so that their conventional symmetry as in FIG. 4 is removed and R 3 / R 1 ≠ R 4 / R 2 .

【0017】さらに、単終端−差動増幅器の同相入力の
要求を軽減するため、抵抗器R1 、R2 、R3 およびR
4 の値は以下に示す組合せられた関係に従い調節され得
る。(増幅器の利得は無限であると仮定)
Furthermore, in order to reduce the requirement for the common mode input of the single- ended- differential amplifier, the resistors R 1 , R 2 , R 3 and R are used.
The value of 4 can be adjusted according to the combined relationships shown below. (Assuming infinite amplifier gain)

【0018】[0018]

【数8】 (Equation 8)

【0019】ここでVCMは増幅器の入力における同相電
圧である。等式1および2を念頭においた上で、目標と
されるのはしたがって、等式1に従い所望される利得を
保持しつつ等式2を最小化するということとなる。
Where V CM is the common mode voltage at the input of the amplifier. With Equations 1 and 2 in mind, the goal is then to minimize Equation 2 while retaining the desired gain according to Equation 1.

【0020】たとえば、従来の増幅器については、R3
はR1 の2倍であり、R4 はR2 の2倍である、すなわ
ちR3 /R1 =R4 /R2 である。この、これまで必要
とされてきた対称性はしかしながら、同相入力の要求が
増大するため、従来の単終端−差動増幅器を、電源電圧
の低い応用について完全に非動作的ではないとしても、
より複雑なものとしてきた。同相入力の要求、すなわち
CM/VIN比を軽減するため、比率R3 /R1 は等式2
で見て取れるようにR4 /R2 よりもずっと大きいもの
とされる必要がある。また等式1を満たすため、R3
大きいR4 /R 2 の結果としての利得を補償すべくR1
とほぼ同じにされる。
For example, for a conventional amplifier, RThree
Is R1Is twice that of RFourIs RTwoThat's twice as much
ChiRThree/ R1= RFour/ RTwoIt is. This ever needed
However, the requirement for in-phase input is
To increase conventional single-ended-to-differential amplifier,
Is not completely non-operational for low-end applications,
It has become more complicated. In-phase input request, ie
Vcm/ VINRatio R to reduce the ratioThree/ R1Is equation 2
As you can see in RFour/ RTwoMuch bigger than
Need to be Also, to satisfy Equation 1, RThreeIs
Large RFour/ R TwoR to compensate the gain as a result of1
Is almost the same as.

【0021】当業者によって認識されるように、単終端
−差動コンバータのための同相入力の要求を緩和する同
じ原理を、図6に示されるように差動−単終端コンバー
タに応用することができる。
As will be appreciated by those skilled in the art, the same principles of relaxing the common mode input requirements for single-ended-to-differential converters can be applied to differential-to-single-ended converters as shown in FIG. it can.

【0022】図6では、差動入力信号VINがその正端子
INPを入力抵抗器R1 を介して増幅器の正端子に接続
されており、かつ負端子INMを入力抵抗器R2 を介し
て増幅器の負端子に接続されている。フィードバック抵
抗器R3 が、ノードBにおいて出力端子と正端子との間
に結合される。もう1つの抵抗器R4 が、負端子と固定
電圧(たとえばAGND)との間に結合される。
In FIG. 6, the differential input signal V IN has its positive terminal INP connected to the positive terminal of the amplifier via the input resistor R 1 and the negative terminal INM via the input resistor R 2. Connected to the negative terminal of the amplifier. Feedback resistor R 3 is coupled at node B between the output terminal and the positive terminal. Another resistor R 4 is coupled between the negative terminal and a fixed voltage (eg AGND).

【0023】この場合、抵抗器R1 、R2 、R3 および
4 は、次に示す等式に従い支配される。
In this case, the resistors R 1 , R 2 , R 3 and R 4 are governed according to the following equation:

【0024】[0024]

【数9】 (Equation 9)

【0025】以上、詳細に説明してきたのはいくつかの
例示的実施例のみであるが、当業者はこの発明の新規な
教示および利点から実質的に逸脱することなく多くの変
形がこれら例示的実施例においては可能であることを容
易に認識するであろう。したがって、そのような変形は
すべて前掲の特許請求の範囲において規定されたこの発
明の範囲内に含まれるものとして意図されている。特許
請求の範囲では、ミーンズ・プラス・ファンクション節
は、記載されている機能を行なうものとしてここで説明
されている構造、および構造的な等価物だけでなく等価
な構造をも包含するものとして意図される。つまり釘と
ねじとは、釘は木製の部品を合わせて固定するための円
筒形の表面を用いる一方で、ねじは螺旋状の表面を用い
ているという点においては構造的に等価ではないかもし
れないが、木製の部品を固定する環境内において、釘と
ねじとは等価な構造であり得るだろうということであ
る。
While only a few exemplary embodiments have been described in detail above, many variations will be apparent to those skilled in the art without substantially departing from the novel teachings and advantages of the invention. It will be readily appreciated that this is possible in the examples. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the appended claims. In the claims, the means-plus-function clause is intended to encompass structures described herein as performing the described functions, and not only structural equivalents but also equivalent structures. To be done. That is, nails and screws may not be structurally equivalent in that nails use cylindrical surfaces to secure wooden parts together while screws use helical surfaces. Although not, it is possible that nails and screws could be equivalent structures in an environment that secures wooden parts.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の増幅器を示す図である。FIG. 1 is a diagram showing a conventional amplifier.

【図2】記号により単終端−差動増幅器を示す図であ
る。
FIG. 2 is a diagram showing a single-ended-differential amplifier by a symbol.

【図3】従来の完全な差動増幅器を示す図である。FIG. 3 shows a conventional fully differential amplifier.

【図4】単終端−差動増幅器に対する従来のアプローチ
を示す図である。
FIG. 4 shows a conventional approach to a single-ended-differential amplifier.

【図5】本発明に従う単終端−差動増幅器を示す図であ
る。
FIG. 5 shows a single-ended-differential amplifier according to the present invention.

【図6】やはり本発明に従う差動−単終端コンバータを
示す図である。
FIG. 6 illustrates a differential-to-single-ended converter also in accordance with the present invention.

【符号の説明】[Explanation of symbols]

1 入力抵抗器 R2 入力抵抗器 R3 フィードバック抵抗器 R4 フィードバック抵抗器 VIN 差動入力信号 VOUT 差動出力信号R 1 input resistor R 2 input resistor R 3 feedback resistor R 4 feedback resistor V IN differential input signal V OUT differential output signal

───────────────────────────────────────────────────── フロントページの続き (72)発明者 ダリューシュ・シャムロウ アメリカ合衆国、92677 カリフォルニア 州、ラグーナ・ニゲル、ベル・メゾン、 30756 (72)発明者 カシフ・エイ・アメド アメリカ合衆国、92715 カリフォルニア 州、アーバイン、パークビュー・レーン、 3701、アパートメント・11−ディ (72)発明者 ガンミン・イン アメリカ合衆国、92715 カリフォルニア 州、アーバイン、パークビュー・レーン、 3900、アパートメント・6・シィ ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Darius Shamrow United States, 92677 California, Laguna Niger, Bell Maison, 30756 (72) Inventor Cassif A Amed United States, 92715 Irvine, California, Parkview Lane, 3701, Apartment 11-Di (72) Inventor Gunmin Inn United States, 92715 Parkview Lane, Irvine, California, 3900, Apartment 6Sii

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 単終端入力VINを正および負の出力端子
を介して差動出力信号VOUT に変換するためのコンバー
タであって、 その入力端子の一方が前記単終端入力に結合されてお
り、その他方入力端子が予め定められた固定電圧に結合
されている完全な差動増幅器を含み、前記完全な差動増
幅器は予め定められた同相電圧VCMを有し、さらに前記
単終端入力と前記完全な差動増幅器の前記正入力端子と
の間に結合される第1の抵抗器手段(「R1 」)と、 前記予め定められた固定電圧と前記完全な差動増幅器の
前記負入力端子との間に結合される第2の抵抗器手段
(「R2 」)と、 前記完全な差動増幅器の前記正入力端子と前記負出力端
子との間に結合される第3の抵抗器手段(「R3 」)
と、 前記負入力端子と前記正出力端子との間に結合される第
4の抵抗器手段(「R 4 」)とを含み、ここでR3 /R
1 ≠R4 /R2 である、コンバータ。
1. Single-ended input VINThe positive and negative output terminals
Differential output signal V viaOUTConvert to convert to
One of its input terminals is coupled to the single-ended input.
, The other input terminal is connected to a predetermined fixed voltage.
Including a fully differential amplifier that is
The width device has a predetermined common-mode voltage VcmAnd further
A single-ended input and the positive input terminal of the fully differential amplifier
A first resistor means ("R1)) Of the fully fixed differential amplifier with the predetermined fixed voltage
Second resistor means coupled between the negative input terminal
("RTwo)), The positive input terminal and the negative output terminal of the fully differential amplifier
A third resistor means ("RThree")
And a first coupling coupled between the negative input terminal and the positive output terminal.
4 resistor means ("R Four)) And where RThree/ R
1≠ RFour/ RTwoIs a converter.
【請求項2】 前記コンバータは次の式 【数1】 によって求められる前記単終端入力VIN対前記差動出力
OUT の利得率を有しており、前記コンバータはまた、
次の式 【数2】 により求められる前記単終端入力VINの前記予め定めら
れた同相電圧VCMへの電圧伝達関数を有する、請求項1
に記載のコンバータ。
2. The converter has the following equation: And having a gain factor of the single-ended input V IN to the differential output V OUT determined by
The following formula [Formula 2] 2. A voltage transfer function of the single-ended input V IN to the predetermined common mode voltage V CM determined by
Converter described in.
【請求項3】 前記予め定められた固定電圧は正の電源
電圧源と負の電源電圧源との半ばにある、請求項1に記
載のコンバータ。
3. The converter of claim 1, wherein the predetermined fixed voltage is midway between a positive power supply voltage source and a negative power supply voltage source.
【請求項4】 入力VINにより差動出力信号VOUT を発
生する方法であって、 (a) その入力端子の一方が前記入力VINに結合され
ており、その他方入力端子が予め定められた固定電圧に
結合されている完全な差動増幅器に前記入力V INを与え
るステップを含み、前記完全な差動増幅器は予め定めら
れた同相電圧V CMを有し、さらに (b) 前記単終端入力と前記完全な差動増幅器の前記
正入力端子との間に第1の抵抗器(「R1 」)を結合す
るステップと、 (c) 前記予め定められた固定電圧と前記完全な差動
増幅器の前記負入力端子との間に第2の抵抗器
(「R2 」)を結合するステップと、 (d) 前記完全な差動増幅器の前記正入力端子と前記
負入力端子との間に第3の抵抗器(「R3 」)を結合す
るステップと、 (e) 前記負入力端子と前記正出力端子との間に第4
の抵抗器(「R4 」)を結合するステップと、 (f) 前記R1 、R2 、R3 、およびR4 の値を、そ
れらの値がR3 /R1≠R4 /R2 に従うものとなるよ
うに設定するステップとを含む、方法。
4. Input VINDifferential output signal VOUTDepart
(A) One of the input terminals has the input VINIs bound to
The other input terminal to a predetermined fixed voltage.
The input V to a fully differential amplifier that is coupled INgive
And the fully differential amplifier has a predetermined
Common-mode voltage V cmAnd (b) the single-ended input and the fully differential amplifier
The first resistor (“R1))
(C) the predetermined fixed voltage and the fully differential
A second resistor between the negative input terminal of the amplifier
("RTwo)), And (d) the positive input terminal of the fully differential amplifier and the
A third resistor (“RThree))
And (e) a fourth terminal between the negative input terminal and the positive output terminal.
Resistor ("RFour)), And (f) the R1, RTwo, RThree, And RFourThe value of
These values are RThree/ R1≠ RFour/ RTwoWill obey
A method comprising:
【請求項5】 (g) 次の式 【数3】 により求められる前記単終端入力VIN対前記差動出力V
OUT の利得率に基づき、かつ、次の式 【数4】 により求められる前記単終端入力VINの前記予め定めら
れた同相電圧VCMへの電圧伝達関数に基づき、前記コン
バータの前記R1 、R2 、R3 、およびR4 の値を調整
するステップをさらに含む、請求項4に記載のコンバー
タ。
5. (g) The following equation (3) The single-ended input V IN to the differential output V
Based on the gain ratio of OUT and the following formula Adjusting the values of the R 1 , R 2 , R 3 and R 4 of the converter based on the voltage transfer function of the single-ended input V IN to the predetermined common mode voltage V CM determined by The converter of claim 4, further comprising:
【請求項6】 前記予め定められた固定電圧は、正の電
源電圧源と負の電源電圧源との半ばにある、請求項4に
記載のコンバータ。
6. The converter of claim 4, wherein the predetermined fixed voltage is midway between a positive power supply voltage source and a negative power supply voltage source.
【請求項7】 VIN=INP−INMであるとき差動入
力電圧VINを正および負の出力端子を介して単終端出力
電圧VOUT に変換するためのコンバータであって、 その入力端子の一方が正入力INPに結合されており、
その他方入力端子が負入力INMに結合されている完全
な差動増幅器を含み、前記完全な差動増幅器は予め定め
られた同相電圧VCMを有し、さらに前記INPと前記完
全な差動増幅器の正入力端子との間に結合される第1の
抵抗器手段(「R1 」)と、 前記INMと前記完全な差動増幅器の前記負入力端子と
の間に結合される第2の抵抗器手段(「R2 」)と、 前記正入力端子と前記出力との間に結合される第3の抵
抗器手段(「R3 」)と、 前記負入力端子と固定電圧との間に結合される第4の抵
抗器手段(「R4 」)とを含み、ここでR3 /R1 ≠R
4 /R2 である、コンバータ。
7. A converter for converting a differential input voltage V IN to a single-ended output voltage V OUT via positive and negative output terminals when V IN = INP-INM, the input terminal One is connected to the positive input INP,
A fully differential amplifier having its other input terminal coupled to the negative input INM, said fully differential amplifier having a predetermined common mode voltage V CM , and further comprising said INP and said fully differential amplifier. A first resistor means ("R 1 ") coupled to the positive input terminal of the second resistor and a second resistor coupled to the negative input terminal of the INM and the fully differential amplifier. Means ("R 2 "), a third resistor means ("R 3 ") coupled between the positive input terminal and the output, and a third resistor means ("R 3 ") coupled between the negative input terminal and a fixed voltage. And a fourth resistor means (“R 4 ”), where R 3 / R 1 ≠ R
A converter that is 4 / R 2 .
【請求項8】 前記コンバータは、次の式 【数5】 により求められる前記差動入力電圧VIN対前記出力電圧
OUT の利得の比率を有しており、前記コンバータはま
た次の式 【数6】 によって求められる前記差動入力VINの前記予め定めら
れた同相電圧VCMへの電圧伝達関数をも有する、請求項
7に記載のコンバータ。
8. The converter has the following equation: The converter also has a ratio of the gain of the differential input voltage V IN to the output voltage V OUT given by: 8. The converter of claim 7 also having a voltage transfer function of the differential input V IN to the predetermined common mode voltage V CM determined by:
JP8256335A 1995-09-29 1996-09-27 Converter for converting single-ended input into differential output signal, method for generating differential output signal dependently on input, and converter for converting differential input voltage into single-ended output voltage Withdrawn JPH09130169A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/536,405 US5614864A (en) 1995-09-29 1995-09-29 Single-ended to differential converter with relaxed common-mode input requirements
US08/536405 1995-09-29

Publications (1)

Publication Number Publication Date
JPH09130169A true JPH09130169A (en) 1997-05-16

Family

ID=24138356

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JP8256335A Withdrawn JPH09130169A (en) 1995-09-29 1996-09-27 Converter for converting single-ended input into differential output signal, method for generating differential output signal dependently on input, and converter for converting differential input voltage into single-ended output voltage

Country Status (4)

Country Link
US (1) US5614864A (en)
EP (1) EP0766381B1 (en)
JP (1) JPH09130169A (en)
DE (1) DE69620330T2 (en)

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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726600A (en) * 1996-01-17 1998-03-10 Hughes Aircraft Company NPN bipolar circuit topology for a tunable transconductance cell and positive current source
US6018272A (en) * 1997-01-02 2000-01-25 Lucent Technologies Inc. Linearization of resistance
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US6008696A (en) * 1998-04-21 1999-12-28 National Semiconductor Corporation Low noise amplifier with actively terminated input
US6329876B1 (en) * 1999-01-04 2001-12-11 Tripath Technology, Inc. Noise reduction scheme for operational amplifiers
US6133787A (en) * 1999-05-04 2000-10-17 Physio-Control Manufacturing Corporation Method and apparatus for controlling the common mode impedance misbalance of an isolated single-ended circuit
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US6437720B1 (en) 2001-02-16 2002-08-20 Conexant Systems, Inc. Code independent charge transfer scheme for switched-capacitor digital-to-analog converter
US6566961B2 (en) 2001-03-30 2003-05-20 Institute Of Microelectronics Wide-band single-ended to differential converter in CMOS technology
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US6946828B1 (en) * 2003-05-20 2005-09-20 Ami Semiconductor, Inc. Bi-directional current measurement circuit that uses a transconductance amplifier to generate a copy current
US6975261B1 (en) * 2004-07-28 2005-12-13 Intersil America's Inc. High accuracy digital to analog converter using parallel P and N type resistor ladders
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US8138833B1 (en) * 2010-10-08 2012-03-20 Texas Instruments Incorporated Common-mode feedback amplifier
US8319466B2 (en) 2011-02-21 2012-11-27 Rockwell Automation Technologies, Inc. Modular line-to-ground fault identification
US8633765B2 (en) * 2011-05-17 2014-01-21 Infineon Technologies Ag Input common mode circuit for a fully differential amplifier
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US9806703B2 (en) * 2015-09-03 2017-10-31 Mediatek Inc. Single-ended to differential conversion circuit and signal processing module
US10110223B2 (en) * 2016-07-06 2018-10-23 Via Alliance Semiconductor Co., Ltd. Single ended-to-differential converter
US10312868B2 (en) * 2017-04-20 2019-06-04 Aura Semiconductor Pvt. Ltd Correcting for non-linearity in an amplifier providing a differential output

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4037170A (en) * 1976-04-05 1977-07-19 Stromberg-Carlson Corporation Difference amplifier having extended common mode range
GB8809206D0 (en) * 1988-04-19 1988-05-25 Otec Electronics Ltd Amplifier circuit
EP0500645A1 (en) * 1989-11-13 1992-09-02 British Technology Group Ltd Transducer signal conditioning circuit

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* Cited by examiner, † Cited by third party
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Also Published As

Publication number Publication date
DE69620330D1 (en) 2002-05-08
DE69620330T2 (en) 2002-11-14
EP0766381A1 (en) 1997-04-02
US5614864A (en) 1997-03-25
EP0766381B1 (en) 2002-04-03

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