JPH09134916A - Formation of element isolation insulating film - Google Patents
Formation of element isolation insulating filmInfo
- Publication number
- JPH09134916A JPH09134916A JP29290095A JP29290095A JPH09134916A JP H09134916 A JPH09134916 A JP H09134916A JP 29290095 A JP29290095 A JP 29290095A JP 29290095 A JP29290095 A JP 29290095A JP H09134916 A JPH09134916 A JP H09134916A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- film
- exposed
- main surface
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 105
- 230000015572 biosynthetic process Effects 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 abstract description 20
- 238000007254 oxidation reaction Methods 0.000 abstract description 20
- 230000007547 defect Effects 0.000 abstract description 17
- 239000013078 crystal Substances 0.000 abstract description 16
- 238000000926 separation method Methods 0.000 description 45
- 241000293849 Cordylanthus Species 0.000 description 8
- 241000894007 species Species 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 241001663154 Electron Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体基板に素子分
離絶縁膜を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation insulating film on a semiconductor substrate.
【0002】[0002]
【従来の技術】従来用いられてきた素子分離としては、
まずLOCOS(Local Oxidation ofSilicon)分離があ
げられる。LOCOS分離は図4に示すように、半導体
基板1上に形成した酸化膜2及び窒化膜3から成る2層
構造をパターニングした後に、半導体基板を選択酸化す
ることによって形成される。2. Description of the Related Art As the element isolation conventionally used,
First, there is LOCOS (Local Oxidation of Silicon) separation. As shown in FIG. 4, the LOCOS isolation is formed by patterning a two-layer structure formed of an oxide film 2 and a nitride film 3 formed on a semiconductor substrate 1 and then selectively oxidizing the semiconductor substrate.
【0003】前記LOCOS分離に対して、パンチスル
ー防止のために素子分離長を長くすることを目的として
提案されたのが、図5に示したRECESSED LO
COS分離(例えば、特開平02−119137号に記
載されている。)である。RECESSED LOCO
S分離は、LOCOS分離と同様に半導体基板1上に形
成した酸化膜2及び窒化膜3から成る2層構造をパター
ニングし、続けて半導体基板をエッチングして分離溝6
を形成した後で、半導体基板を選択酸化することによっ
て形成される。RECESSED LOCOS分離は、
LOCOS分離と比べて、半導体基板表面より下の素子
分離膜厚が厚いために実効的な素子分離長が長くなる。In contrast to the LOCOS isolation, a RECESSED LO shown in FIG. 5 was proposed for the purpose of increasing the element isolation length in order to prevent punch-through.
COS separation (for example, described in JP-A-02-119137). RECESSED LOCO
In the S separation, similar to the LOCOS separation, the two-layer structure formed of the oxide film 2 and the nitride film 3 formed on the semiconductor substrate 1 is patterned, and then the semiconductor substrate is etched to form the separation groove 6
Is formed by selectively oxidizing the semiconductor substrate after forming. RECESSED LOCOS separation
Compared with LOCOS isolation, the effective element isolation length becomes longer because the element isolation film thickness below the semiconductor substrate surface is thicker.
【0004】しかし、LOCOS分離及びRECESS
ED LOCOS分離では、選択酸化において、酸化膜
2の表面が露出している側面から酸化種が侵入・拡散し
て、素子領域の端部の半導体基板1の表面を酸化するこ
とによって、酸化膜が素子領域内に食い込み(この酸化
膜はバーズビークと呼ばれる)、素子幅を減少させるた
め、セルの微細化が困難であった。However, LOCOS separation and RECESS
In the ED LOCOS separation, in selective oxidation, an oxidizing species penetrates and diffuses from the side surface where the surface of the oxide film 2 is exposed, and oxidizes the surface of the semiconductor substrate 1 at the end of the element region, so that the oxide film is formed. It is difficult to miniaturize the cell because it bites into the element region (this oxide film is called bird's beak) and reduces the element width.
【0005】そこで、微細化のためにバーズビーク長を
短く抑えることを目的として提案されたのがOSELL
O II 分離(例えば、IEEE Trans.Elec
tron Devices,vol.35,No.7,
pp893−898,JULY 1988に記載されて
いる。)である。OSELLO II 分離は、図6に示す
ように、半導体基板1上のパターニングされた第一酸化
膜2及び第一窒化膜3から成る2層構造に対して、第二
窒化膜8及び第二酸化膜4から成るサイドウォール部を
形成後、前記サイドウォール部をマスクとして半導体基
板をエッチングして分離溝6を形成し第二酸化膜を除去
した後で、半導体基板を選択酸化することによって形成
される。OSELLO II 分離では、素子分離領域の両
端の半導体基板上に形成された窒化膜サイドウォール部
9が、選択酸化における半導体基板表面への酸化種の到
達を抑制して、バーズビークの成長を抑えるため、セル
の微細化に対して有効である。Therefore, OSELL was proposed for the purpose of keeping the bird's beak length short for miniaturization.
O II separation (for example, IEEE Trans. Elec
tron Devices, vol. 35, No. 7,
pp 893-898, JULY 1988. ). As shown in FIG. 6, the OSELLO II isolation is performed by using the second nitride film 8 and the second dioxide film 4 for the two-layer structure including the patterned first oxide film 2 and the first nitride film 3 on the semiconductor substrate 1. After the formation of the side wall portion made of, the side wall portion is used as a mask to etch the semiconductor substrate to form the separation groove 6 to remove the second dioxide film, and then the semiconductor substrate is selectively oxidized. In the OSELLO II isolation, the nitride film sidewall portions 9 formed on the semiconductor substrate at both ends of the element isolation region suppress the arrival of oxidizing species on the surface of the semiconductor substrate during selective oxidation, and suppress the growth of bird's beaks. It is effective for miniaturization of cells.
【0006】[0006]
【発明が解決しようとする課題】従来用いられてきた素
子分離として、LOCOS分離、RECESSED L
OCOS分離、OSELLO II 分離がある。LOCO
S分離と比べて、RECESSED LOCOS分離、
及びOSELLO II 分離は、半導体基板表面より下の
素子分離膜厚が厚いために実効的な素子分離長が長くな
り、パンチスルー防止に対して有効である。LOCOS isolation, RECESSED L is used as element isolation that has been conventionally used.
There are OCOS separation and OSELLO II separation. LOCO
Compared with S separation, RECESSED LOCOS separation,
And OSELLO II isolation are effective in preventing punch-through because the element isolation film thickness below the surface of the semiconductor substrate is thick and the effective element isolation length becomes long.
【0007】しかし、OSELLO II 分離では、素子
分離領域の両端の半導体基板上に形成された窒化膜サイ
ドウォール部9が、選択酸化による素子領域の端部の体
積膨張を抑えるために、素子領域の端部の半導体基板に
ストレスが生じる。このストレスによって、半導体基板
中に結晶欠陥が発生し、これを再結合中心として接合リ
ーク電流が流れるという問題が生じる。However, in the OSELLO II isolation, the nitride film sidewall portions 9 formed on the semiconductor substrate at both ends of the element isolation region suppress the volume expansion of the edge of the element region due to the selective oxidation, so that Stress is generated on the semiconductor substrate at the edge. This stress causes a crystal defect in the semiconductor substrate, which causes a problem that a junction leak current flows with the crystal defect as a recombination center.
【0008】一方、RECESSED LOCOS分離
では、素子分離領域の両端の半導体基板を窒化膜で直接
抑える構造になっていないため、前述したOSELLO
II分離と同じストレスの発生とこれに伴う接合リーク
電流の増大は起きない。しかし、半導体基板表面をエッ
チングして分離溝を形成する際に用いられる高エネルギ
ーのプラズマによって、分離溝の側面及び底面の半導体
基板中に結晶欠陥が発生する。また、選択酸化時に、分
離溝の側面、及び底面が交差する素子分離領域の端部近
傍には、側面及び底面からの酸化膜の成長によって、L
OCOS分離と比べて大きなストレスが生じ、半導体基
板中により多くの結晶欠陥が発生する。従って、REC
ESSED LOCOS分離では、分離溝の周辺近傍の
半導体基板中に生じる結晶欠陥を再結合中心として接合
リーク電流が流れるという問題が生じる。On the other hand, the RECESSED LOCOS isolation does not have a structure in which the semiconductor films at both ends of the element isolation region are directly suppressed by the nitride film.
The same stress as in II separation and the accompanying increase in junction leakage current do not occur. However, crystal defects occur in the semiconductor substrate on the side surface and the bottom surface of the separation groove due to the high-energy plasma used when the surface of the semiconductor substrate is etched to form the separation groove. Further, during the selective oxidation, the oxide film grows from the side surface and the bottom surface in the vicinity of the end portion of the element isolation region where the side surface and the bottom surface of the isolation groove intersect with each other.
Larger stress occurs as compared with OCOS separation, and more crystal defects occur in the semiconductor substrate. Therefore, REC
In the ESSED LOCOS isolation, there arises a problem that a junction leak current flows with a crystal defect occurring in the semiconductor substrate near the periphery of the isolation groove as a recombination center.
【0009】前述したOSELLO II 分離において
も、半導体基板表面をエッチングして分離溝を形成する
ため、RECESSED LOCOS分離と同様に、分
離溝の周辺近傍の半導体基板中に結晶欠陥が発生し、こ
れに起因する接合リーク電流が流れることが予想され
る。しかし、OSELLO II 分離では、分離溝の側面
から素子領域の端部までの間の半導体基板を選択酸化す
るために、分離溝の周辺近傍の半導体基板中に生じた結
晶欠陥は、素子分離酸化膜中に取り込まれる。従って、
OSELLO II 分離で生じる接合リーク電流は、選択
酸化による体積膨張を窒化膜で抑えることによって生じ
た結晶欠陥にのみ起因し、RECESSEDLOCOS
分離において、分離溝の周辺近傍の半導体基板中に生じ
る結晶欠陥には起因しない。Also in the above-mentioned OSELLO II separation, since the surface of the semiconductor substrate is etched to form the separation groove, crystal defects are generated in the semiconductor substrate in the vicinity of the periphery of the separation groove, as in the RECESSED LOCOS separation. It is expected that the resulting junction leakage current will flow. However, in the OSELLO II isolation, since the semiconductor substrate between the side surface of the isolation trench and the end of the element region is selectively oxidized, the crystal defects generated in the semiconductor substrate in the vicinity of the isolation trench are separated by the element isolation oxide film. It is taken in. Therefore,
The junction leakage current generated by the OSELLO II separation is caused only by the crystal defects generated by suppressing the volume expansion due to the selective oxidation with the nitride film, and the RECESSEDLOCOS
In the separation, it is not caused by a crystal defect generated in the semiconductor substrate near the periphery of the separation groove.
【0010】従って本発明では、選択酸化時に素子分離
領域の端部に発生する結晶欠陥をRECESSED L
OCOS分離及びOSELLO II 分離よりも抑えて接
合リーク電流を低減し、LOCOS分離よりも素子分離
長を長くしてパンチスルーに対する耐性を上げた素子分
離を形成することを課題とする。Therefore, in the present invention, the crystal defects generated at the end of the element isolation region during the selective oxidation are reduced by the RECESSED L method.
It is an object of the present invention to form an element isolation that suppresses the junction leakage current by suppressing it than the OCOS isolation and the OSELLO II isolation, and makes the element isolation length longer than the LOCOS isolation to improve punch-through resistance.
【0011】[0011]
【課題を解決するための手段】本発明によれば、半導体
基板に素子分離絶縁膜を形成する方法において、半導体
基板の主面に第一酸化膜及び窒化膜を順次形成するステ
ップと、前記半導体基板の主面の一部が主面露出部とし
て露出されるように、前記第一酸化膜及び前記窒化膜に
開口を形成するステップと、前記主面露出部の中央部が
中央露出部として露出した状態に保たれるように、該開
口の側面を決めている前記第一酸化膜及び前記窒化膜の
側壁と、前記主面露出部の前記中央部以外の部分とを覆
う、第二酸化膜から成るサイドウォール部を形成するス
テップと、前記サイドウォール部をマスクとして前記中
央露出部をエッチングして前記半導体基板に分離溝を形
成するステップと、前記窒化膜及び前記サイドウォール
部をマスクとして前記分離溝の近傍の前記半導体基板を
選択酸化し、前記素子分離絶縁膜を形成するステップと
を含むことを特徴とする素子分離絶縁膜形成方法が得ら
れる。According to the present invention, in a method of forming an element isolation insulating film on a semiconductor substrate, a step of sequentially forming a first oxide film and a nitride film on the main surface of the semiconductor substrate, Forming an opening in the first oxide film and the nitride film so that a part of the main surface of the substrate is exposed as a main surface exposed portion; and exposing the central portion of the main surface exposed portion as a central exposed portion. A second oxide film covering the side walls of the first oxide film and the nitride film that define the side surface of the opening and the portion of the exposed main surface other than the central portion so as to be kept in the above state. Forming a sidewall portion, forming the isolation trench in the semiconductor substrate by etching the central exposed portion using the sidewall portion as a mask, and using the nitride film and the sidewall portion as a mask Serial selecting oxidizing said semiconductor substrate in the vicinity of the isolation trench, the isolation insulating film forming method characterized by including the steps of forming the device isolation insulating film is obtained.
【0012】更に本発明によれば、半導体基板に素子分
離絶縁膜を形成する方法において、半導体基板の主面に
第一酸化膜及び窒化膜を順次形成するステップと、前記
半導体基板の主面の一部が主面露出部として露出される
ように、前記第一酸化膜及び前記窒化膜に開口を形成す
るステップと、前記主面露出部の中央部が中央露出部と
して露出した状態に保たれるように、該開口の側面を決
めている前記第一酸化膜及び前記窒化膜の側壁と、前記
主面露出部の前記中央部以外の部分とを覆う、露出面が
突出曲面からなる、第二酸化膜から成るサイドウォール
部を形成するステップと、前記サイドウォール部をマス
クとして前記中央露出部をエッチングして前記半導体基
板に分離溝を形成するステップと、前記窒化膜及び前記
サイドウォール部をマスクとして前記分離溝の近傍の前
記半導体基板を選択酸化し、前記素子分離絶縁膜を形成
するステップとを含むことを特徴とする素子分離絶縁膜
形成方法が得られる。Further, according to the present invention, in a method of forming an element isolation insulating film on a semiconductor substrate, a step of sequentially forming a first oxide film and a nitride film on the main surface of the semiconductor substrate, and a step of forming the main surface of the semiconductor substrate. Forming an opening in the first oxide film and the nitride film so that a part of the main surface exposed portion is exposed, and a central portion of the main surface exposed portion is kept exposed as a central exposed portion So as to cover the sidewalls of the first oxide film and the nitride film that define the side surface of the opening and a portion of the main surface exposed portion other than the central portion, the exposed surface has a protruding curved surface. Forming a sidewall portion formed of a dioxide film, etching the central exposed portion by using the sidewall portion as a mask to form an isolation groove in the semiconductor substrate, the nitride film and the sidewall portion The selected oxidizing said semiconductor substrate in the vicinity of the isolation trenches as a mask, the element isolation insulating film forming method characterized by including the steps of forming the device isolation insulating film is obtained.
【0013】また本発明によれば、半導体基板に素子分
離絶縁膜を形成する方法において、半導体基板上のパタ
ーニングされた第一酸化膜及び窒化膜から成る2層構造
に対して、第二酸化膜から成るサイドウォール部を形成
後、前記サイドウォール部をマスクとして半導体基板を
エッチングして分離溝を形成した後に、半導体基板を選
択酸化することによって素子分離絶縁膜を形成すること
を特徴とする素子分離絶縁膜形成方法が得られる。Further, according to the present invention, in a method for forming an element isolation insulating film on a semiconductor substrate, a two-layer structure consisting of a patterned first oxide film and a patterned nitride film on the semiconductor substrate is used, and After the formation of the side wall portion, the side wall portion is used as a mask to etch the semiconductor substrate to form an isolation groove, and then the semiconductor substrate is selectively oxidized to form an element isolation insulating film. An insulating film forming method can be obtained.
【0014】[0014]
【作用】RECESSED LOCOS分離の場合、分
離溝の周辺近傍の半導体基板中に結晶欠陥が発生し、こ
れに起因する接合リーク電流が流れる。一方、本発明の
場合、酸化膜サイドウォール部をマスクにして分離溝を
形成し、分離溝の端部が素子分離領域の端部よりも内側
にあるため、OSELLO II 分離と同様に、分離溝の
周辺近傍の半導体基板中に生じた結晶欠陥は、選択酸化
の際に素子分離酸化膜中に取り込まれて、接合リーク電
流が抑えられることになる。In the case of the RECESSED LOCOS isolation, a crystal defect occurs in the semiconductor substrate in the vicinity of the periphery of the isolation trench, and a junction leak current resulting from this occurs. On the other hand, in the case of the present invention, the isolation trench is formed using the oxide film sidewall portion as a mask, and the edge of the isolation trench is inside the edge of the element isolation region. Therefore, similar to the OSELLO II isolation, the isolation trench is formed. The crystal defects generated in the semiconductor substrate near the periphery of the are taken into the element isolation oxide film during the selective oxidation, and the junction leak current is suppressed.
【0015】さらに、本発明では、素子分離領域の両端
の半導体基板上に形成するサイドウォール部に、OSE
LLO II 分離のように窒化膜ではなく、酸化膜を用い
るために、選択酸化時にサイドウォール部下の半導体基
板の酸化に伴う体積膨張を抑える効果が小さい。このた
め、選択酸化による体積膨張を抑えることによって生じ
る結晶欠陥に起因する接合リーク電流は抑えられること
になる。Further, according to the present invention, the OSE is formed on the sidewall portion formed on the semiconductor substrate at both ends of the element isolation region.
Since an oxide film is used instead of a nitride film as in the case of LLO II isolation, the effect of suppressing the volume expansion due to the oxidation of the semiconductor substrate under the sidewall portion during the selective oxidation is small. Therefore, the junction leak current caused by the crystal defect caused by suppressing the volume expansion due to the selective oxidation can be suppressed.
【0016】また、本発明では素子分離領域の両端の半
導体基板上に形成する酸化膜サイドウォール部の存在に
よって選択酸化時の酸化種の拡散が抑えられるために、
RECESSED LOCOS分離と比べてバーズビー
ク長を短くできる。ただし、酸化種の拡散を抑制する能
力は、シリコン酸化膜よりシリコン窒化膜の方が高いの
で、酸化膜サイドウォール部を用いる本発明では、窒化
膜サイドウォール部を用いるOSELLO II 分離ほど
に、バーズビーク長を抑制することはできない。Further, in the present invention, the presence of the oxide film side wall portions formed on the semiconductor substrate at both ends of the element isolation region suppresses the diffusion of the oxidizing species during the selective oxidation.
Compared with RECESSED LOCOS separation, bird's beak length can be shortened. However, since the silicon nitride film has a higher ability to suppress the diffusion of the oxidizing species than the silicon oxide film, in the present invention using the oxide film side wall portion, the bird's beak is similar to the OSELLO II isolation using the nitride film side wall portion. You cannot control the length.
【0017】[0017]
【発明の実施の形態】次に本発明の実施例について図面
を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.
【0018】図1(a)〜(d)は、本発明の一実施例
の製造工程を示す断面図である。まず、半導体基板1上
のパターニングされた、膜厚が例えば100A程度であ
る第一酸化膜2、膜厚が例えば1200A程度である窒
化膜3から成る2層構造に対して、膜厚が例えば150
0A程度である第二酸化膜4を形成する(図1(a),
(b))。ここで第二酸化膜には、例えば、化学気相成
長法(以後、CVD法と称する)によって、400℃程
度の低温で形成した酸化膜を用いる。次に、異方性エッ
チングによって第二酸化膜4から成る酸化膜サイドウォ
ール部5を形成し、これをマスクとして半導体基板1を
エッチングして、溝の深さが例えば600A程度である
分離溝6を形成する(図1(c))。この後、半導体基
板1を選択酸化して、膜厚が例えば4000A程度であ
る素子分離絶縁膜7を形成する(図1(d))。ここ
で、酸化膜サイドウォール部5は、窒化膜3を除去した
後も凹凸として残り、半導体基板表面の段差を増大させ
る原因となる。半導体基板表面の段差は、以後の目合わ
せ工程におけるフォーカスマージンの低減、金属配線の
段切れ等の原因となるため、できる限りこれを小さくす
ることが望まれる。1 (a) to 1 (d) are sectional views showing a manufacturing process of an embodiment of the present invention. First, for a two-layer structure consisting of a patterned first oxide film 2 having a film thickness of, for example, about 100 A and a nitride film 3 having a film thickness of, for example, about 1200 A on the semiconductor substrate 1, the film thickness is, for example, 150.
A second oxide film 4 having a thickness of about 0 A is formed (FIG. 1 (a),
(B)). Here, as the second dioxide film, for example, an oxide film formed at a low temperature of about 400 ° C. by a chemical vapor deposition method (hereinafter referred to as a CVD method) is used. Next, the oxide film sidewall portion 5 made of the second dioxide film 4 is formed by anisotropic etching, and the semiconductor substrate 1 is etched using this as a mask to form the isolation groove 6 having a groove depth of, for example, about 600A. Formed (FIG. 1 (c)). Thereafter, the semiconductor substrate 1 is selectively oxidized to form an element isolation insulating film 7 having a film thickness of about 4000 A (FIG. 1D). Here, the oxide film side wall portion 5 remains as unevenness even after the nitride film 3 is removed, which causes a step difference on the surface of the semiconductor substrate. Since the step on the surface of the semiconductor substrate causes a reduction in the focus margin and a disconnection of the metal wiring in the subsequent aligning step, it is desired to reduce it as much as possible.
【0019】まとめると、この実施例では、半導体基板
1の主面に第一酸化膜2及び窒化膜3を順次形成し、半
導体基板1の主面の一部が主面露出部として露出される
ように、第一酸化膜2及び窒化膜3に開口を形成する
(図1(a))。In summary, in this embodiment, the first oxide film 2 and the nitride film 3 are sequentially formed on the main surface of the semiconductor substrate 1, and a part of the main surface of the semiconductor substrate 1 is exposed as a main surface exposed portion. Thus, openings are formed in the first oxide film 2 and the nitride film 3 (FIG. 1A).
【0020】次に、主面露出部の中央部が中央露出部と
して露出した状態に保たれるように、開口の側面を決め
ている第一酸化膜2及び窒化膜3の側壁と、前記主面露
出部の前記中央部以外の部分とを覆う、露出面が突出曲
面からなる、第二酸化膜4から成る酸化膜サイドウォー
ル部5を形成する(図1(b)及び(c))。Next, the sidewalls of the first oxide film 2 and the nitride film 3 which define the side surfaces of the opening so that the central portion of the exposed portion of the main surface is kept exposed as the exposed portion of the central surface, An oxide film sidewall portion 5 made of the second dioxide film 4 is formed so that the exposed surface is a protruding curved surface and covers the surface exposed portion other than the central portion (FIGS. 1B and 1C).
【0021】次に、酸化膜サイドウォール部5をマスク
として前記中央露出部をエッチングして半導体基板1に
分離溝6を形成する(図1(c))。Next, using the oxide film sidewall portion 5 as a mask, the central exposed portion is etched to form a separation groove 6 in the semiconductor substrate 1 (FIG. 1C).
【0022】そして窒化膜3及び酸化膜サイドウォール
部5をマスクとして分離溝6の近傍の半導体基板1を選
択酸化し、素子分離絶縁膜7を形成する。Then, using the nitride film 3 and the oxide film sidewall portion 5 as a mask, the semiconductor substrate 1 in the vicinity of the isolation trench 6 is selectively oxidized to form an element isolation insulating film 7.
【0023】ところで、通常の半導体デバイスプロセス
では、素子分離領域の形成後、素子領域表面の第一酸化
膜2を弗酸等を用いて除去し、更に素子領域表面に犠牲
酸化膜と呼ばれる熱酸化膜を形成し、続いてこれを弗酸
等を用いて除去する事により、基板表面に存在した欠
陥、金属汚染等を除去することを行う。その後、素子領
域表面に熱酸化法等によりゲート酸化膜を形成する。必
要に応じて犠牲酸化膜の形成と除去を複数回行うことも
ある。そのため、本発明の製造方法で残った酸化膜サイ
ドウォール部は、ゲート酸化膜の形成に先立って、少な
くとも2回の酸化膜除去工程を経るので、その形状はな
だらかなものとなり、その段差の影響はほとんど無視で
きる。By the way, in a normal semiconductor device process, after the formation of the element isolation region, the first oxide film 2 on the surface of the element region is removed by using hydrofluoric acid or the like, and the surface of the element region is thermally oxidized called a sacrificial oxide film. By forming a film and then removing it with hydrofluoric acid or the like, defects and metal contamination existing on the substrate surface are removed. After that, a gate oxide film is formed on the surface of the element region by a thermal oxidation method or the like. If necessary, the sacrificial oxide film may be formed and removed a plurality of times. Therefore, the oxide film sidewall portion remaining by the manufacturing method of the present invention undergoes at least two oxide film removing steps prior to the formation of the gate oxide film, so that its shape becomes gentle and the influence of the step Can be almost ignored.
【0024】本発明では、分離溝を形成して選択酸化を
行なうため、LOCOS分離よりも、半導体基板表面よ
り下の素子分離膜厚が厚い。このため、実効的な素子分
離長が長くなり、パンチスルーに対する耐圧が高い。こ
こで、LOCOS分離、RECESSED LOCOS
分離、OSELLO II 分離、及び本発明に対する、パ
ンチスルー耐性を図2に示す。横軸は素子分離幅、縦軸
はパンチスルー耐圧である。図2から、LOCOS分離
が0.55μmまで分離可能であるのに対して、OSE
LLO II 分離、及び本発明は0.4μmまで分離可能
であり、RECESSED LOCOS分離は0.35
μmで分離可能であることがわかる。従って、本発明の
素子分離が必要となる素子分離幅は0.55μm以下で
ある。In the present invention, since the isolation trench is formed and the selective oxidation is performed, the element isolation film thickness below the semiconductor substrate surface is thicker than that in the LOCOS isolation. Therefore, the effective element isolation length becomes long, and the breakdown voltage against punch through is high. Where LOCOS separation, RECESSED LOCOS
Punch-through resistance for separation, OSELLO II separation, and the present invention is shown in FIG. The horizontal axis represents the element isolation width, and the vertical axis represents the punch-through breakdown voltage. From FIG. 2, LOCOS separation is possible up to 0.55 μm, while OSE
The LLO II separation and the present invention can be separated up to 0.4 μm, and the RECESSED LOCOS separation is 0.35.
It can be seen that separation is possible in μm. Therefore, the element isolation width required for element isolation of the present invention is 0.55 μm or less.
【0025】次に本発明では、サイドウォール部をマス
クにして分離溝を形成することにより、分離溝の端部が
素子分離領域の端部よりも内側にあるため、分離溝の周
辺近傍の半導体基板中に生じた結晶欠陥は素子分離酸化
膜中に取り込まれるために、RECESSED LOC
OS分離よりも接合リーク電流が低減される。また本発
明では、サイドウォール部に酸化膜を用いるために、窒
化膜を用いるOSELLO II 分離と比べて、選択酸化
時にサイドウォール部下の半導体基板の酸化に伴う体積
膨張を抑えることによって生じるストレスが小さいため
に、接合リーク電流は低減される。ここで、LOCOS
分離、RECESSED LOCOS分離、OSELL
O II 分離、及び本発明に対する、接合リーク電流特性
を図3に示す。横軸は逆バイアス電圧、縦軸は接合リー
ク電流である。図3から、本発明の接合リーク電流は、
RECESSED LOCOS分離、及びOSELLO
II 分離よりは低減されていて、LOCOS分離と同等
のレベルであることがわかる。Next, in the present invention, the isolation groove is formed by using the sidewall portion as a mask, and the edge of the isolation groove is inside the edge of the element isolation region. Therefore, the semiconductor near the edge of the isolation groove is formed. Since the crystal defects generated in the substrate are taken into the element isolation oxide film, the RECESSED LOC
Junction leakage current is reduced as compared with OS isolation. Further, in the present invention, since the oxide film is used for the sidewall portion, the stress caused by suppressing the volume expansion due to the oxidation of the semiconductor substrate under the sidewall portion during the selective oxidation is smaller than that of the OSELLO II separation using the nitride film. Therefore, the junction leak current is reduced. Where LOCOS
Separation, RECESSED LOCOS separation, OSELL
The junction leakage current characteristics for O II separation and the present invention are shown in FIG. The horizontal axis represents the reverse bias voltage, and the vertical axis represents the junction leakage current. From FIG. 3, the junction leakage current of the present invention is
RECESSED LOCOS separation and OSELLO
It can be seen that the level is lower than that of II separation, and that the level is equivalent to LOCOS separation.
【0026】上述の実施例では、酸化膜サイドウォール
部5の高さを、窒化膜3の厚さと同程度にしている。し
かし、酸化膜サイドウォール部5の高さは、窒化膜3の
厚さによって制限されるものではない。In the above-described embodiment, the height of the oxide film side wall portion 5 is set to be approximately the same as the thickness of the nitride film 3. However, the height of the oxide film sidewall portion 5 is not limited by the thickness of the nitride film 3.
【0027】その高さを低くすれば、素子分離膜形成
後、素子領域表面の酸化膜除去工程を経た後に残る酸化
膜サイドウォール部の高さも低くなるため、上述の実施
例に比べて、更に段差が小さく、微細な素子分離構造を
得ることが可能となる。しかし、酸化膜サイドウォール
部の高さを低くすると、選択酸化において酸化種が酸化
膜サイドウォール部の下の半導体基板表面にまで拡散す
ることを抑制する効果が小さいため、バーズビークが生
じ易くなる。このため、酸化膜サイドウォール部の形成
に、例えば400℃程度の低温で形成した酸化膜と比べ
て、密度が高い、例えば800℃程度の高温雰囲気で形
成したCVD酸化膜を用いると、選択酸化時に酸化膜サ
イドウォール部下に酸化種が拡散してバーズビークが生
じるのを抑制する効果が高く、バーズビークを抑えるこ
とができるため、酸化膜サイドウォール部を低く形成す
ることが可能である。If the height is lowered, the height of the oxide film side wall portion remaining after the oxide film removing process on the surface of the element region after forming the device isolation film also becomes lower. It is possible to obtain a fine element isolation structure with a small step. However, when the height of the oxide film side wall portion is reduced, the effect of suppressing the diffusion of the oxidizing species to the surface of the semiconductor substrate below the oxide film side wall portion is small in the selective oxidation, so that bird's beak is likely to occur. For this reason, if a CVD oxide film formed in a high-temperature atmosphere of, for example, about 800 ° C., which has a higher density than that of an oxide film formed at a low temperature of about 400 ° C., is used for forming the oxide film sidewall portion, selective oxidation is performed. At times, it is highly effective in suppressing the generation of bird's beak due to the diffusion of oxidizing species under the oxide film side wall portion, and since bird's beak can be suppressed, it is possible to form the oxide film side wall portion low.
【0028】[0028]
【発明の効果】以上説明してきたように本発明によれ
ば、分離溝を形成して選択酸化を行なうことによって、
実効的な素子分離長を長くして、LOCOS分離と比べ
てパンチスルーに対する耐性が高い。ただし、RECE
SSED LOCOS分離、及びOSELLO II 分離
とはパンチスルーに対する耐性は同程度である。As described above, according to the present invention, by forming the isolation trench and performing the selective oxidation,
By increasing the effective element isolation length, the resistance to punch through is higher than that in LOCOS isolation. However, RECE
The resistance to punch-through is similar to that of SSED LOCOS separation and OSELLO II separation.
【0029】さらに本発明によれば、サイドウォール部
をマスクにして分離溝を形成すること、及びサイドウォ
ール部に酸化膜を用いることによって、素子分離領域の
端部の半導体基板中の結晶欠陥の発生を抑制して、RE
CESSED LOCOS分離、及びOSELLO II
分離と比べて、接合リーク電流を低減できた。Further, according to the present invention, by forming the isolation groove using the sidewall portion as a mask and using the oxide film in the sidewall portion, crystal defects in the semiconductor substrate at the end portion of the element isolation region are eliminated. Suppress the occurrence, RE
CESSED LOCOS separation and OSELLO II
The junction leakage current could be reduced as compared with the separation.
【図1】本発明の一実施例を説明するための断面図であ
る。FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.
【図2】図1の実施例の効果を説明するための図であ
る。FIG. 2 is a diagram for explaining an effect of the embodiment of FIG.
【図3】図1の実施例の効果を説明するための図であ
る。FIG. 3 is a diagram for explaining an effect of the embodiment of FIG.
【図4】従来例を説明するための断面図である。FIG. 4 is a cross-sectional view for explaining a conventional example.
【図5】もう一つの従来例を説明するための断面図であ
る。FIG. 5 is a cross-sectional view for explaining another conventional example.
【図6】更に別の従来例を説明するための断面図であ
る。FIG. 6 is a cross-sectional view for explaining still another conventional example.
1 半導体基板 2 第一酸化膜 3 窒化膜 4 第二酸化膜 5 酸化膜サイドウォール部 6 分離溝 7 素子分離絶縁膜 1 Semiconductor Substrate 2 First Oxide Film 3 Nitride Film 4 Second Dioxide Film 5 Oxide Film Sidewall 6 Isolation Groove 7 Element Isolation Insulation Film
Claims (3)
方法において、 半導体基板の主面に第一酸化膜及び窒化膜を順次形成す
るステップと、 前記半導体基板の主面の一部が主面露出部として露出さ
れるように、前記第一酸化膜及び前記窒化膜に開口を形
成するステップと、 前記主面露出部の中央部が中央露出部として露出した状
態に保たれるように、該開口の側面を決めている前記第
一酸化膜及び前記窒化膜の側壁と、前記主面露出部の前
記中央部以外の部分とを覆う、第二酸化膜から成るサイ
ドウォール部材を形成するステップと、 前記サイドウォール部をマスクとして前記中央露出部を
エッチングして前記半導体基板に分離溝を形成するステ
ップと、 前記窒化膜及び前記サイドウォール部をマスクとして前
記分離溝の近傍の前記半導体基板を選択酸化し、前記素
子分離絶縁膜を形成するステップとを含むことを特徴と
する素子分離絶縁膜形成方法。1. A method of forming an element isolation insulating film on a semiconductor substrate, the step of sequentially forming a first oxide film and a nitride film on the main surface of the semiconductor substrate, and a part of the main surface of the semiconductor substrate is the main surface. Forming an opening in the first oxide film and the nitride film so as to be exposed as an exposed portion; and so as to keep the central portion of the main surface exposed portion exposed as a central exposed portion, Forming a sidewall member made of a second dioxide film, which covers sidewalls of the first oxide film and the nitride film that define the side surface of the opening and a portion other than the central portion of the main surface exposed portion, Forming an isolation trench in the semiconductor substrate by etching the central exposed portion using the sidewall portion as a mask; and using the nitride film and the sidewall portion as a mask, the semiconductor near the isolation trench. Selectively oxidized substrate, the element isolation insulating film forming method characterized by including the steps of forming the element isolation insulating film.
方法において、 半導体基板の主面に第一酸化膜及び窒化膜を順次形成す
るステップと、 前記半導体基板の主面の一部が主面露出部として露出さ
れるように、前記第一酸化膜及び前記窒化膜に開口を形
成するステップと、 前記主面露出部の中央部が中央露出部として露出した状
態に保たれるように、該開口の側面を決めている前記第
一酸化膜及び前記窒化膜の側壁と、前記主面露出部の前
記中央部以外の部分とを覆う、露出面が突出曲面からな
る、第二酸化膜から成るサイドウォール部を形成するス
テップと、 前記サイドウォール部をマスクとして前記中央露出部を
エッチングして前記半導体基板に分離溝を形成するステ
ップと、 前記窒化膜及び前記サイドウォール部をマスクとして前
記分離溝の近傍の前記半導体基板を選択酸化し、前記素
子分離絶縁膜を形成するステップとを含むことを特徴と
する素子分離絶縁膜形成方法。2. A method of forming an element isolation insulating film on a semiconductor substrate, the step of sequentially forming a first oxide film and a nitride film on the main surface of the semiconductor substrate, and a part of the main surface of the semiconductor substrate being the main surface. Forming an opening in the first oxide film and the nitride film so as to be exposed as an exposed portion; and so as to keep the central portion of the main surface exposed portion exposed as a central exposed portion, A side formed of a second dioxide film, which covers the side walls of the first oxide film and the nitride film that define the side surface of the opening and a portion of the exposed portion of the main surface other than the central portion, the exposed surface being a protruding curved surface. Forming a wall portion; etching the central exposed portion using the sidewall portion as a mask to form an isolation trench in the semiconductor substrate; and using the nitride film and the sidewall portion as a mask, Said semiconductor substrate is selectively oxidized, the isolation insulating film forming method characterized by including the steps of forming the device isolation insulating film in the vicinity of the isolation trench.
方法において、半導体基板上のパターニングされた第一
酸化膜及び窒化膜から成る2層構造に対して、第二酸化
膜から成るサイドウォール部を形成後、前記サイドウォ
ール部をマスクとして半導体基板をエッチングして分離
溝を形成した後に、半導体基板を選択酸化することによ
って素子分離絶縁膜を形成することを特徴とする素子分
離絶縁膜形成方法。3. A method of forming an element isolation insulating film on a semiconductor substrate, wherein a sidewall portion made of a second dioxide film is provided to a two-layer structure made of a patterned first oxide film and a nitride film on the semiconductor substrate. After the formation, the semiconductor substrate is etched by using the sidewall portion as a mask to form an isolation groove, and then the element isolation insulating film is formed by selectively oxidizing the semiconductor substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29290095A JPH09134916A (en) | 1995-11-10 | 1995-11-10 | Formation of element isolation insulating film |
| KR19960054760A KR970030650A (en) | 1995-11-10 | 1996-11-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29290095A JPH09134916A (en) | 1995-11-10 | 1995-11-10 | Formation of element isolation insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09134916A true JPH09134916A (en) | 1997-05-20 |
Family
ID=17787856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29290095A Pending JPH09134916A (en) | 1995-11-10 | 1995-11-10 | Formation of element isolation insulating film |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH09134916A (en) |
| KR (1) | KR970030650A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518129B2 (en) | 2000-08-17 | 2003-02-11 | Koninklijke Philips Electronics N.V. | Manufacture of trench-gate semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59165434A (en) * | 1983-03-11 | 1984-09-18 | Toshiba Corp | Manufacture of semiconductor device |
| JPH01125845A (en) * | 1987-11-10 | 1989-05-18 | Sharp Corp | Element isolation of semiconductor device |
| JPH0817813A (en) * | 1994-06-24 | 1996-01-19 | Nec Corp | Method for manufacturing semiconductor device |
-
1995
- 1995-11-10 JP JP29290095A patent/JPH09134916A/en active Pending
-
1996
- 1996-11-11 KR KR19960054760A patent/KR970030650A/ko not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59165434A (en) * | 1983-03-11 | 1984-09-18 | Toshiba Corp | Manufacture of semiconductor device |
| JPH01125845A (en) * | 1987-11-10 | 1989-05-18 | Sharp Corp | Element isolation of semiconductor device |
| JPH0817813A (en) * | 1994-06-24 | 1996-01-19 | Nec Corp | Method for manufacturing semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518129B2 (en) | 2000-08-17 | 2003-02-11 | Koninklijke Philips Electronics N.V. | Manufacture of trench-gate semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970030650A (en) | 1997-06-26 |
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