JPH09129870A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a PMOS transistor, and facilitate the high speed stable operation, by additively introducing boron impurities in the interface region of a titanium silicide layer and a diffusion layer, through implantation of compensation ions. SOLUTION: A field oxide film 2, a gate oxide film 3, and a gate electrode 6 constituted of an N-type polycrystalline silicon layer 4 and a tungsten silicide layer 5 are formed on the surface of a silicon substrate 1. A P-type low concentration diffusion layer 7, a side wall film 8 and a P-type high concentration diffusion layer 9 are formed, and a thin titanium film 10 is deposited on the whole surface. A titanium silicide layer 11 is formed by heat treatment at 600-650 deg.C. After the titanium silicide layer 11 is formed only on the P-type high concentration diffusion layer 9 by implanting compensation ions 12, crystal structure is phase-inverted to C54 by performing once more high temperature heat treatment. Thereby high boron concentration is maintained in the surface of the P-type high concentration diffusion layer, and the contact resistance between the titanium silicide layer and the P-type high concentration diffusion layer is decreased and stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a p-channel type MOS transistor in which source / drain diffusion layers are silicided with titanium.

[0002]

2. Description of the Related Art Miniaturization and densification of semiconductor devices are still being energetically promoted.
An ultra-highly integrated semiconductor device such as a memory device or a logic device designed on the basis of a dimension of 0.25 μm has been developed and prototyped. With such high integration of semiconductor devices, it is particularly important to reduce the dimensions of the gate electrode width and the diffusion layer width and to reduce the thickness of the material forming the semiconductor element.

[0003] Among them, the reduction of the width of the gate electrode or the gate electrode wiring and the reduction of the film thickness of the gate electrode material are required.
Inevitably, these wiring resistances increase, which has a great influence on the delay of the circuit operation. Therefore, in a miniaturized semiconductor element, a technique of reducing the resistance of a high melting point metal silicide used as a part of a gate electrode material is regarded as an essential technique. In particular, the silicidation technique using titanium metal as the refractory metal is essential for fine insulated gate field effect transistors (hereinafter referred to as MOS transistors).

Further, in the MOS transistor having such a structure, it is necessary to suppress the diffusion of impurities forming a diffusion layer and suppress the short channel effect of the transistor in accordance with the tendency of high integration of the semiconductor device described above. No. As a result, the diffusion layer is also made shallower with higher integration. Further, as described above, it is also important to reduce the resistance of such a diffusion layer. Therefore, the silicidation of such a diffusion layer is also essential.

Here, M having a conventional silicide structure
A method of manufacturing the OS transistor will be described with reference to FIGS. 7 and 8. 7 and 8 are sectional views in the order of manufacturing steps showing a method of siliciding a diffusion layer of a p-channel MOS transistor (hereinafter referred to as pMOS transistor).

Hereinafter, the diffusion layer will be referred to as an LDD (Lightly
A pMOS transistor having a doped drain structure will be described as an example in the order of steps.

As shown in FIG. 7A, a field oxide film 102 is selectively formed on the surface of a silicon substrate 101 having an N type conductivity or a P well layer. Then, as shown in FIG. 7B, the gate oxide film 103 is formed by a known thermal oxidation method.

Next, on the gate oxide film 103, the N-type polycrystalline silicon layer 104 and the tungsten silicide layer 10 are formed.
The gate electrode 106 composed of 5 is patterned and formed. Next, as shown in FIG. 7C, in order to form the LDD layer of the pMOS transistor, boron ions 10
7 is ion-implanted. Here, the dose amount is 1 × 10 ¹³
/ Cm ² . As a result, the low concentration P-type diffusion layer 108 having low concentration impurities is formed.

Next, a silicon oxide film is deposited on the entire surface of the silicon substrate by a chemical vapor deposition (CVD) method, and anisotropic reactive ion etching (RIE) of the silicon oxide film is performed.
Thus, as shown in FIG. 7D, the sidewall film 109 is formed on the sidewall of the gate electrode 106. Then p
Boron difluoride ions 110 are implanted to form the source and drain diffusion layers of the MOS transistor. Here, the dose amount is about 1 × 10 ¹⁵ / cm ² . Then, heat treatment is applied to form a high-concentration P-type diffusion layer 111 containing high-concentration impurities.

Next, a titanium thin film 112 is formed on the entire surface of the silicon substrate 101. Then, heat treatment is performed to cause a silicide reaction between titanium and silicon on the surface of the high-concentration P-type diffusion layer 111, which is a source / drain. Next, the titanium remaining without undergoing the silicide reaction is removed. And FIG.
As shown in (b), the titanium silicide layer 113 is formed only on the high concentration P-type diffusion layer 111. The titanium silicide layer formed at this time has a crystal structure of C49. Next, heat treatment at a higher temperature than that for forming the titanium silicide layer having the C49 structure is performed again, and C54
Is converted into a titanium silicide layer having a crystal structure.
As a result, the silicide layer has a resistance lower than that of C49.

Next, as shown in FIG. 8C, an interlayer insulating film 114 is formed, a contact hole 115 is opened at a predetermined position where the titanium silicide layer 113 is formed, and an electrode wiring 116 is formed. It

As described above, in the active region surrounded by the field oxide film of the silicon substrate 101, the high-concentration P-type diffusion layer 111 whose surface is coated with the titanium silicide layer 113 is used as the source / drain, and the gate is formed. P having an oxide film 103 and a gate electrode 106 composed of an N-type polycrystalline silicon 104 and a tungsten silicide layer 105.
A MOS transistor is manufactured.

[0013]

In this conventional technique, the heat treatment is performed twice. This is because if titanium silicide is to be formed by a single high temperature heat treatment, a titanium silicide layer is also formed on the field oxide film separating the semiconductor elements and the elements are electrically short-circuited. Therefore, in the first heat treatment, a C49 titanium silicide layer is formed at a relatively low temperature (for example, about 650 ° C.), then unreacted titanium is removed, and then a heat treatment at a relatively high temperature (about 850 ° C.) is performed. A method is used in which the titanium silicide layer is phase-converted into a low-resistance C54 crystal structure.

However, when the titanium silicide layer is formed in the diffusion layer having the conductivity type of P in this way, the contact resistance between the titanium silicide layer and the diffusion layer of P type is increased or its variation is increased. The problem that it becomes abnormally large occurs. Although there are some unclear points regarding this reason, it is considered that boron in the diffusion layer segregates in the titanium silicide layer when the titanium silicide reacts with silicon to form a titanium silicide layer. At the interface between the titanium silicide layer and the diffusion layer, it is considered that the concentration of boron in the diffusion layer decreases and the contact resistance increases.

As described above, in the conventional manufacturing method, the contact resistance between the P-type diffusion layer and the titanium silicide layer becomes large, so that the driving capability of the pMOS transistor cannot be sufficiently drawn out, and the semiconductor device. It is difficult to improve the operating speed of.

The object of the present invention is to solve the above-mentioned problems,
Another object is to improve the performance of the pMOS transistor and facilitate high speed and stable operation of the semiconductor device.

[0017]

Therefore, according to the method of manufacturing a semiconductor device of the present invention, in the step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, a gate insulating film is formed on the surface of the semiconductor substrate. After the gate electrodes are sequentially laminated and formed, impurity ions containing boron impurities are implanted into the entire surface of the semiconductor substrate and heat treatment is performed to form the source / drain of the p-channel type insulated gate field effect transistor. A step of forming a diffusion layer,
A step of depositing a titanium thin film on the surface of the semiconductor substrate including the diffusion layer; and a heat treatment on the semiconductor substrate to cause a silicidation reaction between the surface of the diffusion layer and the titanium thin film to form titanium on the surface of the diffusion layer. The method includes the steps of forming a silicide layer, and after forming the titanium silicide layer, compensating ions are injected into an interface region between the titanium silicide layer and the diffusion layer, and boron impurities are additionally introduced into the interface region.

Alternatively, in the step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, after a gate insulating film and a gate electrode are sequentially laminated and formed on the surface of the semiconductor substrate, the surface of the semiconductor substrate is formed. A step of implanting impurity ions containing boron impurities and heat-treating the entire surface to form a diffusion layer serving as a source / drain of the p-channel type insulated gate field effect transistor;
Depositing a titanium thin film on the surface of the semiconductor substrate including the diffusion layer; and subjecting the semiconductor substrate to a first heat treatment to cause a silicidation reaction between the surface of the diffusion layer and the titanium thin film to form the diffusion layer. A step of forming a titanium silicide layer on the surface, and a step of, after forming the titanium silicide layer, injecting compensating ions into an interface region between the titanium silicide layer and the diffusion layer and additionally introducing a boron impurity into the interface region, Performing a second heat treatment on the semiconductor substrate having the titanium silicide layer formed thereon at a temperature higher than the temperature of the first heat treatment.

Alternatively, in the step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, a gate insulating film and a polycrystalline silicon layer not containing impurities and patterned into a gate electrode shape are sequentially formed on the surface of the semiconductor substrate. And a step of forming the diffusion layer to be the source / drain of the p-channel type insulated gate field effect transistor by implanting impurity ions containing boron impurities and heat-treating the entire surface of the semiconductor substrate. And a step of depositing a titanium thin film on the surface of the semiconductor substrate including the polycrystalline silicon layer and the diffusion layer, and performing a first heat treatment on the semiconductor substrate to form the surface of the polycrystalline silicon layer and the titanium. The surface of the polycrystalline silicon layer is formed by silicidizing the thin film and the surface of the diffusion layer with the titanium thin film. And a step of forming a titanium silicide layer on the surface of the diffusion layer, and, after forming the titanium silicide layer, an interface area between the titanium silicide layer and the polycrystalline silicon layer and an interface area between the titanium silicide layer and the diffusion layer. Implanting compensating ions into the interfacial region and additionally introducing boron impurities into these interface regions; and performing a second heat treatment on the semiconductor substrate having the titanium silicide layer formed thereon at a temperature higher than the temperature of the first heat treatment. including.

In such a semiconductor device manufacturing method, the titanium silicide layer is formed by the above-mentioned heat treatment or the first heat treatment. Then, at the stage of forming the titanium silicide layer, boron impurities on the surface of the diffusion layer are taken into the titanium silicide layer. Therefore, boron impurities are introduced into the surface portion of the polycrystalline silicon layer to be the gate electrode or the surface portion of the high-concentration P-type diffusion layer through implantation of compensation ions. Then, the second heat treatment converts the titanium silicide layer into a silicide layer having a crystal structure with lower resistance. At this stage of the second heat treatment, boron impurities are not taken into the titanium silicide layer. Therefore, the boron concentration on the surface of the polycrystalline silicon layer or the high-concentration P-type diffusion layer is kept high, and the titanium silicide layer and the polycrystalline silicon layer or the high-concentration P-type diffusion layer are maintained.
The contact resistance with the mold diffusion layer becomes low and becomes stable.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to FIG. 1A to 1D are cross-sectional views in the order of manufacturing steps of a pMOS transistor. Here, the process up to the step of FIG. 8A described in the conventional technique is the same as the conventional technique. That is, as shown in FIG. 1A, a field oxide film 2 is formed on the surface of a silicon substrate 1 having an N type conductivity or a P well layer. Then, the gate oxide film 3 is formed by a known thermal oxidation method. Here, the film thickness is set to about 10 nm.

Next, on the gate oxide film 3, a gate electrode 6 composed of an N-type polycrystalline silicon layer 4 and a tungsten silicide layer 5 is formed. Here, the thickness of the N-type polycrystalline silicon layer 4 is 100 nm and the thickness of the tungsten silicide layer 5 is 100 nm.
Is set to about 150 nm. Next, pMOS
Low concentration P with low impurity concentration that becomes the LDD layer of the transistor
The mold diffusion layer 7 is formed.

Next, a sidewall film 8 is formed on the sidewall of the gate electrode 6. Here, this film thickness is about 100 nm. Then, the high-concentration P-type diffusion layer 9 having a high impurity concentration and forming the source and drain diffusion layers of the pMOS transistor is formed. Then, the titanium thin film 10 is deposited on the entire surface of the silicon substrate 1. Here, the titanium thin film 10 is deposited by the sputtering method, and its thickness is set to about 40 nm.

Thereafter, as shown in FIG. 1B, a silicide reaction between titanium and silicon on the surface of the high-concentration P-type diffusion layer 9 serving as the source / drain is performed by heat treatment at a temperature of 600 to 650 ° C. in a nitrogen atmosphere. Is done. Then, the titanium silicide layer 11 having a crystal structure of C49 is formed. By this silicide reaction, silicon atoms in the P-type diffusion layer are taken into reaction with titanium, and boron atoms in this region are also segregated in this silicide layer. Therefore, at the interface between the titanium silicide layer 11 and the high-concentration P-type diffusion layer 9, the boron concentration on the surface portion of the high-concentration P-type diffusion layer 9 decreases.

Next, as shown in FIG. 1B, the compensation ions 12 are ion-implanted. Here, this compensation ion 1
2 is an ion of boron difluoride, that is, BF ₂ . Then, the implantation energy is set in the range of 30 to 50 keV. Also, the dose amount is 1 × 10 ¹⁴ / cm
It is set to ^{2 ~2 × 10 15 / cm 2} .

Next, the titanium remaining without undergoing the silicide reaction is removed. Then, the titanium silicide layer 11 is formed only on the high concentration P-type diffusion layer 9. Then C again
Heat treatment at a temperature higher than that for forming the titanium silicide layer of No. 49 causes the crystal structure to undergo phase conversion to C54. As a result, the silicide layer has a resistance lower than that of C49.
Here, this heat treatment is performed at a temperature of 800 to 8 in a nitrogen atmosphere.
The setting is performed at 50 ° C. In this stage heat treatment,
Boron atoms on the surface of the high concentration P-type diffusion layer 9 are not taken into the titanium silicide layer 11. Therefore, the boron concentration on the surface of the high concentration P-type diffusion layer 9 does not decrease.

Next, as shown in FIG. 1C, an interlayer insulating film 13 is formed, a contact hole 14 is opened at a predetermined position where the titanium silicide layer 11 is formed, and an electrode wiring 15 is formed. It As described above, FIG.
The pMOS transistor shown in (c) is manufactured.

As described above, in the embodiment of the present invention, after the titanium silicide layer having the C49 structure is formed by the first heat treatment, boron is introduced into the surface portion of the high concentration P-type diffusion layer through the implantation of compensation ions. It Then, the titanium silicide layer is converted into the C54 structure by the second heat treatment. Then, at the stage of this second heat treatment, boron impurities are not segregated in the titanium silicide layer. Therefore, the boron impurity concentration on the surface of the high-concentration P-type diffusion layer is kept high, and the contact resistance between the titanium silicide layer and the high-concentration P-type diffusion layer is low and stable.

Next, the second embodiment of the present invention will be described with reference to FIGS. 2 and 3.
An embodiment will be described. 2 and 3 are cross-sectional views in the order of manufacturing steps in the case where a salicide technique is used for manufacturing a pMOS transistor.

As shown in FIG. 2A, a field oxide film 2 is formed on the surface of a silicon substrate 1 having an N type conductivity or a P well layer. Then, the gate oxide film 3
Is formed of a SiON film by a thermal oxidation method and a thermal nitriding method.
Here, the film thickness is set to about 6 nm.

Next, a polycrystalline silicon layer 4a is formed on the gate oxide film 3. Here, the N polycrystalline silicon layer 4a has a film thickness of 150 nm and contains no impurities.
Next, as shown in FIG. 2B, boron ions 16 are implanted. Here, the implantation energy is 20 keV
The dose is set to about 3 × 10 ¹³ / cm ² . In this way, the low-concentration P-type diffusion layer 7 having a low impurity concentration and serving as the LDD layer of the pMOS transistor is formed. Further, boron impurities are also introduced into the polycrystalline silicon layer 4a.

Next, as shown in FIG. 2C, a sidewall film 8 is formed on the sidewall of the polycrystalline silicon layer 4a. Here, this film thickness is about 100 nm. Then, the boron difluoride ions 17 are ion-implanted. Here, the implantation energy is 40 keV and the dose amount is set to about 5 × 10 ¹⁴ / cm ² . In this way, the high-concentration P-type diffusion layer 9 with a high impurity concentration that forms the source and drain diffusion layers of the pMOS transistor is formed. Also at this time, boron impurities are introduced into the polycrystalline silicon layer 4a.

Next, as shown in FIG. 2D, a titanium thin film 10 is deposited on the entire surface of the silicon substrate 1. here,
This titanium thin film 10 is deposited by the sputtering method, and its film thickness is set to about 40 nm.

Thereafter, a heat treatment is performed at a temperature of 650 ° C. in a nitrogen atmosphere to perform a silicidation reaction between titanium and silicon on the surface of the high-concentration P-type diffusion layer 9 which is a source / drain, and polycrystalline silicon containing titanium and boron. A silicidation reaction with the silicon of layer 4a takes place. And FIG.
As shown in (a), the titanium silicide layer 11 and the on-gate titanium silicide layer 18 are formed.
Here, the crystal structure of these titanium silicide layers is C4.
9

Next, as shown in FIG. 3A, the compensation ions 12 are ion-implanted. Here, this compensation ion 1
2 is a BF ₂ ion. Then, the implantation energy is set to 40 keV. The dose is 5
It is set to × 10 ¹⁴ / cm ² .

Next, the titanium remaining without undergoing the silicide reaction is removed. Then, the titanium silicide layer 11 is formed only on the high-concentration P-type diffusion layer 9, and the polycrystalline silicon layer 4 is formed.
An on-gate titanium silicide layer 18 is formed only on a. Next, heat treatment is performed at a temperature of about 800 ° C., and the crystal structure of these titanium silicide layers is phase-converted to C54.

Next, as shown in FIG. 3B, an interlayer insulating film 13 is formed, a contact hole 14 is opened at a predetermined position where the titanium silicide layer 11 is formed, and an electrode wiring 15 is formed. It

As described above, in the active region surrounded by the field oxide film 2 of the silicon substrate 1, the high-concentration P-type diffusion layer 9 whose surface is coated with the titanium silicide layer 11 is used as the source / drain. A pMOS transistor having the gate oxide film 3 and the gate electrode 6 composed of the polycrystalline silicon layer 4a and the titanium silicide layer on the gate 18 is manufactured.

In this embodiment, compensating ions are implanted into the interface region between the titanium silicide layer and the polycrystalline silicon layer and the interface region between the titanium silicide layer and the diffusion layer, and boron impurities are additionally introduced into these interface regions. Therefore, the electric resistance of these interface regions is reduced and further stabilized.

However, in this embodiment, it is necessary to control the amount of boron contained in the polycrystalline silicon layer 4a.
The reason for this is that if the amount of boron is too large, this boron will pass through the gate oxide film 3 and enter the channel region, resulting in pMO.
This is because the S transistor characteristic becomes abnormal.

Next, a third embodiment of the present invention will be described with reference to FIGS. 4 to 6 are cross-sectional views in the order of manufacturing steps when manufacturing a CMOS transistor using the present invention. The following manufacturing method is basically the first
Alternatively, since it is similar to the second embodiment, it will be briefly described. In addition, the n-channel MOS transistor is nM
It is called an OS transistor.

As shown in FIG. 4A, the silicon substrate 1
Then, an N well 21 and a P well 22 are formed, and a field oxide film 2 is formed. Next, as shown in FIG. 4B, a gate oxide film 3 is formed, and a gate electrode 6 composed of an N-type polycrystalline silicon layer 4 and a tungsten silicide layer 5 is formed thereon. Next, as shown in FIG. 4C, a resist pattern 23 is provided on the pMOS transistor side, phosphorus impurities (denoted by P in the figure) are ion-implanted, and the nMOS transistor side is doped with a low concentration N of a low impurity concentration.
The mold diffusion layer 24 is formed. Similarly, as shown in FIG. 4D, this time, a resist pattern 23 is provided on the nMOS transistor side, and a boron impurity (denoted by B in the drawing).
Is ion-implanted to form a low concentration P-type diffusion layer 7 on the pMOS transistor side.

Next, as shown in FIG. 5A, a sidewall film 8 is formed on the sidewall of the gate electrode 6. afterwards,
As shown in FIG. 5B, the pMOS side is covered with the resist pattern 23, and arsenic impurities (denoted by As in the figure) on the nMOS transistor side are 1 × 10 ^{15 to} 3 × 10 ¹⁵ /.
A high-concentration N-type diffusion layer 25 serving as a source / drain is formed by ion implantation with a dose of cm ² . Similarly, FIG.
As shown in (c), this time, a resist pattern 23 is provided on the nMOS transistor side, and boron difluoride ions (denoted as BF _{2 in the} figure) are 1 × 10 ^{15 to} 3 × 10 ^15.
A high concentration P-type diffusion layer 9 serving as a source / drain is formed by ion implantation with an implantation amount of / cm ² .

Then, heat treatment is applied to activate the implanted impurities. Next, as shown in FIG.
The titanium thin film 10 is deposited on the entire surface of the silicon substrate, and the first
The titanium silicide layer 11 having the C49 crystal structure is subjected to the heat treatment of, and the high concentration P-type diffusion layer 9 and the high concentration N are formed.
It is formed on the surface of the mold diffusion layer 25.

Next, as shown in FIG. 6A, the compensation ions 12 are ion-implanted over the entire surface. Here, the implantation energy is 50 keV, and the implantation amount is 1 × 10 ¹⁴ to 1
It is set within the range of × 10 ¹⁵ / cm ² . However, the implantation amount at this time is the high-concentration N-type diffusion layer 25 of the nMOS transistor.
Is set so as to be half or less than the implantation amount of arsenic impurities implanted for forming.

Next, as in the first and second embodiments, the unreacted titanium thin film is removed, and the crystal structure of the titanium silicide layer is changed from C49 to C54 by the second phase conversion. Heat treatment is performed.

After that, as shown in FIG. 6B, the interlayer insulating film 13 is formed, and the contact hole 14 is formed at a predetermined position.
Is opened and the electrode wiring 15 is provided.

In the third embodiment, the compensation ions 12 which are P-type impurities are ion-implanted into the source / drain diffusion layers of the nMOS transistor and the pMOS transistor. Since it is set to be less than or equal to half the implantation amount of the N-type impurity for forming the n-type impurity, the source / drain diffusion layer of the nMOS transistor, that is, the high-concentration N-type diffusion layer 25 remains N-type. As described above, even when the present invention is applied to the CMOS transistor, the entire manufacturing process can be shortened by appropriately selecting the implantation amount of the compensation ions 12.

In the above embodiments, the case where the silicidation of titanium is performed by the two-step heat treatment process has been described. However, the present invention is not limited to such heat treatment. It should be noted that the present invention produces the same effect even when the titanium silicide layer is formed by the one-step heat treatment process.

[0050]

As described above, according to the present invention, a titanium thin film is deposited on the surface of a P-type diffusion layer in the production of a pMOS transistor having a diffusion layer silicided with titanium, and C49 is formed by the first heat treatment. After the titanium silicide layer having the structure is formed on the surface of the P type diffusion layer, boron is introduced into the surface portion of the P type diffusion layer through the implantation of compensation ions. Then, the titanium silicide layer is converted into the 54 structure by the second heat treatment. For this reason, high concentration P
The boron concentration on the surface of the type diffusion layer is maintained high, and the contact resistance between the titanium silicide layer and the high concentration P type diffusion layer becomes low and stabilized.

In this way, the driving capability of the pMOS transistor is greatly improved, and the speed of the semiconductor device is further increased.

[Brief description of the drawings]

1A to 1C are cross-sectional views in order of the steps, illustrating a first embodiment of the present invention.

2A to 2D are cross-sectional views in order of the steps, illustrating a second embodiment of the present invention.

3A to 3D are cross-sectional views in order of the steps, illustrating a second embodiment of the present invention.

4A to 4D are cross-sectional views in order of the steps, illustrating a third embodiment of the present invention.

FIG. 5 is a cross-sectional view in order of the steps, illustrating a third embodiment of the present invention.

FIG. 6 is a cross-sectional view in order of the steps, illustrating a third embodiment of the present invention.

FIG. 7 is a cross-sectional view in the order of steps for explaining a conventional technique.

8A to 8D are cross-sectional views in order of the processes, for illustrating the conventional technique.

[Explanation of symbols]

 1, 101 Silicon substrate 2, 102 Field oxide film 3, 103 Gate oxide film 4, 104 N-type polycrystalline silicon layer 4a Polycrystalline silicon layer 5, 105 Tungsten silicide layer 6, 106 Gate electrode 7, 108 Low concentration P-type diffusion Layer 8,109 Sidewall film 9,111 High-concentration P type diffusion layer 10,112 Titanium thin film 11,113 Titanium silicide layer 12 Compensation ion 13,114 Interlayer insulating film 14,115 Contact hole 15,116 Electrode wiring 16,107 Boron Ion 17,110 Boron difluoride ion 18 Titanium silicide layer on gate 21 N well 22 P well 23 Resist pattern 24 Low concentration N type diffusion layer 25 High concentration N type diffusion layer

Claims (3)

[Claims] 1. In a step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, after forming a gate insulating film and a gate electrode on the surface of the semiconductor substrate, boron impurities are formed on the entire surface of the semiconductor substrate. A step of forming a diffusion layer serving as a source / drain of the p-channel type insulated gate field effect transistor by injecting the contained impurity ions and performing a heat treatment, and a titanium thin film on the surface of the semiconductor substrate including the diffusion layer. The step of depositing,
Performing a heat treatment on the semiconductor substrate to cause a silicidation reaction between the surface of the diffusion layer and the titanium thin film to form a titanium silicide layer on the surface of the diffusion layer; and after forming the titanium silicide layer, the titanium silicide layer. And a step of implanting compensation ions into the interface region between the diffusion layer and additionally introducing boron impurities into this interface region. 2. A step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, after forming a gate insulating film and a gate electrode on the surface of the semiconductor substrate, boron impurities are formed on the entire surface of the semiconductor substrate. A step of forming a diffusion layer serving as a source / drain of the p-channel type insulated gate field effect transistor by injecting the contained impurity ions and performing a heat treatment, and a titanium thin film on the surface of the semiconductor substrate including the diffusion layer. The step of depositing,
Performing a first heat treatment on the semiconductor substrate to cause a silicidation reaction between the surface of the diffusion layer and the titanium thin film to form a titanium silicide layer on the surface of the diffusion layer; and after forming the titanium silicide layer, A step of implanting compensation ions into the interface region between the titanium silicide layer and the diffusion layer and additionally introducing boron impurities into the interface region, and a temperature higher than the temperature of the first heat treatment for the semiconductor substrate on which the titanium silicide layer is formed. Applying a second heat treatment at a temperature,
A method for manufacturing a semiconductor device, comprising: 3. In the step of forming a p-channel type insulated gate field effect transistor on a semiconductor substrate, a gate insulating film and a polycrystalline silicon layer which does not contain impurities and is patterned into a gate electrode shape are sequentially formed on the surface of the semiconductor substrate. And a step of forming the diffusion layer to be the source / drain of the p-channel type insulated gate field effect transistor by implanting impurity ions containing boron impurities and heat-treating the entire surface of the semiconductor substrate. And the process of
Depositing a titanium thin film on the surface of the semiconductor substrate including the polycrystalline silicon layer and the diffusion layer; and subjecting the semiconductor substrate to a first heat treatment to form the surface of the polycrystalline silicon layer, the titanium thin film, and the diffusion. Forming a titanium silicide layer on the surface of the polycrystalline silicon layer and the surface of the diffusion layer by subjecting the surface of the layer and the titanium thin film to a silicidation reaction; and after forming the titanium silicide layer, the titanium silicide layer and the polycrystalline layer. A step of implanting compensating ions into the interface region with the silicon layer and the interface region between the titanium silicide layer and the diffusion layer to introduce boron impurities into these interface regions, and to the semiconductor substrate on which the titanium silicide layer is formed. Performing a second heat treatment at a temperature higher than the temperature of the first heat treatment. The method of production.