JPH09129867A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a structure that reduces the gate resistance and maximizes the effect of reducing the on-resistance by reducing the distance between source contacts. In a horizontal DSA power MOSFET, two sides parallel to a diagonal line are formed on a diagonal intersection of a quadrangle formed by source contact holes 25 that define four adjacent source contacts arranged regularly at equal pitches. Drain contact hole 2 defining a rhombic drain contact including a square with
By arranging 7, the distance between the source contacts is reduced and the on-resistance is reduced. Further, the gate electrode 23 forming an insulated gate together with the gate insulating film provided on the P-type base layer surrounds the source and drain contacts and is formed in a bent mesh shape, thereby reducing the gate resistance.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device, and more particularly to a unit cell structure of a lateral DSA (double diffusion self-alignment type) power MOSFET (insulated gate field effect transistor).

[0002]

2. Description of the Related Art A lateral DSA power MOSFET defines a channel length in a self-aligned manner by double diffusion of impurities on the surface of a semiconductor substrate using an insulating gate as a mask. As shown in the cross-sectional views taken along the line II-II ′ of FIG.
Japanese Patent Application Laid-Open No. 2 (hereinafter referred to as Conventional Example 1) discloses an arrangement arranged in a deformed stripe shape. As shown in the plan view of FIG. 7 and the cross-sectional view taken along the line IV-IV ′ of FIG. 8 in FIG. Are formed so as to alternately surround square source and drain contact holes 25 and 27 arranged at predetermined intervals, and have a layout in which these are arranged in a rectangular wave shape. MO having an insulated gate with such a modified stripe arrangement
The SFET can be formed with a longer gate width per unit area than that of the conventional mesh arrangement, and accordingly, the ON resistance is small and the loss is small, so
The efficiency as T is good.

[0003]

In this conventional power MOSFET having a modified striped gate electrode, a source contact is regularly arranged at an equal pitch, and a drain contact is arranged on a diagonal intersection thereof. Since the square pattern has the same shape as the contacts, the distance between the source contacts cannot be reduced, and the ratio of the gate width to the unit area cannot be said to be sufficiently large. Further, since the modified striped gate electrode is formed in a rectangular wave shape, the power MOSF having a large cell area is formed.
In ET, uniform operation of each unit cell is difficult due to the influence of gate resistance. For these reasons, there is a problem that the on-resistance cannot be reduced in the power MOSFET having the above structure.

Therefore, a technical problem of the present invention is to provide an insulated gate semiconductor device having a structure that maximizes the effect of reducing the on-resistance by reducing the gate resistance and reducing the distance between the source contacts. To do.

[0005]

In order to solve the above technical problems, in a semiconductor device of the present invention, a substantially square source is regularly arranged on a surface of a semiconductor substrate at a constant pitch in two directions intersecting with each other. In a semiconductor device having a lateral DSA power MOSFET having contacts, at least one of the diagonal lines of a quadrangle formed by a line segment connecting the centers of four source contacts adjacent to each other has two sides parallel to each other. It is characterized by having a square drain contact.

Further, the semiconductor device of the present invention is characterized in that, in the semiconductor device, the drain contact is a rhombus including a square.

Further, the semiconductor device of the present invention is characterized in that the rhombus has a center at an intersection of the diagonal lines.

In addition, the semiconductor device of the present invention is characterized in that, in any one of the semiconductor devices, an insulated gate is formed in a mesh shape surrounding the source contact and the drain contact. .

Here, in the semiconductor device of the present invention,
In the semiconductor device, it is preferable that the insulated gate has an opening for forming an N ⁺ type drain extraction layer by self-alignment.
N ⁺ -type drain diffusion region so as to surround the channel region of the FET is formed in a mesh shape, the N ⁺ -type drain diffusion region is preferably formed on the S surface under the gate electrode by ion implantation of high energy.

Further, the semiconductor device of the present invention includes source contacts arranged at a constant pitch in two directions intersecting with each other on the surface of the semiconductor substrate and a plurality of polygonal insulated gates arranged around the source contacts. And a drain region formed in the semiconductor substrate region having a polygonal shape defined by four insulated gates adjacent to each other among the plurality of insulated gates, the drain provided on the drain region And a contact.

Further, in the semiconductor device of the present invention, in the semiconductor device, the drain contact is provided on an intersection of diagonal lines of a quadrangle formed by the adjacent four on the semiconductor substrate plane. Characterize.

The semiconductor device of the present invention is characterized in that, in the semiconductor device, the polygon formed by the insulated gate is an octagon.

Further, the semiconductor device of the present invention is characterized in that, in the semiconductor device, the drain layer is a rhombus or an octagon including a square in a plane of the semiconductor substrate.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a VI of the semiconductor device of FIG.
FIG. 6 is a cross-sectional view along the line VI ′.

Referring to FIGS. 1 and 2, an N-type Si substrate 11 composed of an N-type epitaxial layer or an N-type well layer is provided with a P-type base layer having a square plane without corners, that is, an octagonal channel region. 13 are formed at equal pitch intervals in directions orthogonal to each other, and four adjacent P-type base layers 1 are formed.
3 are arranged at the vertices of a square. At the center position of the square, a diamond-shaped N having four sides so as to be in contact with the short sides inside the region of the octagonal P-type base layer 13 respectively.
^{The +} type drain layer 15 is formed via the field oxide film 17. In the P-type base layer 13, an N ⁺ -type source layer 19 is formed in a square frame shape without corners. A gate oxide film 21 is formed between an outer end of the N ⁺ type source layer 19 and the field oxide film 17 so as to cover an edge of the P-type base layer 13 and a part of the field oxide film 17. A gate electrode 23 made of poly-Si or the like is formed in a square having no corners, that is, an octagon in a plan view. The gate electrode 23 is a square source contact hole 2 formed on the center of the N ⁺ type source layer 19 on the semiconductor substrate plane.
5 and the drain contact hole 27 formed on the center of the N ⁺ type drain layer 15 is formed in a bent mesh shape. The source contact hole 25 on the surface of the portion surrounded by the N ⁺ -type source layer 19 at the center of the P-type base layer 13 and on the surface of the center of the N ⁺ -type drain layer 15 at the center of the P-type base layer 13. A first interlayer insulating film 29 is provided except for the drain contact hole 27. Reference numeral 33a denotes a gate electrode opening for forming an N ⁺ type drain lead region. In addition, code 1
Reference numeral 5a is an N ⁺ type drain lead layer. The gate electrode opening 33a is provided for forming the N ⁺ -type drain lead-out region 15a by self-alignment. Here, the field oxide film 17 reduces the electric field at the end of the gate electrode 23 to obtain the target breakdown voltage. On the source contact hole 25 and the drain contact hole 27,
First metal electrodes 31 each having a T-shaped side cross section are provided. These first metal electrodes 31 are provided with a second interlayer insulating film 33 except for the first metal portions on the drain contact holes 27, and the second metal electrodes 3 are further formed thereon.
5 are provided. The first metal electrode 31 and the second metal electrode 35 are electrically connected via a contact hole 37 located on the N ⁺ type drain layer 15.

In the above-described first embodiment, the shape of the drain contact arranged on the diagonal intersection with respect to the source contacts arranged regularly at equal pitches is a rhombus including a square having four sides along the diagonal. It is formed in a shape. In other words, the rhombus reduces the distance between the source contacts and the on-resistance.

Further, as described above, the gate electrode 23 forming the insulated gate together with the gate oxide film 21 formed on the P-type base layer surrounds the source contact hole 25 and the drain contact hole 27, and has a bent mesh shape. have. By doing so, the gate resistance is reduced, and uniform MOS operation of each unit cell becomes possible.

The N ⁺ type source layer 19 and the P type base layer 13 have a DSA structure in which the gate electrode 23 is used as a mask to doubly diffuse, and the channel length and threshold voltage are controlled in a self-aligned manner. The N ⁺ -type source layer 19 and the N ⁺ -type drain layer 15 may be formed in the same step or in separate steps.

Although not shown, the source electrode and the drain electrode may be separately formed by the first metal layer.

FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. FIG. 4 is a cross-sectional view taken along the line VIII-VIII 'in FIG. 3, and portions equivalent to those in FIG. 2 are denoted by the same reference numerals as in FIG. Referring to FIGS. 3 and 4, the gate electrode 23 is not provided with an opening for forming an N ⁺ -type drain extraction layer. In the plan view, the N ⁺ -type drain layer 15 surrounded by the octagonal gate electrode is formed in an octagonal shape obtained by cutting off four corners of a rhombus including a square.
The long side of the octagon is formed so as to circumscribe the short side of the octagonal gate electrode region. The N ⁺ -type drain extraction layer 15a is formed on the Si surface below the gate electrode 23 by performing high-energy ion implantation of several hundred keV of phosphorus using a photoresist as a mask. This is the first
This is a cell pattern having the same effect as that of the embodiment.
4, the N ⁺ -type drain layer 15 is a deep diffusion layer because it is formed by high-energy ion implantation as compared with FIG.

[0022]

As described above, according to the present invention, in the lateral DSA power MOSFET, the distance between the source contacts can be reduced, the channel width per unit area increases, and the on-resistance can be reduced.

Further, in the present invention, the uniform gate of the unit cell is formed by forming the insulated gate in a mesh shape.
The operation is enabled, and the on-resistance can be further reduced.

In the present invention, a quadrangle having two sides parallel to at least one of the quadrangular diagonals formed by the line segments connecting the centers of the four source contacts adjacent to each other, for example, Since the diamond-shaped drain contacts are arranged so as to have a side parallel to the diagonal line between the source contacts to reduce the distance between the source contacts, the on-resistance is reduced.

Further, in the present invention, since the insulated gate has a deformed mesh-like structure and is continuous over the entire chip, even in a large chip area, uniform MOS operation of each unit cell is possible, and switches such as switches are In terms of characteristics, stable characteristics can be obtained.

From the above, the horizontal DSA power MOS of the present invention
The semiconductor device including the FET has an effect that stable device characteristics are obtained and the on-resistance is reduced by about 30%.

[Brief description of the drawings]

FIG. 1 is a power MOS showing a first embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

FIG. 2 is a sectional view taken along line VI-VI of FIG.

FIG. 3 is a power MOS showing a second embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

FIG. 4 is a sectional view taken along the line VIII-VIII ′ of FIG.

FIG. 5 is a partial plan view showing an example of a conventional power MOSFET.

FIG. 6 is a sectional view taken along the line II-II ′ of FIG.

FIG. 7 is a partial plan view showing another example of a conventional power MOSFET.

FIG. 8 is a sectional view taken along line IV-IV ′ of FIG. 7;

[Explanation of symbols]

Reference Signs List 11 N-type Si substrate (N-type epitaxial layer N-type well layer) 13 P-type base layer 15 N ⁺ -type drain layer 15 a N ⁺ -type drain extraction layer 17 Field oxide film 19 N ⁺ -type source layer 21 Gate oxide film 23 Gate electrode 33a Gate electrode opening 25 Source contact hole 27 Drain contact hole 29 First interlayer insulating film 31 First metal electrode 33 Second interlayer insulating film 35 Second metal electrode 37 Contact hole

Claims (10)

[Claims] 1. A semiconductor device including a lateral DSA power MOSFET having substantially square source contacts regularly arranged at a constant pitch in two directions intersecting with each other on a surface of a semiconductor substrate, and four source contacts adjacent to each other. A semiconductor device having a square drain contact having two sides parallel to at least one of the diagonal lines of the square formed by a line segment connecting the centers of the two. 2. The semiconductor device according to claim 1, wherein the drain contact is a rhombus including a square. 3. The semiconductor device according to claim 2, wherein the rhombus has a center on an intersection of the diagonal lines. 4. The semiconductor device according to claim 1, further comprising an insulated gate formed in a mesh shape surrounding the source contact and the drain contact. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the insulated gate has an opening for forming an N ⁺ -type drain extraction layer by self-alignment. 6. The semiconductor device according to claim 4, wherein the N ⁺ type drain diffusion region is formed in a mesh shape so as to surround the channel region of the laminated power MOSFET, and the N ⁺ type drain diffusion region has high energy ions. A semiconductor device, which is formed on the surface of S under the gate electrode by implantation. 7. A source contact arranged at a constant pitch in two directions intersecting with each other on a surface of a semiconductor substrate, a plurality of polygonal insulated gates arranged around the source contact, and the plurality of insulated gates. A drain region formed in the semiconductor substrate region having a polygonal shape defined by four insulated gates adjacent to each other, and a drain contact provided on the drain region. Semiconductor device. 8. The semiconductor device according to claim 7, wherein the drain contact is provided on an intersection of diagonal lines of a quadrangle formed by the adjacent four on the semiconductor substrate plane. Semiconductor device. 9. The semiconductor device according to claim 8, wherein the polygon formed by the insulated gate is an octagon. 10. The semiconductor device according to claim 9, wherein
The semiconductor device, wherein the drain layer is a rhombus or an octagon including a square in a plane of the semiconductor substrate.