JPH09129417A - Forming method of varistor outer electrode - Google Patents
Forming method of varistor outer electrodeInfo
- Publication number
- JPH09129417A JPH09129417A JP7306872A JP30687295A JPH09129417A JP H09129417 A JPH09129417 A JP H09129417A JP 7306872 A JP7306872 A JP 7306872A JP 30687295 A JP30687295 A JP 30687295A JP H09129417 A JPH09129417 A JP H09129417A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode
- varistor
- film electrode
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 58
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 239000010408 film Substances 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims description 13
- 238000007598 dipping method Methods 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 5
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract description 5
- 229910001120 nichrome Inorganic materials 0.000 abstract description 5
- 229910003322 NiCu Inorganic materials 0.000 abstract description 4
- 230000002542 deteriorative effect Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、バリスタの電極形
成方法に関し、詳しくは、酸やアルカリに侵されやすい
バリスタ素体に、ダメージを与えることなく良好な外部
電極を形成することが可能なバリスタの外部電極形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a varistor electrode, and more particularly, it can form a good external electrode without damaging a varistor element body that is easily attacked by acid or alkali. The external electrode forming method of
【０００２】[0002]
【従来の技術及び発明が解決しようとする課題】従来、
チップ型（表面実装型）積層セラミックコンデンサなど
のセラミック電子部品に外部電極を形成する場合、素体
上に銀や銀−パラジウムなどを導電成分とする導電ペー
ストを塗布、焼付けして銀や銀−パラジウムの厚膜電極
を形成した後、その上にニッケルやスズなどを湿式メッ
キすることにより外部電極を形成している。2. Description of the Related Art
When forming external electrodes on a ceramic electronic component such as a chip-type (surface-mounting) monolithic ceramic capacitor, a conductive paste containing silver or silver-palladium as a conductive component is applied on the element body and baked to form silver or silver- After forming a thick film electrode of palladium, the external electrode is formed by wet plating nickel or tin on the electrode.
【０００３】しかし、例えば、サージ吸収素子として用
いられるバリスタは、バリスタ素体が酸やアルカリに侵
されやすく、上述のような湿式メッキ工程を含む方法を
用いにくいため、バリスタ素体に導電ペーストを塗布、
焼付けすることにより形成した銀−パラジウム厚膜電極
をそのまま外部電極としたり、バリスタ素体にニッケル
系合金−銀などをスパッタリング法や蒸着法などにより
乾式メッキした薄膜電極をそのまま外部電極としたりす
ることが多い。However, for example, in a varistor used as a surge absorbing element, the varistor element body is easily attacked by an acid or an alkali, and it is difficult to use the method including the wet plating step as described above. Application,
The silver-palladium thick film electrode formed by baking can be used as the external electrode as it is, or the thin film electrode obtained by dry-plating the varistor element body with nickel alloy-silver etc. by sputtering or vapor deposition can be used as the external electrode. There are many.
【０００４】しかし、銀−パラジウム電極を塗布、焼付
けした厚膜電極を外部電極とした場合には、はんだ付性
不良やはんだ耐熱性不良を発生しやすいという問題点が
ある。また、スパッタリング法や蒸着法などの乾式メッ
キ法で形成した薄膜電極を外部電極とした場合には、は
んだ付性やはんだ耐熱性には優れているが、バリスタが
吸収するサージ電流により電極が熱破壊を起こすという
問題点がある。However, when a thick film electrode formed by coating and baking a silver-palladium electrode is used as an external electrode, there is a problem that defective solderability and defective solder heat resistance are likely to occur. When a thin film electrode formed by dry plating such as sputtering or vapor deposition is used as an external electrode, it has excellent solderability and solder heat resistance, but the surge current absorbed by the varistor causes the electrode to heat up. There is a problem of causing destruction.
【０００５】また、スパッタリング法や蒸着法などの乾
式メッキ法で形成された薄膜電極の場合、はんだ付性や
はんだ耐熱性には優れているが、バリスタが吸収するサ
ージ電流により電極が熱破壊し易いという問題点があ
る。Further, in the case of a thin film electrode formed by a dry plating method such as a sputtering method or a vapor deposition method, although the solderability and the solder heat resistance are excellent, the electrode is thermally destroyed due to the surge current absorbed by the varistor. There is a problem that it is easy.
【０００６】本発明は、上記の問題点を解決するもので
あり、バリスタ素体を劣化させることなく、はんだ付
性、はんだ耐熱性、サージ耐量などに優れた外部電極を
確実に形成することが可能なバリスタの外部電極形成方
法を提供することを目的とする。The present invention solves the above-mentioned problems, and it is possible to reliably form an external electrode excellent in solderability, solder heat resistance, surge resistance, etc. without deteriorating the varistor element body. An object is to provide a method of forming an external electrode of a possible varistor.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明のバリスタの外部電極形成方法は、バリスタ
素体の所定の位置に、乾式メッキ法により薄膜電極を形
成する薄膜電極形成工程と、前記薄膜電極形成工程にお
いて形成された薄膜電極上に、はんだ浸漬法によりはん
だ厚膜電極を形成するはんだ厚膜電極形成工程とを具備
することを特徴としている。In order to achieve the above object, a method of forming an external electrode of a varistor according to the present invention is a thin film electrode forming step of forming a thin film electrode at a predetermined position of a varistor element body by a dry plating method. And a solder thick film electrode forming step of forming a solder thick film electrode by a solder dipping method on the thin film electrode formed in the thin film electrode forming step.
【０００８】また、乾式メッキ法により種類の異なる複
数の薄膜を順次成膜して、複層構造の薄膜電極を形成す
ることを特徴としている。Further, it is characterized in that a plurality of thin films of different types are sequentially formed by a dry plating method to form a thin film electrode having a multilayer structure.
【０００９】[0009]
【作用】バリスタ素体の所定の位置に乾式メッキ法によ
り薄膜電極を形成した後、その上に、はんだ浸漬法によ
りはんだ厚膜電極を形成することによって、はんだ厚膜
電極により、薄膜電極だけでは不十分である耐サージ性
を改善することが可能になるとともに、薄膜電極により
優れたはんだ付性やはんだ耐熱性を確保することが可能
になる。したがって、本発明の方法によれば、バリスタ
素体を劣化させることなく、はんだ付性、はんだ耐熱性
が良好で、しかもサージ耐量に優れた外部電極を確実に
形成することが可能になる。The thin film electrode is formed on the varistor element body at a predetermined position by the dry plating method, and then the solder thick film electrode is formed thereon by the solder dipping method. Insufficient surge resistance can be improved, and excellent solderability and solder heat resistance can be secured by the thin film electrode. Therefore, according to the method of the present invention, it is possible to reliably form the external electrode having good solderability and solder heat resistance and excellent surge resistance without deteriorating the varistor element body.
【００１０】また、前記乾式メッキ法により種類の異な
る複数の薄膜を順次成膜して、バリスタ素体上に複層構
造の薄膜電極を形成することにより、はんだ浸漬による
はんだ厚膜電極の形成時、及び実装時のはんだ付け工程
ではんだ喰われが生じることのない外部電極を形成し
て、本発明をより実効あらしめることが可能になる。す
なわち、例えば、バリスタ素体の表面に、ＮｉＣｒ薄
膜、ＮｉＣｕ薄膜、Ａｇ薄膜などを順次成膜して複層構
造の薄膜電極を形成することにより、はんだ浸漬による
はんだ厚膜電極の形成時や実装時のはんだ付け工程など
ではんだ喰われが生じることのない外部電極を確実に形
成することが可能になる。When a plurality of thin films of different types are sequentially formed by the dry plating method to form a thin film electrode having a multi-layer structure on the varistor element body, a solder thick film electrode is formed by dipping the solder. Moreover, it becomes possible to more effectively embody the present invention by forming an external electrode that does not cause solder erosion in the soldering process during mounting. That is, for example, a NiCr thin film, a NiCu thin film, and an Ag thin film are sequentially formed on the surface of a varistor element body to form a thin film electrode having a multi-layer structure. It becomes possible to reliably form an external electrode that does not cause solder erosion during the soldering process.
【００１１】[0011]
【発明の実施の形態】以下、本発明のバリスタの外部電
極形成方法の実施形態を、図に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for forming external electrodes of a varistor according to the present invention will be described below with reference to the drawings.
【００１２】この実施形態においては、まず、図１に示
すように、セラミック１中に複数の内部電極２が配設さ
れた焼成後のバリスタ素体３の両端側の外部電極形成部
以外の部分をマスキングし（図示せず）、スパッタリン
グ法により、バリスタ素体３上にＮｉＣｒ薄膜、ＮｉＣ
ｕ薄膜、Ａｇ薄膜の順に着膜させて、膜厚が約１μmの
複層構造の薄膜電極（下層電極）４を形成した。なお、
この場合、薄膜電極４の形成方法は、スパッタリング法
に限られるものではなく、蒸着法、ＣＶＤ法などの種々
の方法を用いることが可能である。In this embodiment, first, as shown in FIG. 1, portions other than the external electrode forming portions on both ends of the varistor element body 3 after firing, in which a plurality of internal electrodes 2 are arranged in a ceramic 1. Is masked (not shown), and a NiCr thin film and a NiC thin film are formed on the varistor element body 3 by a sputtering method.
The u thin film and the Ag thin film were deposited in this order to form a thin film electrode (lower electrode) 4 having a multilayer structure with a film thickness of about 1 μm. In addition,
In this case, the method of forming the thin film electrode 4 is not limited to the sputtering method, and various methods such as a vapor deposition method and a CVD method can be used.
【００１３】次いで、バリスタ素体３の薄膜電極４が形
成された部分をロジン系のフラックスに浸漬して１５０
℃、１分間の予熱を行った後、２３０℃の溶融はんだ浴
に５秒間浸漬することにより、薄膜電極４上にはんだ厚
膜電極（上層電極）５を形成した。Next, the portion of the varistor element body 3 on which the thin film electrode 4 is formed is immersed in rosin-based flux for 150
After preheating at 1 ° C. for 1 minute, it was immersed in a molten solder bath at 230 ° C. for 5 seconds to form a solder thick film electrode (upper layer electrode) 5 on the thin film electrode 4.
【００１４】それから、薄膜電極４とはんだ厚膜電極５
とからなる外部電極６が形成されたバリスタ素体を洗浄
してバリスタ（チップ型バリスタ）を得た。Then, the thin film electrode 4 and the solder thick film electrode 5
A varistor (chip type varistor) was obtained by cleaning the varistor element body on which the external electrode 6 composed of and was formed.
【００１５】そして、上述の方法により外部電極を形成
してなるチップ型バリスタ（実施例）と、従来の方法
で、銀厚膜電極のみからなる外部電極を形成したチップ
型バリスタ（比較例）についてはんだ耐熱性試験を行っ
たところ、比較例のバリスタの外部電極には喰われが発
生し、バリスタ素体の部分的な露出が認められたが、ス
パッタリング法で形成した複層構造の薄膜電極上にはん
だ厚膜電極を形成した本発明の実施例のバリスタの場
合、電極の喰われによるバリスタ素体の露出はまったく
認められなかった。Then, a chip-type varistor in which the external electrodes are formed by the above-mentioned method (Example) and a chip-type varistor in which the external electrodes made of only the silver thick film electrodes are formed by the conventional method (Comparative example) When a solder heat resistance test was conducted, bite occurred on the external electrodes of the varistor of the comparative example, and partial exposure of the varistor element body was observed, but on the thin film electrode of the multilayer structure formed by the sputtering method. In the case of the varistor of the example of the present invention in which the solder thick film electrode was formed on the substrate, no exposure of the varistor element body due to the erosion of the electrode was observed.
【００１６】また、上記のようにして外部電極を形成し
たバリスタについて、サージ耐量を調べた。その結果を
表１に示す。なお、表１のサージ耐量の値は、８／２０
μｓ標準電流波形を５分間隔で２回印加した場合におい
て、バリスタ電圧の変化率が±１０％以内で、かつ、外
観異常の認められない電流値である。The surge resistance of the varistor having the external electrode formed as described above was examined. Table 1 shows the results. The surge withstand value in Table 1 is 8/20.
When the μs standard current waveform is applied twice at intervals of 5 minutes, the change rate of the varistor voltage is within ± 10%, and the current value has no abnormal appearance.
【００１７】[0017]
【表１】 [Table 1]
【００１８】なお、表１には、比較のため、銀−パラジ
ウムペーストを塗布、焼付けすることにより形成した厚
膜電極のみからなる外部電極を有する試料（従来例１）
と、スパッタリング法により形成したニッケル系合金−
銀薄膜電極のみからなる外部電極を有する試料（従来例
２）について測定したサージ耐量を併せて示している。In Table 1, for comparison, a sample having an external electrode composed only of a thick film electrode formed by applying and baking a silver-palladium paste (conventional example 1).
And a nickel-based alloy formed by the sputtering method
The surge withstand capability measured for the sample (conventional example 2) having the external electrode composed only of the silver thin film electrode is also shown.
【００１９】表１より、従来例２の薄膜電極のみからな
る試料では、サージ耐量が２０Ａであるのに対して、厚
膜と薄膜電極からなる外部電極を有する実施例の試料に
おいては、厚膜電極を外部電極とする従来例１と同じ
く、サージ耐量が５００Ａと、実用上十分な特性が得ら
れていることがわかる。From Table 1, it can be seen that the sample having only the thin film electrode of Conventional Example 2 has a surge withstand capability of 20 A, whereas the sample of the example having the external electrode composed of the thick film and the thin film electrode has the thick film thickness. As in the case of Conventional Example 1 in which the electrodes are external electrodes, it can be seen that the surge withstand capability is 500 A, which is a practically sufficient characteristic.
【００２０】また、上記実施形態では、薄膜電極とし
て、ＮｉＣｒ薄膜、ＮｉＣｕ薄膜、Ａｇ薄膜を順に着膜
させた複層構造を有する薄膜電極を形成した場合につい
て説明したが、薄膜電極は必ずしも複層構造としなけれ
ばならないものではなく、場合によっては単層構造とす
ることも可能である。また、薄膜電極の構成材料につい
ても特別の制約はない。In the above embodiment, the case where a thin film electrode having a multi-layer structure in which a NiCr thin film, a NiCu thin film and an Ag thin film are sequentially deposited is formed as the thin film electrode has been described. It does not have to be a structure, but may have a single layer structure in some cases. Further, there is no particular restriction on the constituent material of the thin film electrode.
【００２１】本発明は、さらにその他の点においても上
記実施形態に限定されるものではなく、発明の要旨の範
囲内において、種々の応用、変形を加えることが可能で
ある。The present invention is not limited to the above embodiment in other respects, and various applications and modifications can be made within the scope of the invention.
【００２２】[0022]
【発明の効果】上述のように、本発明のバリスタの外部
電極形成方法は、バリスタ素体の所定の位置に乾式メッ
キ法により薄膜電極を形成した後、その上に、はんだ浸
漬法によりはんだ厚膜電極を形成するようにしているの
で、はんだ厚膜電極により、薄膜電極だけでは不十分で
ある耐サージ性を改善することが可能になるとともに、
薄膜電極により優れたはんだ付性やはんだ耐熱性を確保
することが可能になる。したがって、本発明の方法によ
れば、バリスタ素体を劣化させることなく、はんだ付
性、はんだ耐熱性が良好で、しかもサージ耐量に優れた
外部電極を形成することができる。As described above, according to the method of forming external electrodes of a varistor of the present invention, a thin film electrode is formed at a predetermined position of a varistor element body by a dry plating method, and then a solder thickness is formed by a solder dipping method. Since the film electrode is formed, the solder thick film electrode makes it possible to improve the surge resistance, which is insufficient with the thin film electrode alone.
The thin-film electrode makes it possible to ensure excellent solderability and solder heat resistance. Therefore, according to the method of the present invention, it is possible to form an external electrode having good solderability and solder heat resistance and excellent surge resistance without deteriorating the varistor element body.
【００２３】また、前記乾式メッキ法により種類の異な
る複数の薄膜を順次成膜して、バリスタ素体上に複層構
造の薄膜電極を形成することにより、はんだ浸漬による
はんだ厚膜電極の形成時、及び実装時のはんだ付け工程
ではんだ喰われが生じることのない外部電極を形成し
て、本発明をより実効あらしめることが可能になる。す
なわち、例えば、バリスタ素体の表面にＡｇ薄膜電極を
形成し、その上に、さらに、ＮｉＣｒ薄膜、ＮｉＣｕ薄
膜、Ａｇ薄膜などを順次成膜して複層構造の薄膜電極を
形成することにより、はんだ浸漬法によるはんだ厚膜電
極の形成時や実装時のはんだ付け工程などではんだ喰わ
れが生じることのない外部電極を確実に形成することが
可能になる。When a plurality of thin films of different types are sequentially formed by the dry plating method to form a thin film electrode having a multi-layer structure on the varistor element body, a solder thick film electrode is formed by dipping the solder. Moreover, it becomes possible to more effectively embody the present invention by forming an external electrode that does not cause solder erosion in the soldering process during mounting. That is, for example, by forming an Ag thin film electrode on the surface of a varistor element body, and then further forming a NiCr thin film, a NiCu thin film, an Ag thin film, etc. in that order to form a multi-layered thin film electrode, It becomes possible to reliably form an external electrode that does not cause solder erosion during the soldering process such as when forming a solder thick film electrode by the solder dipping method or during mounting.
【図１】本発明のバリスタの外部電極形成方法の一実施
形態を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a method for forming an external electrode of a varistor according to the present invention.
【図２】本発明のバリスタの外部電極形成方法により製
造されたバリスタを示す断面図である。FIG. 2 is a cross-sectional view showing a varistor manufactured by the method for forming external electrodes of a varistor of the present invention.
１ セラミック ２ 内部電極 ３ バリスタ素体 ４ 薄膜電極（下層電極） ５ 厚膜電極（上層電極） ６ 外部電極 1 Ceramic 2 Internal Electrode 3 Varistor Element 4 Thin Film Electrode (Lower Layer Electrode) 5 Thick Film Electrode (Upper Layer Electrode) 6 External Electrode
Claims (2)
キ法により薄膜電極を形成する薄膜電極形成工程と、 前記薄膜電極形成工程において形成された薄膜電極上
に、はんだ浸漬法によりはんだ厚膜電極を形成するはん
だ厚膜電極形成工程とを具備することを特徴とするバリ
スタの外部電極形成方法。1. A thin film electrode forming step of forming a thin film electrode on a predetermined position of a varistor element body by a dry plating method, and a solder thick film by a solder dipping method on the thin film electrode formed in the thin film electrode forming step. A method of forming an external electrode of a varistor, comprising: a solder thick film electrode forming step of forming an electrode.
薄膜を順次成膜して、複層構造の薄膜電極を形成するこ
とを特徴とする請求項１記載のバリスタの外部電極形成
方法。2. The method for forming an external electrode of a varistor according to claim 1, wherein a plurality of thin films of different types are sequentially formed by a dry plating method to form a thin film electrode having a multi-layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7306872A JPH09129417A (en) | 1995-10-30 | 1995-10-30 | Forming method of varistor outer electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7306872A JPH09129417A (en) | 1995-10-30 | 1995-10-30 | Forming method of varistor outer electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09129417A true JPH09129417A (en) | 1997-05-16 |
Family
ID=17962267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7306872A Pending JPH09129417A (en) | 1995-10-30 | 1995-10-30 | Forming method of varistor outer electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09129417A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007118472A1 (en) * | 2006-04-18 | 2007-10-25 | Epcos Ag | Electrical ptc thermistor component, and method for the production thereof |
-
1995
- 1995-10-30 JP JP7306872A patent/JPH09129417A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007118472A1 (en) * | 2006-04-18 | 2007-10-25 | Epcos Ag | Electrical ptc thermistor component, and method for the production thereof |
| US8154379B2 (en) | 2006-04-18 | 2012-04-10 | Epcos Ag | Electrical PTC thermistor component, and method for the production thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH06163306A (en) | Electronic component | |
| JPS58178903A (en) | Conductive paste | |
| JPH09129417A (en) | Forming method of varistor outer electrode | |
| JPH08138969A (en) | Manufacture of electronic component | |
| JPH0878279A (en) | Formation of outer electrode on electronic chip device | |
| JPH0722268A (en) | Chip device | |
| JPH0897075A (en) | Production of ceramic device | |
| JPH09120909A (en) | Method of forming external electrode of varistor | |
| JP2000077253A (en) | Electronic component, electronic component chip, and component manufacturing method | |
| JPH04293214A (en) | Conductive paste for chip type electronic component | |
| JP2003243245A (en) | Ceramic electronic component and its manufacturing method | |
| JP3772270B2 (en) | Small electronic component manufacturing method and chip resistor | |
| JP3031026B2 (en) | Manufacturing method of chip-type ceramic electronic component | |
| JP5000912B2 (en) | Chip varistor | |
| JPH02294007A (en) | Formation of ceramic electronic component electrode | |
| JPH08111349A (en) | Chip component | |
| JP4556337B2 (en) | Manufacturing method of multilayer ceramic electronic component | |
| JP2976048B2 (en) | Manufacturing method of chip-type ceramic electronic component | |
| JP2000021607A (en) | Manufacture of chip thermistor | |
| JPH04188801A (en) | Chip type positive temperature coefficient thermistor | |
| JP3019567B2 (en) | Manufacturing method of chip-type ceramic electronic component | |
| JPH07335487A (en) | Electronic part and method of manufacturing the same | |
| JPH04329616A (en) | Laminated type electronic component | |
| JP2003147573A (en) | Method of manufacturing electronic parts and electronic parts | |
| JP3031025B2 (en) | Manufacturing method of chip-type ceramic electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20020820 |