JPH09116177A - Method for forming compound semiconductor film and method for manufacturing thin film solar cell - Google Patents
Method for forming compound semiconductor film and method for manufacturing thin film solar cellInfo
- Publication number
- JPH09116177A JPH09116177A JP7270864A JP27086495A JPH09116177A JP H09116177 A JPH09116177 A JP H09116177A JP 7270864 A JP7270864 A JP 7270864A JP 27086495 A JP27086495 A JP 27086495A JP H09116177 A JPH09116177 A JP H09116177A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- indium
- copper
- solar cell
- selenium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/541—CuInSe2 material PV cells
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- Photovoltaic Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】
【課題】 スパッタリング装置などの高価な装置を必要
とせず、端部まで結晶が発達し、かつ、厚さ斑や短絡等
の欠点のない優れた銅−インジウム−セレン三元合金か
らなる化合物半導体膜の形成方法を提供する。
【解決手段】 銅及びインジウムの薄膜をそれぞれ化学
メッキ法によって形成し、その後、セレンを含む雰囲気
中で熱処理を行う。(57) Abstract: An excellent copper-indium-selenium ternary element that does not require expensive equipment such as a sputtering apparatus, has crystals developed to the end, and has no defects such as thickness unevenness or short circuit. A method for forming a compound semiconductor film made of an alloy is provided. Thin films of copper and indium are formed by a chemical plating method, respectively, and then heat treatment is performed in an atmosphere containing selenium.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、太陽電池の吸収層
等に用いられる化合物半導体膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a compound semiconductor film used for an absorption layer of a solar cell.
【0002】[0002]
【従来の技術】太陽電池は、光エネルギーを電気エネル
ギーに変換する装置であり、最初は単結晶シリコンが用
いられていたが、この単結晶シリコンでは大面積の太陽
電池の作成が困難で、かつ、コストも高いものとなるの
で、最近は非晶質シリコンや化合物半導体が用いられる
ようになってきた。2. Description of the Related Art A solar cell is a device for converting light energy into electric energy, and initially single crystal silicon was used. However, it is difficult to make a large area solar cell with this single crystal silicon, and However, since the cost becomes high, amorphous silicon and compound semiconductors have been used recently.
【0003】化合物半導体のうちでも、銅−インジウム
−セレン三元合金が優れた光電変換効率を有するものと
され、これを用いれば低コストで大面積の太陽電池が可
能となると期待されている。ここで、銅−インジウム−
セレン三元合金については、特開昭61−237476
号公報、特開平1−231313号公報など多くの提案
がなされている。Among the compound semiconductors, a copper-indium-selenium ternary alloy is considered to have excellent photoelectric conversion efficiency, and it is expected that a large-area solar cell can be realized at low cost by using it. Where copper-indium-
Regarding the selenium ternary alloy, JP-A-61-237476
Many proposals have been made such as Japanese Patent Publication No. Hei 1-231313.
【0004】これら従来技術は、基板上に銅、インジウ
ムを電着させ、セレン化水素中で熱処理を行って、銅−
インジウム−セレン三元合金層を形成し、プリカーサー
とするものであった。しかし、このような電着法を用い
た場合、電着面に対する電流密度を斑なく一定とするこ
とが困難であった。特に基板の端部では電流集中が生じ
て厚さ斑が著しい。In these conventional techniques, copper and indium are electrodeposited on a substrate and heat-treated in hydrogen selenide to form copper-
An indium-selenium ternary alloy layer was formed and used as a precursor. However, when such an electrodeposition method is used, it has been difficult to make the current density on the electrodeposition surface uniform. In particular, current concentration occurs at the edges of the substrate, resulting in significant thickness unevenness.
【0005】即ち、図10に厚さ斑を示すモデル(断面
図)を示す。この図において、符号1’は基板、符号
2’はモリブデンからなる導電層であり、その上に銅層
3及びインジウム層4が電着によって形成されている
が、図のように電着によって形成された銅層3及びイン
ジウム層4の端部の厚さが厚くなってしまう。That is, FIG. 10 shows a model (cross-sectional view) showing unevenness in thickness. In this figure, reference numeral 1'is a substrate, reference numeral 2'is a conductive layer made of molybdenum, and a copper layer 3 and an indium layer 4 are formed thereon by electrodeposition, but as shown in the figure, they are formed by electrodeposition. The thickness of the end portions of the removed copper layer 3 and indium layer 4 becomes large.
【0006】このような厚さ斑が大きいプリカーサーを
セレンを含む雰囲気下で熱処理を行うと、得られる化合
物半導体層に厚さ斑が生じ、ひびや剥離の原因となる
が、それ以外に化合物の組成が端部のみならず中央部も
含めて不均一となって三元合金の結晶発達を妨げて光電
変換効率を低下させたり、或いは、短絡を生じるため製
品歩留まりの低下を引き起こす。When the precursor having such a large thickness unevenness is heat-treated in an atmosphere containing selenium, thickness unevenness occurs in the obtained compound semiconductor layer, which causes cracks and peeling. The composition becomes non-uniform not only in the end portion but also in the central portion, which hinders the crystal growth of the ternary alloy to lower the photoelectric conversion efficiency, or causes a short circuit, which causes a reduction in product yield.
【0007】これら欠陥部は端部に集中して生じるた
め、大面積の単モジュールの太陽電池を形成する場合に
は無視できることもあるが、限られた大きさの基板上に
複数のモジュールを形成してこれを直列に接続する場合
などの、1つのモジュールの大きさが小さくなる場合に
は、相対的に欠陥部の影響が増加してしまうため、大き
な問題となる。Since these defective portions are concentrated on the edges, they may be ignored when forming a large-area single-module solar cell, but a plurality of modules are formed on a substrate of a limited size. Then, when the size of one module is reduced, for example, when these are connected in series, the influence of the defective portion relatively increases, which is a serious problem.
【0008】また、このように1つの基板上に複数個の
モジュールを形成する場合、従来法では、まず基板上に
それぞれのモジュールに対応する導電層(図10におい
てはモリブデン薄膜)を複数形成し、これら導電層をそ
れぞれ電極としてこれら導電層の上に電気メッキを行っ
て銅層、インジウム層等を順次形成していくが、このと
き導電層すべてがそれぞれ陰極として電源に接続してい
なければならない。この電気的接続のために基板上のモ
ジュールの配置の自由度、すなわちモジュールの設計の
自由度が制限されると云う欠点があった。Further, in the case of forming a plurality of modules on one substrate as described above, in the conventional method, first, a plurality of conductive layers (molybdenum thin films in FIG. 10) corresponding to the respective modules are formed on the substrate. , Using these conductive layers as electrodes to perform electroplating on these conductive layers to sequentially form copper layers, indium layers, etc. At this time, all of the conductive layers must be connected to the power source as cathodes. . This electrical connection has a drawback in that the degree of freedom in arranging the module on the substrate, that is, the degree of freedom in designing the module is limited.
【0009】一方、スパッタリング等の真空応用技術に
おいては、上記のような厚さ斑による欠陥を生じること
は少ないが、これら方法によって製膜を行うためには、
真空容器等の高価な設備を必要とするとともに、これら
方法は処理効率が悪いため、高コストの原因となってし
まう。On the other hand, in vacuum application techniques such as sputtering, defects due to the thickness unevenness described above are rarely generated, but in order to perform film formation by these methods,
In addition to requiring expensive equipment such as a vacuum container, these methods have poor processing efficiency, which causes high cost.
【0010】[0010]
【発明が解決しようとする課題】本発明は従来技術の上
記問題点を解決する、すなわち、スパッタリング装置な
どの高価な装置を必要とせず、端部まで結晶が発達し、
かつ、厚さ斑や短絡、ひび、剥離等の欠点のない優れた
銅−インジウム−セレン三元合金からなる化合物半導体
膜の形成方法を提供する。SUMMARY OF THE INVENTION The present invention solves the above problems of the prior art, that is, it does not require an expensive apparatus such as a sputtering apparatus, and the crystal develops to the end,
Further, there is provided a method for forming a compound semiconductor film made of an excellent copper-indium-selenium ternary alloy, which is free from defects such as thickness unevenness, short circuit, cracking, and peeling.
【0011】[0011]
【課題を解決するための手段】本発明の化合物半導体膜
の形成方法は請求項1に記載のように、銅及びインジウ
ムの薄膜をそれぞれ化学メッキ法によって形成し、その
後、セレンを含む雰囲気中で熱処理を行う構成を有す
る。また、本発明の薄膜太陽電池の製造方法は請求項2
に記載のように、導電性基板上に、銅及びインジウムの
薄膜を化学メッキ法によって形成し、その後、セレンを
含む雰囲気中で熱処理を行う構成を有する。According to the method of forming a compound semiconductor film of the present invention, as described in claim 1, thin films of copper and indium are respectively formed by a chemical plating method, and thereafter, in an atmosphere containing selenium. It has a configuration for performing heat treatment. The method for producing a thin-film solar cell according to the present invention is claim 2.
As described in 1), a thin film of copper and indium is formed on a conductive substrate by a chemical plating method, and then heat treatment is performed in an atmosphere containing selenium.
【0012】[0012]
【発明の実施の態様】導電性基板上に化学メッキによっ
て銅及びインジウムの薄膜を形成して得たプリカーサー
を、セレンを含む雰囲気下で熱処理を行ってCuInS
e2 三元合金層を得る。ここで上記プリカーサーは、導
電性基板/銅層/インジウム層の順に形成されていて
も、或いは、導電性基板/インジウム層/銅層の順に形
成されていても良い。また導電性基板上に銅−インジウ
ム合金が形成されていても良い。BEST MODE FOR CARRYING OUT THE INVENTION A precursor obtained by forming a thin film of copper and indium on a conductive substrate by chemical plating is heat-treated in an atmosphere containing selenium to form CuInS.
e 2 Obtain a ternary alloy layer. Here, the precursor may be formed in the order of conductive substrate / copper layer / indium layer, or may be formed in the order of conductive substrate / indium layer / copper layer. Further, a copper-indium alloy may be formed on the conductive substrate.
【0013】また、セレンを含む雰囲気とは、セレン化
水素、セレン蒸気を含む不活性気体等が挙げられる。た
だし、セレン化水素は非常に毒性が強いため、セレン蒸
気を用いることが望ましい。セレン蒸気は、プリカーサ
ーを熱処理する容器中に固体のセレンを同時に封入する
ことで得ることができる。一方、熱処理は350〜50
0℃で行うことができる。ここで400℃以上500℃
以下での温度で熱処理を行うと、特に高効率の太陽電池
を得ることができるので望ましい。Examples of the atmosphere containing selenium include hydrogen selenide and an inert gas containing selenium vapor. However, since hydrogen selenide is extremely toxic, it is desirable to use selenium vapor. Selenium vapor can be obtained by simultaneously encapsulating solid selenium in a vessel for heat treating the precursor. On the other hand, heat treatment is 350-50
It can be carried out at 0 ° C. Here, 400 ° C or more and 500 ° C
It is desirable to perform the heat treatment at the following temperature because a highly efficient solar cell can be obtained.
【0014】[0014]
[実施例1] 〔銅メッキ液の調製〕まず、メッキ液の調製を行った。
表1に銅メッキ液の組成を示す。すなわち表1に示した
各薬品を溶解し、pHを12.6になるよう水酸化ナト
リウムを添加しメッキ液とした。なお、使用に際しては
液温を69℃に保った。[Example 1] [Preparation of copper plating solution] First, a plating solution was prepared.
Table 1 shows the composition of the copper plating solution. That is, each chemical shown in Table 1 was dissolved and sodium hydroxide was added to adjust the pH to 12.6 to obtain a plating solution. The liquid temperature was kept at 69 ° C. during use.
【0015】[0015]
【表1】 [Table 1]
【0016】〔インジウムメッキ液の調製〕一方、イン
ジウムメッキ液の組成を表2に示す。すなわちこのよう
な組成になるよう各薬剤を溶解し、これに水酸化ナトリ
ウムを添加してpHを10.0とした。なお、使用に際
してはこのインジウムメッキ液の液温を80℃に保っ
た。[Preparation of Indium Plating Solution] On the other hand, Table 2 shows the composition of the indium plating solution. That is, each drug was dissolved to have such a composition, and sodium hydroxide was added thereto to adjust the pH to 10.0. The liquid temperature of the indium plating solution was kept at 80 ° C. during use.
【0017】[0017]
【表2】 [Table 2]
【0018】〔プリカーサーの作製〕ソーダライムガラ
ス上に導電性層として2μmのモリブデン層をスパッタ
リング法によって形成し、導電性基板とした。この導電
性基板を上記銅メッキ液に12分間浸漬したところ、モ
リブデン層上に銅層が、中央部、端部ともに0.3μm
の厚さに形成された。なお、モリブデン層のない部分
(ソーダライムガラス部)にはメッキ層は形成されなか
った。[Preparation of Precursor] A 2 μm molybdenum layer was formed as a conductive layer on soda lime glass by a sputtering method to obtain a conductive substrate. When this conductive substrate was dipped in the above copper plating solution for 12 minutes, a copper layer on the molybdenum layer was 0.3 μm in both the central portion and the end portion.
Formed to a thickness of No plating layer was formed on the portion without the molybdenum layer (soda lime glass portion).
【0019】次いで、インジウムメッキを行った。上記
銅メッキを施した導電性基板を前述のインジウムメッキ
液中に20分間浸漬したところ、中央部0.67μm、
端部0.65μmの厚さ(蛍光X線膜厚計による)のイ
ンジウム層が形成された(このものを以下「プリカーサ
ーA」と云う)。このときも、ソーダライムガラス部に
はメッキ層は形成されなかった。なお、これらメッキ工
程前後の重量変化より、各メッキ層中の銅元素の量とイ
ンジウム元素の量とは1.01:1であることが判っ
た。Then, indium plating was performed. When the copper-plated conductive substrate was immersed in the indium plating solution described above for 20 minutes, the central portion had a thickness of 0.67 μm.
An indium layer having a thickness of 0.65 μm (according to a fluorescent X-ray film thickness meter) was formed at the edge (hereinafter referred to as “precursor A”). At this time, no plating layer was formed on the soda lime glass portion. From the weight change before and after the plating process, it was found that the amount of copper element and the amount of indium element in each plating layer were 1.01: 1.
【0020】〔熱処理〕上記プリカーサーAをセレン粉
末とともに密閉容器に封入し、25℃/分の昇温速度で
450℃まで昇温し、1時間保った。その後、室温まで
自然冷却させて、銅−セレン−インジウム三元合金層を
得た。この合金層の外観は全体に良好で、厚さ斑、ひび
或いは剥離等の欠陥もなかった。この合金層端部と中央
部についてX線回折分析を行ったところ、ともに良く発
達し配向したCuInSe2 のカルコパイライト型結晶
が存在することが確認された。[Heat Treatment] The precursor A was enclosed in a closed container together with selenium powder, heated to 450 ° C. at a heating rate of 25 ° C./min, and kept for 1 hour. Then, it was naturally cooled to room temperature to obtain a copper-selenium-indium ternary alloy layer. The appearance of this alloy layer was good on the whole, and there were no defects such as thickness unevenness, cracks or peeling. When X-ray diffraction analysis was performed on the edge portion and the center portion of the alloy layer, it was confirmed that there existed well-developed and oriented CuInSe 2 chalcopyrite type crystals.
【0021】[比較例]実施例1で用いたのと同様のモ
リブデン膜を有するソーダライムガラスを用い、これを
正極とし、白金板を陰極として、硫酸酸性の硫酸銅水溶
液(0.5mol/ l)を用いて電気メッキを行った。こ
のとき、得られた銅層の厚さは、中央部が0.31μm
で、端部は0.78μmであった。COMPARATIVE EXAMPLE A soda lime glass having a molybdenum film similar to that used in Example 1 was used as a positive electrode and a platinum plate as a cathode, and a sulfuric acid-acidified copper sulfate aqueous solution (0.5 mol / l) was used. ) Was used for electroplating. At this time, the thickness of the obtained copper layer is 0.31 μm at the central portion.
The edge was 0.78 μm.
【0022】次いで、この銅膜上に、スルファミン酸イ
ンジウム水溶液を用いてインジウムメッキを行った。得
られたインジウム層の厚さは、中央部0.67μm、端
部では1.41μmであった(このものを以下「プリカ
ーサーB」と云う)。このプリカーサーBを実施例1と
同様にセレン雰囲気下で熱処理を行った。Next, indium plating was performed on this copper film using an indium sulfamate aqueous solution. The thickness of the obtained indium layer was 0.67 μm at the center and 1.41 μm at the edges (this is hereinafter referred to as “precursor B”). This precursor B was heat-treated in the same selenium atmosphere as in Example 1.
【0023】得られた三元合金層の端部には小さなひび
が多数存在し、一部剥離している部分もあった。また、
X線回折分析を行ったところ、中央部には実施例1と同
様に良好なCuInSe2 の結晶が存在することが確認
されたが、端部においてはその回折強度は中央部の60
%であり、満足できないものであることが判った。There were many small cracks at the end of the obtained ternary alloy layer, and there was a part where it was peeled off. Also,
As a result of X-ray diffraction analysis, it was confirmed that good CuInSe 2 crystals were present in the central portion as in Example 1, but the diffraction intensity at the end portions was 60 at the central portion.
%, Which was found to be unsatisfactory.
【0024】[実施例2]実施例2として、1つの基板
上に複数のモジュールを形成する過程を図1至図9のモ
デル図を用いて説明する。図1は、2μmのモリブデン
層(図中符号2)を形成したソーダライムガラス(図中
符号1)の断面図である。[Embodiment 2] As Embodiment 2, a process of forming a plurality of modules on one substrate will be described with reference to the model diagrams of FIGS. 1 to 9. FIG. 1 is a cross-sectional view of soda lime glass (reference numeral 1 in the figure) on which a 2 μm molybdenum layer (reference numeral 2 in the figure) is formed.
【0025】このものを図2に示すように上記モリブデ
ン層2をレーザスクライブ法によりパターンニングして
短冊状の金属電極2a 、2b に分割した。次いで実施例
1で行ったのと同様に、銅メッキ及びインジウムメッキ
を行い、銅層3a 及び3b と、インジウム層4a 及び4
b とを形成して図3に示すようなプリカーサーCを得
た。なお、各メッキ工程でのメッキ層の厚さ斑について
実施例1と同様に調査したが、中央部−端部間での厚さ
斑はなく良好なメッキ層であることが判った。As shown in FIG. 2, the molybdenum layer 2 was patterned by a laser scribing method to divide it into strip-shaped metal electrodes 2a and 2b. Then, in the same manner as in Example 1, copper plating and indium plating are performed to form copper layers 3a and 3b and indium layers 4a and 4a.
b was formed to obtain a precursor C as shown in FIG. In addition, the thickness unevenness of the plating layer in each plating step was investigated in the same manner as in Example 1, but it was found that there was no thickness unevenness between the central portion and the end portion, and the plating layer was good.
【0026】ここで、これらメッキ過程において、通常
ソーダライムガラス上にはメッキ層は形成されないが、
ガラス表面が特に凸凹が多い場合などメッキ層が形成さ
れるおそれがある場合には、メッキ不要箇所にはシリコ
ンゴム等を密着させてメッキ層形成を防ぐ等の手段を講
ずる。Here, in these plating processes, a plating layer is not usually formed on soda lime glass,
When a plating layer is likely to be formed, for example, when the glass surface has a large number of irregularities, measures such as preventing the plating layer from being formed by adhering silicon rubber or the like to places where plating is unnecessary are taken.
【0027】上記のようにして得られたプリカーサーC
を、実施例1と同様にセレン化を行い、銅−インジウム
−セレン三元合金層5a 及び5b (図4参照)を得た。
この三元合金層は、良好で、ひびや剥離等はなく、ま
た、その中央部及び端部でのX線回折結果も共に満足で
きるものであった。Precursor C obtained as described above
Was selenized in the same manner as in Example 1 to obtain copper-indium-selenium ternary alloy layers 5a and 5b (see FIG. 4).
This ternary alloy layer was good, free from cracks, peeling, and the like, and the X-ray diffraction results at the central portion and the end portion were both satisfactory.
【0028】p型半導体である上記三元合金層上にn型
半導体である硫化カドミウム層(図5中符号6a 及び6
b )を液相成長法によって形成した。すなわち70℃の
硫酸カドミウム(CdSO4 )0.01mol / l水溶液
(アンモニア水でpHを8.5に調製したもの)に、上
記の薄膜層を形成したソーダライムガラスを5分間浸漬
し、その後、チオ尿素0.01mol / l水溶液を添加し
5分間保持して硫化カドミウム層6a 及び6b を成長さ
せた。このとき不要部分にシリコンゴムを密着させて硫
化カドミウム層の形成を防いだ。On the ternary alloy layer which is a p-type semiconductor, a cadmium sulfide layer which is an n-type semiconductor (reference numerals 6a and 6 in FIG. 5).
b) was formed by liquid phase epitaxy. That is, the soda lime glass having the thin film layer formed thereon was dipped in a 0.01 mol / l aqueous solution of cadmium sulfate (CdSO 4 ) at 70 ° C. (pH adjusted to 8.5 with ammonia water) for 5 minutes, and then, An aqueous solution of 0.01 mol / l thiourea was added and kept for 5 minutes to grow cadmium sulfide layers 6a and 6b. At this time, silicon rubber was adhered to unnecessary portions to prevent the formation of the cadmium sulfide layer.
【0029】次いでレーザスクライブ法を応用してビー
ム強度を調整しながら、図6に示すようにこの硫化カド
ミウム層及び三元合金層の一部を除去した。その後、透
明電極層(図7中符号7)として2重量%のアルミニウ
ムをドープさせた酸化亜鉛の2μm厚の薄膜をスパッタ
リングにて形成した後、再度ビーム強度を調整してレー
ザスクライブ法によって図8に示すように、この酸化亜
鉛層の一部を削除し、最終的に図9に示すようにリード
線8を付けて、直列接続された複数モジュールからなる
太陽電池ユニットを得た。Then, while adjusting the beam intensity by applying the laser scribing method, the cadmium sulfide layer and a part of the ternary alloy layer were removed as shown in FIG. Then, a 2 μm thick thin film of zinc oxide doped with 2% by weight of aluminum was formed by sputtering as a transparent electrode layer (reference numeral 7 in FIG. 7), and then the beam intensity was adjusted again and a laser scribing method was performed as shown in FIG. As shown in FIG. 5, a part of this zinc oxide layer was removed, and finally a lead wire 8 was attached as shown in FIG. 9 to obtain a solar cell unit composed of a plurality of modules connected in series.
【0030】以上のように本発明に係る薄膜太陽電池の
製造方法によると、実施例2で明らかになったようにメ
ッキ工程における導電層の電気的接続が不要であるた
め、1つの基板上に複数の太陽電池モジュールを形成す
る場合の、モジュールの配置の自由度が非常に高いこと
が理解される。As described above, according to the method for manufacturing a thin-film solar cell of the present invention, it is not necessary to electrically connect the conductive layers in the plating process as is apparent from the second embodiment. It is understood that, when forming a plurality of solar cell modules, the degree of freedom in arranging the modules is very high.
【0031】[0031]
【発明の効果】上記実施例及び比較例より明らかなよう
に、本発明によれば、高価な装置を必要とせずに、中央
部はもちろん端部まで均一で良好な銅−インジウム−セ
レン三元合金層を効率よく得ることができる。また、1
つの基板上に複数の太陽電池モジュールを形成する場合
の設計の自由度が非常に高い。As is apparent from the above-mentioned examples and comparative examples, according to the present invention, a good copper-indium-selenium ternary material is obtained, which is uniform and not only in the central portion but also in the end portions without requiring an expensive device. The alloy layer can be efficiently obtained. Also, 1
The flexibility of design is extremely high when a plurality of solar cell modules are formed on one substrate.
【図1】太陽電池ユニットを製造する中間工程(ソーダ
ライムガラス上にモリブデン層を形成した状態)を表す
図である。FIG. 1 is a diagram showing an intermediate step of manufacturing a solar cell unit (a state in which a molybdenum layer is formed on soda lime glass).
【図2】太陽電池ユニットを製造する中間工程(モリブ
デン層を短冊状に切断した状態)を表す図である。FIG. 2 is a diagram illustrating an intermediate step of manufacturing a solar cell unit (a state in which a molybdenum layer is cut into strips).
【図3】太陽電池ユニットを製造する中間工程(モリブ
デン層上に銅層及びインジウム層を形成した状態(プリ
カーサーC))を表す図である。FIG. 3 is a diagram illustrating an intermediate step of manufacturing a solar cell unit (a state in which a copper layer and an indium layer are formed on a molybdenum layer (precursor C)).
【図4】太陽電池ユニットを製造する中間工程(銅−イ
ンジウム−セレン三元合金層を形成した状態)を表す図
である。FIG. 4 is a diagram illustrating an intermediate step of manufacturing a solar cell unit (a state in which a copper-indium-selenium ternary alloy layer is formed).
【図5】太陽電池ユニットを製造する中間工程(硫化カ
ドミウム層を形成した状態)を表す図である。FIG. 5 is a diagram illustrating an intermediate step (a state in which a cadmium sulfide layer is formed) for manufacturing a solar cell unit.
【図6】太陽電池ユニットを製造する中間工程(硫化カ
ドミウム層及び三元合金層の一部をパターニングした状
態)を表す図である。FIG. 6 is a diagram showing an intermediate step of manufacturing a solar cell unit (a state in which a part of a cadmium sulfide layer and a ternary alloy layer are patterned).
【図7】太陽電池ユニットを製造する中間工程(酸化亜
鉛層を形成した状態)を表す図である。FIG. 7 is a diagram illustrating an intermediate step (a state in which a zinc oxide layer is formed) for manufacturing a solar cell unit.
【図8】太陽電池ユニットを製造する中間工程(酸化亜
鉛相の一部をパターニングした状態)を表す図である。FIG. 8 is a diagram illustrating an intermediate step of manufacturing a solar cell unit (a state in which a part of a zinc oxide phase is patterned).
【図9】太陽電池ユニットを製造する中間工程(リード
線を接続した状態)を表す図である。FIG. 9 is a diagram illustrating an intermediate step (a state in which lead wires are connected) for manufacturing a solar cell unit.
【図10】従来の技術により基板の導電層上に形成され
た銅層及びインジウム層の状態をモデル的に示す断面図
である。FIG. 10 is a cross-sectional view schematically showing a state of a copper layer and an indium layer formed on a conductive layer of a substrate by a conventional technique.
1 ソーダライムガラス 2 モリブデン層 2a 、2b 短冊状のモリブデン層 3a 、3b 銅層 4a 、4b インジウム層 5a、5b 銅−インジウム−セレン三元合金層 6a 、6b 硫化カドミウム層 7 酸化亜鉛層 8 リード線 1 Soda lime glass 2 Molybdenum layer 2a, 2b Strip-shaped molybdenum layer 3a, 3b Copper layer 4a, 4b Indium layer 5a, 5b Copper-indium-selenium ternary alloy layer 6a, 6b Cadmium sulfide layer 7 Zinc oxide layer 8 Lead wire
Claims (2)
メッキ法によって形成し、その後、セレンを含む雰囲気
中で熱処理を行うことを特徴とする化合物半導体膜の形
成方法。1. A method for forming a compound semiconductor film, which comprises forming thin films of copper and indium by a chemical plating method and then performing heat treatment in an atmosphere containing selenium.
膜を化学メッキ法によって形成し、その後、セレンを含
む雰囲気中で熱処理を行うことを特徴とする薄膜太陽電
池の製造方法。2. A method for manufacturing a thin film solar cell, which comprises forming a thin film of copper and indium on a conductive substrate by a chemical plating method, and then performing a heat treatment in an atmosphere containing selenium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7270864A JPH09116177A (en) | 1995-10-19 | 1995-10-19 | Method for forming compound semiconductor film and method for manufacturing thin film solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7270864A JPH09116177A (en) | 1995-10-19 | 1995-10-19 | Method for forming compound semiconductor film and method for manufacturing thin film solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09116177A true JPH09116177A (en) | 1997-05-02 |
Family
ID=17492044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7270864A Withdrawn JPH09116177A (en) | 1995-10-19 | 1995-10-19 | Method for forming compound semiconductor film and method for manufacturing thin film solar cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09116177A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006202919A (en) * | 2005-01-19 | 2006-08-03 | Shinko Electric Ind Co Ltd | Solar cell module manufacturing method and solar cell module |
| WO2007004501A1 (en) * | 2005-07-01 | 2007-01-11 | Honda Motor Co., Ltd. | Solar cell module |
| KR100853197B1 (en) * | 2007-03-13 | 2008-08-20 | 한국전자통신연구원 | -type CIs and n-type CIS thin film manufacturing method |
-
1995
- 1995-10-19 JP JP7270864A patent/JPH09116177A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006202919A (en) * | 2005-01-19 | 2006-08-03 | Shinko Electric Ind Co Ltd | Solar cell module manufacturing method and solar cell module |
| WO2007004501A1 (en) * | 2005-07-01 | 2007-01-11 | Honda Motor Co., Ltd. | Solar cell module |
| KR100853197B1 (en) * | 2007-03-13 | 2008-08-20 | 한국전자통신연구원 | -type CIs and n-type CIS thin film manufacturing method |
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