JPH09105906A - Power source circuit for liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold an output current to a constant value and also to eliminate the adjusting of a circuit with respect to the variation of a source driver IC becoming a load and the change of ambient temps, etc. SOLUTION: At least either the output current Ip of a positive power source output terminal OUT+ or the output current In of a negative power source output terminal OUT- is made to have a constant-current characteristic. Moreover, a source driver has the characteristic of Ip =In . In the case a source driver IC has input terminals of control voltages (a voltage for controlling the magnitude of the output current of a source driver by controlling magnitudes of input currents of the positive and negative sources of a source driver), a control voltage Vr is automatically controlled so that at least either the output current Ip or the output current In becomes a prescribed value. In the figure A, when In is increased. I2 is decreased to lower a voltage Vr and then In decreases. Moreover, In is decreased, I2 is increased to raise Vr and then In increses and thus In is held at a constant value almost equal to Vbe /R1 . Further, C1 is a capacitor for oscillation prevention. Furthermore, resistor for base current limitation may be inserted at a base input terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT (thin film transistor) switch matrix liquid crystal display element (hereinafter referred to as LC
D) source driver (also referred to as a source bus driver or signal electrode driver) for supplying positive and negative operating power supplies, and in particular, an output current of the source driver caused by manufacturing variations of the source driver (IC) This relates to a technique for suppressing the variation of (load current).

[0002]

2. Description of the Related Art As shown in FIG. 2, in an LCD 1 of this type, a source bus 1a and a gate bus 1b are arranged in rows and columns, and a TFT 1c is formed near the intersection of the source bus 1a and the source bus 1a. Each of them is connected to the gate bus 1b, and the drain thereof is the display electrode 1d.
Connected to. The display electrode 1d faces a common electrode (not shown) through the liquid crystal, and a capacitance is formed between the two.

The source bus 1a and the gate bus 1b are composed of a plurality of source driver ICs 2 and a gate bus driver IC3.
, Respectively. Multiple source driver ICs
2 is driven by a positive power supply 5 and a negative power supply 6 via a common power supply circuit 4. The source driver IC 2 has a power supply circuit 4
A control voltage V _r divided by a potentiometer 4a (both ends of which are connected to a positive power source 5 and a negative power source 6) provided therein is supplied. The magnitude of the control voltage V _r sets the approximate values of the positive and negative input currents I ₊ , I ₋ of each source driver 2a in the source driver IC2 and the output current I _L for the source bus 1a.

An example of the source driver 2a is shown in FIG.
The output stage OS is a FET transistor Q _Five~ Q₈Consists of
You. Output enable / disable signal CS₁Becomes H (high level)
And transistor Q_Five, Q₈L (low level) to the gate of
Or H (high level) voltage is input respectively,
The transistor is turned on, which causes the transistor Q₆,
Q₇Source of positive and negative operating power. Reverse
Output permission / prohibition signal CS₁When becomes L, the transition
Star Q_Five, Q₈Is turned off and transistor Q₆, Q₇
Source is cut off from the power line.

Only the transistor Q ₆ is a transistor having an amplifying function in the output stage, and the video signal is inputted to its gate from the differential amplifier circuit DA. A bias voltage for control (hereinafter referred to as a control voltage) V _r is supplied from the power supply circuit 4 of FIG. 2 to the base of the transistor Q ₇ , and the resistance value between the source and the drain (source driver 2
forming the output resistance of a) changes.

The sample and hold circuit SH has a control signal C
The switch SW is turned on / off by S ₂ , and the amplitude value of the video signal is taken into the capacitor C _S during the on period.
Holds its value during the off period. The output of the sample hold circuit SH is amplified by the differential amplifier circuit DA and supplied to the gate of the transistor Q ₆ . The video signal amplified by the transistor Q ₆ is supplied from its drain to the source bus (which can be approximated by the load capacitor C _L ). The output voltage of the output stage OS is fed back to the gate of the transistor Q ₂ .

After that, it is assumed that the output enable / disable signal CS ₁ is H and the transistors Q ₅ and Q ₈ are on. If the gate voltage of the transistor Q _i (i = 1, 2) is represented by V _Gi , then V
_G2 <When V _G1, conductance between the source-drain of Q ₁ is (equal to the gate voltage of Q ₆₎ the drain voltage for Q ₁ than in the Q larger next than that of _2, V _G2 = V _G1
Goes down, increasing the drain current of Q ₆ and increasing the load C
Charge _L and raise V _G2 .

When V _G2 > V _G1 , the conductance between the source and drain of Q ₂ becomes larger than that of Q ₁ , and V _G2
The drain voltage of Q ₂ is lower than that when V _G1 . Therefore, the conductance between the source and drain of Q ₃ and Q ₄ of the current mirror circuit CM is increased, the gate voltage of Q ₆ is increased, the drain current is decreased, the load _CL is discharged, and V _G2 is decreased. In this way, the differential amplifier circuit DA is in a stable state with V _G2 = V _G1 .

Load capacitor C_LAt the other end of the
Voltage (eg equal to common potential) V_CIs supplied
You. Current I flowing from the positive power source 5 to the source driver 2a
₊And the current I flowing from the source driver 2a to the negative power source 6
_-Are almost equal, and the load current I _LThe size of these inputs
Current I₊, I_-Is almost proportional to.

[0010]

As shown in FIG. 4, the source driver 2a has an input current (I ₊ , I ₋ ) vs. control voltage (V _r ) characteristic due to the manufacturing process of the source driver IC 2. Variation occurs between individual ICs. Therefore, the output current I _{L of the} source driver also varies among ICs. If the output current I _L is too small, the liquid crystal pixels will be poorly driven, and if it is too large, the input current (power supply current) will be wasted.

As shown in FIG. 2, when the plurality of source driver ICs 2 are driven by the common power supply circuit 4, the control voltage V _r supplied from the power supply circuit 4 is the input currents I ₊ , I _{− in} FIG. Of the load current I _L , that is, the IC having the lowest capability, that is, the load current I _L. Then, power is wasted in a high-performance IC.

In order to avoid this, as shown in FIG. 5, a power supply circuit 4 _i is provided for each source driver IC 2 _i , and the control voltage V _ri is controlled by the potentiometer 4 a.
It is possible to set it for each
If the number of C's is large, it takes manpower and time for the adjustment, and the productivity is remarkably reduced, which is not realistic. Further, in the above methods, the input currents I ₊ , I ₋ , and thus the load current I _L , change due to changes in the environmental conditions such as the ambient temperature of the source driver IC 4 and the LCD, and therefore the control voltage V _r is checked with a margin therefor. , V _ri must be set, so that the consumption current (input currents I ₊ , I ₋ ) increases accordingly.

An object of the present invention is to source driver IC2.
Of the source driver 2a (power input current I ₊ ,
I ₋ ), therefore, the magnitude of the load current I _L can be kept constant, and a power supply circuit 4 for driving a source driver that does not require circuit adjustment is provided.

[0014]

[Means for Solving the Problems]

(1) According to the power supply circuit of the invention of claim 1, the output current of at least one of the positive power supply output terminal and the negative power supply output terminal has a constant current characteristic. (2) In the invention of claim 2, in the above-mentioned (1), the source driver controls the magnitude of the control voltage (the positive and negative power source input currents of the source driver to control the magnitude of the output current of the source driver). (Voltage for controlling) input terminal, and the power supply circuit accordingly has a control voltage output terminal, and positive power supply output regardless of variations in positive / negative power supply current vs. control voltage characteristics of the source driver. The control voltage is automatically adjusted so that the output current of at least one of the terminal and the negative power supply output terminal becomes a predetermined value.

(3) In the invention of claim 3, in the above (2), the positive power source input terminal is connected to the positive power source output terminal, and the first resistor is provided between the negative power source input terminal and the negative power source output terminal. Connect the second resistor and the collector-emitter of the npn-type transistor in series between the positive power supply input terminal and the negative power supply output terminal, connect the base of the transistor to the negative power supply output terminal, and connect the collector of the transistor. Is connected to the control voltage output terminal.

(4) In the invention of claim 4, in the above (2), the negative power source input terminal is connected to the negative power source output terminal, and the first resistor is provided between the positive power source input terminal and the positive power source output terminal. Connect the second resistor and the collector-emitter of a pnp-type transistor in series between the negative power supply input terminal and the positive power supply input terminal, connect the base of the transistor to the positive power supply output terminal, and connect the collector of the transistor. Is connected to the control voltage output terminal.

(5) According to the invention of claim 5, in the above (3) or (4), a capacitor for preventing oscillation is connected in parallel with the second resistor. (6) According to the invention of claim 6, in (3) or (4), a resistor is inserted on the base input side of the transistor.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. In this example, the power supply circuit 4 _i is provided for each source driver IC 2 _i . In the figure, IN ₊ is a positive power supply input terminal, IN ₋ is a negative power supply input terminal, OUT ₊ is a positive power supply output terminal, OUT ₋ is a negative power supply output terminal, and OUT _vr is a control voltage output terminal.

According to the present invention, at least one of the load currents I _{P and} I _n of the positive or negative power supply output terminals has a constant current characteristic (claim 1). In the source driver 2a, since the input currents I ₊ and I _{− have} the same magnitude, if at least one of the load currents I _{P and} I _n of the source driver driving power supply circuit 4 has a constant current characteristic,
The other also has a constant current.

As a result, even if the characteristics of the source driver IC vary or the environmental conditions such as the ambient temperature change, the input currents I ₊ and I ₋ of each source driver 2a in the source driver IC, and thus the load thereof. The magnitude of the current I _L can be set to a substantially constant value. The power source circuit 4 _i of FIG. 1A is of a type in which the source driver as a load has an input terminal for the control voltage V _r as described in FIG.
Even if the positive and negative power supply current (I ₊ , I ₋ ) vs. control voltage (V _r ) characteristics of the built-in source driver vary among a plurality of source driver ICs, at least one of the load currents I _{P and} I _n is predetermined. Control voltage V _r so that it becomes a value (constant value)
Is automatically adjusted (claim 2). Next, the circuit and operation will be described in detail.

In this circuit, the positive power source input terminal IN ₊ is connected to the positive power source output terminal OUT ₊ , and the negative power source input terminal IN _−.
A resistor R ₁ is connected between the negative power supply output terminal OUT ₋ and the negative power supply output terminal OUT ₋ . Between the positive power supply input terminal IN ₊ and the negative power supply input terminal IN ₋ , the resistor R ₂ and the collector-emitter of the npn-type transistor Q are sequentially connected in series. Then the base negative power output terminal OUT _- Connect to connect the collector to the control voltage output terminal OUT _vr (claim 3).

The currents flowing through the resistors R ₁ and R ₂ are I ₁ and I
₂ , and the symbols R ₁ and R ₂ are used to represent the resistance value. Positive, negative power supply input terminal IN _+, IN _- the voltage between E
And load current flowing into the negative power supply output terminal OUT ₋ is I
_{Let n be} the base-emitter voltage of the transistor Q _be V _be and the base current _be I _b . V _r = E−R ₂ I ₂ ………… (1) ∴I ₂ = E / R ₂ −V _r / R ₂ ………… (2) I ₁ = V _be / R ₁ ………… (3) I _b = I _n −I ₁ = I _n −V _be / R ₁ (4) On the other hand, the current I ₂ can be expressed as I ₂ = I _b h _fe when the current amplification factor of the transistor Q is represented by h _fe. . By substituting the I _b of the above equation _{(4), I 2 = I b h fe} = (I n -V be / R 1) h fe ......... (5) (1) formula to I ₂ ( 5) by substituting the _{equation, V r = E-R 2} (I n -V be / R 1) h fe ......... (6) (6) I n from the equation _{I n = (E-V r} ) / R ₂ h _fe + V _be / R ₁ (7) In the above equation, E and V _r are several V, V _be ≈0.6 V, R ₁ is several tens to several 100 ohms, and R ₂ is several. The first term can be neglected as compared with the second term, since 10 to several 100 KΩ, R ₂ >> R ₁ , and h _fe is in the order of several 10 to several 100. Therefore, I _n = V _be / R ₁ (7 '), and I _n is almost constant.

On the other hand, the source driver input currents I ₊ , I
_{Since −} and the control voltage V _r have a linear relationship as shown in FIG. 4, the input current I _n of the source driver IC2 _i is approximated as I _n = A _i V _r + B _i (8) it can. Here, A _i and B _i are source driver ICs
It is a constant that varies depending on 2 _i .

If V _r satisfying (7) or (7 ') and (8) at the same time is represented by V _ri , then from formulas (7') and (9), A _i V _ri + B _i = V _be / R ₁ ∴ V _ri = (V _be / R ₁ −B _i ) / A _i ... (9 ′). Also the _{(7) V ri = {E} + (V be / R 1 -B i) R 2 h fe} in the case of using the formula _{/ (1 + A i R 2} h fe) ......... (9). This V _ri is the value of V _r at point P in FIG. 1B.

As can be seen from the above description, in equation (8)
Input current between source driver ICs shown (I_+,I_-)versus
Control voltage (V_r) Regardless of variations in characteristics,
Road 4 _iOutput current I_n(= I_p) Becomes almost constant
Both control voltage V_rIs the output current I_P, I_nIs that constant
A value that is a value, that is, the value of equation (9 '), (9)
It is set dynamically.

Next, it will be qualitatively explained that the output current I _n (= I _P ) becomes constant. If I _n increases (decreases) for some reason, the base current I _b of the transistor Q increases (decreases), and therefore the collector current I ₂ that is h _fe times the base current also increases (decreases). . Then, the voltage drop across the resistor R ₂ increases (decreases), and therefore the control voltage V _r decreases (rises), which causes the source driver IC.
Input current I _n decreases (increases). As described above, the power supply circuit 4 _i holds the current I _n at a constant value by the negative feedback control. The capacitor C ₁ in parallel with the resistor R ₂ is for performing phase compensation to prevent loop oscillation (Claim 5).

[0027] by a change in environmental conditions such as temperature, the electrical properties of semi-source driver IC and LCD is changed, so that the value of V _BE / R ₁ is constant, the transistor Q and the resistor R ₁ By selecting, the output currents I _P and I _n can be held constant. In the power supply circuit 4 _i of FIG. 1A, the source driver IC 2 _i has a control voltage input terminal for inputting the control voltage V _{r based} on the voltage of the negative power supply. When the control voltage input terminal for inputting the voltage V _r is provided, the circuit of FIG. 1C using the pnp type transistor Q may be used (claim 4). (1) the contents described with respect to (9) may be replaced with I _n the I _P, can be directly applied to the circuit of FIG. 1C.

In the circuits of FIGS. 1A and 1C, a base resistor for limiting the base current may be inserted at the input terminal of the base to protect the transistor (claim 6). Although the bipolar transistor is used in the power supply circuit of FIG. 1, it is also possible to use an FET transistor, an operational amplifier, or the like instead.

In the above description, the power supply circuit 4 _i is provided for each source driver IC 2 _i , but if the variation of the source driver IC is small, one power supply circuit is provided for several source driver ICs. Alternatively, one power supply circuit may be provided for all the source driver ICs as in the case of FIG. With this configuration, the total input current of the plurality of source driver ICs can be kept constant against changes in environmental conditions, and the control voltage V _r can be automatically adjusted.

[0030]

As described above, according to the present invention,
Even if the electric characteristics of the source driver IC2 vary or the ambient environmental conditions change, the magnitudes of the current consumptions I _+, I _{− of the} source driver 2a, and thus the load current I _L thereof, can be kept constant. Further, it is possible to provide a power supply circuit which does not require circuit adjustment including adjustment of the control voltage V _r and therefore has high productivity.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention, and B is A.
6 is a graph showing the relationship between the output current and the control voltage of C, and C is a circuit diagram showing another embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional TFT matrix LCD display device.

3 is a circuit diagram showing an example of a source driver 2a in FIG.

FIG. 4 is a graph showing a relationship between an input current and a control voltage of the source driver 2a shown in FIGS. 2 and 3.

FIG. 5 is a circuit diagram showing another example of a conventional TFT matrix LCD display device.

Claims (6)

[Claims] 1. A positive power supply input terminal, a negative power supply input terminal, and T
A liquid crystal display device power supply circuit having a positive power supply output terminal and a negative power supply output terminal for supplying operating power to a source driver of an FT matrix liquid crystal display device, wherein at least one of the positive power supply output terminal and the negative power supply output terminal is provided. A power supply circuit for a liquid crystal display device, which is characterized in that the output current has a constant current characteristic. 2. The voltage according to claim 1, wherein the source driver controls the magnitude of the output current of the source driver by controlling the magnitude of the control voltage (positive or negative power source input current of the source driver). ), The power supply circuit correspondingly has a control voltage output terminal, and the control voltage is controlled so that the output current of at least one of the positive power supply output terminal and the negative power supply output terminal becomes a predetermined value. A power supply circuit for a liquid crystal display device, which is characterized by automatically adjusting. 3. The positive power supply input terminal according to claim 2, wherein the positive power supply input terminal is connected to a positive power supply output terminal, and a first resistor is connected between the negative power supply input terminal and the negative power supply output terminal. A second resistor and a collector-emitter of an npn-type transistor are sequentially connected in series between a terminal and a negative power supply input terminal, a base of the transistor is connected to the negative power supply output terminal, and a collector of the transistor is controlled by the control circuit. A power supply circuit for a liquid crystal display device that is connected to a voltage output terminal. 4. The negative power supply input according to claim 2, wherein the negative power supply input terminal and the negative power supply output terminal are connected, and a first resistor is connected between the positive power supply input terminal and the positive power supply output terminal. A second resistor and a collector-emitter of a pnp-type transistor are sequentially connected in series between the terminal and the positive power supply input terminal, the base of the transistor is connected to the positive power supply output terminal, and the collector of the transistor is controlled by the control circuit. A power supply circuit for a liquid crystal display device that is connected to a voltage output terminal. 5. The power supply circuit for a liquid crystal display device according to claim 3, wherein an oscillation preventing capacitor is connected in parallel with the second resistor. 6. The power supply circuit for a liquid crystal display device according to claim 3, wherein a resistor is inserted in the base input side of the transistor.