JPH088413A - Method of manufacturing semiconductor substrate - Google Patents

Abstract

PURPOSE:To prevent the generation of a gap in a bonding part, improve bonding power, and stabilize the quality of a single crystal layer of a silicon wafer which layer turns to an active layer, by forming an oxide film like an SiO2 film on the bonding surface of a silicon wafer to the other wafer, and stacking and bonding the wafers. CONSTITUTION:A silicon wafer having (100) face orientation by the CZ method, and a sappphire wafer having (1102) face orientation by epitaxial growth which is used as a device of an SOS structure substrate are used as starting materials. An oxide film like an SiO2 film is formed on the bonding surface of the silicon wafer, and thereon the sapphire wafer is stacked at a normal temperature. The temperature is increased up to about 270 deg.C by about 0.5-5 hours for bonding. After a bonded silicon wafer layer is ground to be thinner than or equal to 10mum, the thickness of the silicon wafer layer is reduced to be at least 3mum or less by etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor substrate having an SOS structure, which is formed by bonding a silicon wafer and another wafer having a low water absorption such as a sapphire wafer.

[0002]

2. Description of the Related Art As a conventional semiconductor substrate, there is a semiconductor substrate having an SOS structure (Silicon On Sapphire structure) in which a heteroepitaxially grown silicon film is formed on a sapphire wafer surface which serves as a support substrate for an insulator. Has been widely studied by
In recent years, it has been put to practical use as an element under severe radiation exposure environments such as space development and nuclear reactors.

However the semiconductor substrate of this structure, the epitaxial growth of a lattice mismatch of the silicon film, as well as the difference in thermal expansion coefficient between silicon and sapphire, the dislocation density in the silicon film is increased (10 ^8-10 cm ^{- 2} ), a silicon wafer obtained by processing a silicon single crystal ingot manufactured by the CZ method, the FZ method, etc. (the silicon wafer of the present invention refers to this) Performance is not enough.

[0004]

Therefore, attempts have been made to directly bond the silicon wafer to the sapphire wafer. However, in such a semiconductor substrate having an SOS structure, when a silicon wafer and a sapphire wafer are usually superposed at room temperature and bonded by heat treatment, sapphire is a single crystal and does not absorb excess water. There is a problem that voids are apt to occur in the portion and a sufficiently large joining force cannot be obtained. That is, even if a silicon wafer is superposed on a sapphire wafer at room temperature (room temperature) and heat-treated at 250 ° C. or higher to improve the bonding force at the bonded portion, voids are often generated at the bonded portion.

Therefore, an object of the present invention is to bond a silicon wafer to a sapphire wafer or the like and prevent the formation of voids in the bonded portion, thereby strengthening the bonding force and forming a single crystal of a silicon wafer which becomes an active layer. The object is to provide a semiconductor substrate whose layers are stable in quality.

[0006]

According to the present invention, in particular, in a semiconductor substrate having an SOS structure formed by bonding a silicon wafer to another wafer such as a sapphire wafer, in order to prevent the occurrence of voids at the bonding portion, It is characterized by the following manufacturing method.

(1) When manufacturing a semiconductor substrate formed by bonding a silicon wafer and another wafer to each other, an oxide film such as SiO ₂ is formed on the bonding surface of the silicon wafer to the other wafer. After being formed, the other wafer is overlaid and bonded.

(2) The other wafer bonded to the silicon wafer on which the oxide film is formed is a sapphire wafer or a silicon wafer, and the thickness of the oxide film formed on the silicon wafer is 50 angstroms or more.

(3) SiO on the bonding surface of the silicon wafer
Form an oxide film such as ₂ and superpose it on a sapphire wafer at room temperature. In order to prevent cracks from occurring between the superposed wafers, it takes about 0.5 to 5 hours until the temperature reaches around 270 ° C. The temperature is raised to bond the silicon wafer layer, the bonded silicon wafer layer is ground to a thickness of 10 μm or less, and an etching process is performed to reduce the thickness of the silicon wafer layer to at least 3 μm. In this case, the semiconductor substrate is heat-treated in the temperature range of 300 to 1000 ° C. for 0.5 to 5 hours, and then the thickness of the silicon wafer layer is 0.1 to 3 μm, preferably 0.1 to 3 μm.
It is preferable to gradually reduce the thickness by polishing until the thickness becomes 1 μm.

[0010]

When the silicon wafer is bonded to the other wafer such as sapphire or silicon, this oxide film
In order to prevent the occurrence of voids in the bonding part due to the small amount of water adsorption by the natural oxide film of the silicon wafer,
An oxide film is formed on a silicon wafer to a thickness of at least 50 angstroms.

The silicon wafer having the oxide film formed thereon is superposed on the other wafer such as a sapphire wafer or a silicon wafer at room temperature. Then, in order to prevent the occurrence of cracks in the stacked wafers, the stacked wafers are slowly heated to around 270 ° C. for about 2 hours to bond them, and then the back surface side of the silicon wafer on which an oxide film is formed. Is ground to a thickness of about 10 μm.

Further, in order to remove damage caused by grinding, etching (KOH etching at 80 ° C., etc.) is performed to reduce the thickness of the silicon wafer layer to about 3 μm, and the surface is mirror-polished to have a thin silicon layer. A semiconductor substrate having an SOS structure is obtained.

With respect to the semiconductor substrate in which the silicon layer has a thickness of 3 μm, heat treatment at a higher temperature is applied stepwise in relation to the thickness of the silicon layer to further increase the bonding strength. be able to. For example, the above semiconductor substrate can be heat-treated at 450 ° C. in a dry oxygen atmosphere, and then the silicon layer can be polished to a thickness of 0.5 μm. Here, if the silicon layer is not thinned to a thickness of 0.5 μm or less, and if the silicon layer having a thickness of 2.2 μm is heat-treated at 900 ° C. for 2 hours, dislocations are generated at a high density. If the silicon layer is thicker and the heat treatment temperature is higher during this heat treatment, not only dislocations but also cracks occur. However, by stepwise heat treatment and polishing, an additional 0.2
In the case of a semiconductor substrate having a silicon layer thinned to a thickness of μm or less, as in the case of an SOS type semiconductor substrate in which a quartz glass wafer and a silicon wafer are bonded,
Dislocations and cracks do not occur even if heat treatment is applied at 00 ° C. for 2 hours.

According to the above steps, by forming an oxide film on the silicon wafer, it is possible to prevent the formation of voids on the bonding surface, particularly when the silicon wafer is bonded to the sapphire wafer or the silicon wafer. It is possible and can be joined by a strong adhesive force. Further, in the bonding of the silicon wafer and the sapphire wafer by heat treatment, the formation of the oxide film can prevent the diffusion of impurities such as boron between the sapphire wafer and the bonding surface into the silicon wafer layer.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor substrate according to an embodiment of the present invention. However, unless otherwise specified, the experimental conditions, sample dimensions, materials, etc. described in this example are not intended to limit the scope of the present invention thereto, but are merely illustrative examples.

Starting materials were a silicon wafer having a (100) plane orientation by the CZ method and a sapphire wafer having a (1102) plane orientation which is usually used for an apparatus of an SOS structure substrate formed by epitaxial growth. The silicon wafer and the sapphire wafer each have a diameter of 1
The disk is 00 mm and has a thickness of 525 μm.

First, as a comparative example, the silicon wafer and the sapphire wafer are washed, and the silicon wafer and the sapphire wafer are superposed at room temperature. The bonding force at this time is resistant to the grinding force for grinding the silicon wafer side. Since it is not large enough to perform the heat treatment, heat treatment at high temperature is necessary to increase the bonding force.

FIG. 1 is an X-ray topographic photograph of a bonded silicon-sapphire wafer (100 mm diameter). FIG. 1A shows voids generated when left at room temperature for a long time, and FIG. It shows the voids induced by the evaporation of water. In the case where the oxide film is not formed on the silicon wafer as described above, FIG. 1A and FIG.
As shown in (1), a void is generated in the wafer, but the formation of the oxide film prevents the void from being generated.

As shown in Table 1, there is a difference in coefficient of thermal expansion between silicon and sapphire. Therefore, in this experiment, in order to mitigate the influence of the difference in the coefficient of thermal expansion, the silicon / sapphire junction is preliminarily provided with an oxide film of 200 angstrom and is 300 μm thick, which is thinner than the sapphire wafer. It was used.

[0020]

[Table 1]

However, even if a thin silicon wafer is used, cracking occurs when it is heat-treated at a temperature higher than 300.degree. FIG. 1 (c) shows the occurrence of cracks when a silicon / sapphire wafer is heat-treated at 400 ° C. The cracks described above also occur in the silicon / quartz glass bonding.

In order to prevent the occurrence of cracks as described above,
The bonded body of silicon wafers stacked on the sapphire wafer was heated to 270 ° C. for 2 hours, and then ground to reduce the thickness from 300 μm to 10 μm. Further, in order to remove the layer damaged by the grinding material of the grinder, the surface layer of the silicon layer was etched with a KOH solution at 80 ° C. to a thickness of 3 μm, and then in dry oxygen at 450 ° C. for 2 hours. Heat treatment was applied. Then, the silicon layer was finally thinned by polishing (mirror finish) until the thickness became 0.5 μm.

However, if this polishing time is too long,
Wrinkle-like scratches occur on a part of the silicon layer. This is the difference between the removal rates of silicon in grinding and polishing, that is, in grinding, it is ˜100 μm / min.
It should be noted that the polishing force is ˜0.1 μm / min, and the resistance force acting on the surface of the silicon wafer is much larger during polishing than during polishing.

Next, a method of measuring the bonding force of the semiconductor substrate having the SOS structure manufactured as described above and the test results will be described. Tensile Test Device and Sample for Bonding Force Measurement A semiconductor substrate to which a silicon wafer layer thinned by the above method is bonded is subjected to a high temperature heat treatment and then subjected to a tensile test (7 × 7). The sample was cut into a size of mm ² .

The thickness of the silicon layer of the sample was set to three types: 0.5 μm> 0.5 to 1.0 μm 1.0 to 3.0 μm. The test equipment (Se
FIG. 2 shows the structure of the main part of bastian V) and the fracture state of the sample.

In FIG. 2 (a), 1 is a jig of a tensile tester, 2 is a sample (semiconductor substrate) consisting of a sapphire wafer layer 2a and a silicon wafer layer 2b, 3 is an adhesive, 4
Is a sample support member. The sectional area of the jig 1 is 5.7.
mm ² , the tensile strength of the adhesive between the jig 1 and the sample 2 is about 80 MPa.

The tensile test under the above conditions was evaluated when the bonding force between silicon and sapphire exceeded 80 MPa, that is, in the case of the fracture condition (a) shown in FIG.
The mark () indicates peeling of the adhesive, so the bonding of both wafers is in the best condition, the case (b) (marked with △) indicates that some damage has occurred to the sapphire, and the case (c) (marked with □) The mark () indicates the case where some damage occurs in silicon, and the case (4) (mark ●) indicates the case where the bonding of both wafers is incomplete.

Results of Measurement of Bonding Force (Results of Tensile Test) FIG. 3 shows the results of a tensile test of a sample of a semiconductor substrate having an SOS structure using the above tensile test apparatus. Sample heat-treated at 450 ° C for 2 hours, (b) sample heat-treated at 700 ° C for 2 hours in dry oxygen, (c) temperature rise in dry oxygen at 900 ° C for 2 hours, and then temperature drop in nitrogen The case where each of the prepared samples is used is shown.

In the case of a bonded structure of silicon and quartz glass having a silicon layer having no dislocations and no cracks in a semiconductor substrate having an SOI structure, a thick silicon layer (thickness 2.0 ± 0) is obtained in a high temperature region. A sample having a thin silicon layer (0.5 ± 0.5 μm, where thickness ≠ 0) in the high temperature region has a critical thickness. However, such a critical condition is not observed in the case of the bonded body of silicon and sapphire within the range of the test temperature and the sample thickness under the above conditions.

Although the bonding strength of the silicon layer indicated by □ in FIG. 3 is sufficiently high, the silicon layer itself frequently breaks. Such breakage is not observed in the bonded body of silicon and quartz glass. In any case, sapphire does not break.

Summary of Experimental Results FIG. 4 is a model illustration of the formation of voids in various bonding forms (combinations) and why the presence of an intervening thin oxide film layer can prevent the formation of voids. is there. In FIG. 4, (a) shows silicon wafers directly superposed without an oxide film interposed and bonded at a temperature of 100 ° C. or higher, and (b) shows silicon wafers having a thickness of 200 angstroms or more on one side. SiO ₂ (oxide film) formed thereon, (c) a silicon wafer and a quartz glass wafer bonded together, (d) a silicon wafer and a sapphire wafer bonded together, (e)
Indicates a silicon wafer on which SiO ₂ (oxide film) having a thickness of 200 Å or more is formed.

As is apparent from FIG. 4, silicon / silicon in the case where no oxide film is formed on both silicon wafers
In the silicon junction ((a) of FIG. 4), since the adsorption of water by the natural oxide film is small, the void V is generated and silicon /
In the sapphire joint ((d) of FIG. 4), the void V is generated at the joint. On the other hand, a silicon wafer with a thickness of 2
Silicon / silicon bonding (FIG. 4 (b)) silicon / quartz glass bonding (FIG. 4 (c)) when an oxide film having a thickness of 00 angstroms or more is formed, and an oxide film having a thickness of 200 angstroms or more is formed on a silicon wafer. No void is observed in the silicon / sapphire junction when formed ((e) in FIG. 4). It is necessary that the thickness of the oxide film is at least 50 angstroms or more, and if it is 200 angstroms, it can be said that the thickness is sufficient to adsorb moisture on the bonding surface.

In the experimental example shown in FIG. 4, in the silicon / quartz glass bonding (FIG. 4 (c)), no void was generated in the bonding portion, and the silicon / sapphire bonding (FIG. 4 (d)) was performed.
Then, the reason why voids are generated at the joint is explained as follows. That is, quartz glass has an amorphous and bulky structure. On the other hand, sapphire is a single crystal having a dense structure and does not absorb excess water. On the other hand, as described above, a silicon wafer having a thickness of 200 μm or more causes cracks during bonding by heating at 300 ° C., but a sapphire wafer does not.

In the silicon / quartz glass bonding, a critical temperature and a critical thickness of the thickness of the silicon layer exist in order to secure a bonding state in which dislocations do not exist and cracks do not occur. On the other hand, in the silicon / sapphire bond, no clear dependence of the critical element is observed as far as the tensile test.

Next, the relationship between the thickness of the silicon layer and the crystal having no dislocation was investigated by using the double crystal X-ray topography method and the cross-section transmission electron microscope (TEM). FIG. 5 shows FIG.
The same sample (900
It is an optical micrograph of heat treatment at (° C.), and optical fringes showing a large thickness distribution are observed. In FIG. 5, one stripe increment corresponds to a silicon layer thickness of 0.06 μm.

In FIG. 5, according to the two elongated X-ray topographic images recognized as a mesh, misfit dislocations are recognized in the thicker silicon layer region. From this dislocation distribution, the thickness of the dislocation-free silicon layer is small,
It can be seen that it is about 0.2 μm.

FIG. 6 (a) shows a cross-sectional TEM image of the same sample as that in FIG. 5, that is, a sample having a silicon / sapphire junction and a silicon layer having a thickness of 2.2 μm. As is clear from the figure, high-density dislocations are observed near the bonding interface.

FIG. 6B shows a T of a conventional SOS wafer having a silicon epitaxial layer having a thickness of 0.6 μm.
EM images are shown. In such a conventional SOS wafer, not only high-density dislocations but also high-density stacking faults starting from the interface are observed.

FIG. 6 (c) is a TEM image of the same sample as in FIG. 5 with a silicon layer having a thickness of 0.2 μm, in which dislocations having an oxide film with a thickness of 20 nm do not exist. A silicon layer is shown.

Further, FIG. 6 (d) is a crystal lattice image of FIG. 6 (c), showing a rough surface of sapphire at the SiO ₂ / sapphire interface.

As is apparent from FIGS. 6A to 6D, when the silicon layer is sufficiently thin, for example, a thickness of 0.2 μm for a silicon / sapphire bond and a silicon / quartz glass bond. Can provide a dislocation-free layer when the thickness is 0.5 μm. This is because in such a thin layer, the silicon lattice elastically expands and contracts along the substrate without generating dislocations at the silicon / sapphire joint and the silicon / quartz glass joint.

FIG. 7 shows a profile in the depth direction by secondary ion mass spectrometry (SIMS) of the same 0.6 μm thick sample as in FIG. The thickness of the oxide film is 2
In the case of 0 nm or less, a peak value indicating the presence of boron, which is an impurity introduced before superimposing both wafers, is observed. The thin oxide film as described above functions to prevent the formation of voids and to prevent the diffusion of boron into the silicon layer. In addition, here, the measurement was performed by focusing on boron, but it is considered that similar effects can be obtained with other harmful impurities.

[0043]

As described above, according to the present invention, an oxide film is formed on a silicon wafer in a semiconductor substrate formed by superposing and bonding a silicon wafer on the other wafer such as a sapphire wafer or a silicon wafer. Thus, it is possible to prevent voids from being generated at the bonding surfaces of both wafers, and it is possible to obtain a semiconductor substrate in which two types of wafers are bonded with a strong adhesive force.

Further, particularly in the case of a semiconductor substrate obtained by bonding a silicon wafer to a sapphire wafer,
By forming the oxide film to have a thickness of at least 50 angstroms or more, it is possible to prevent the diffusion of boron as an impurity at the bonding interface and prevent the adverse effect of the boron on the bonding portion. Further, by making it thinner, a dislocation-free silicon layer can be obtained.

[Brief description of drawings]

FIG. 1 is an X-ray photograph of a silicon-sapphire wafer according to an embodiment of the present invention.

FIG. 2 is an explanatory view of a semiconductor substrate bonding force measurement test.

FIG. 3 is a diagram showing a result of a tensile test on a silicon-sapphire wafer.

FIG. 4 is a comparative diagram for explaining a state of a bonding portion between various wafers of a semiconductor substrate.

FIG. 5 is a photomicrograph of the tensile test piece.

FIG. 6 is a TEM photograph of a semiconductor substrate sample.

FIG. 7 is a diagram showing the number of secondary ions in the semiconductor substrate.

[Explanation of symbols]

 1 Jig for tensile test 2 Sample (semiconductor substrate) 2a Sapphire wafer 2b Silicon wafer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuaki Nakazato 1393 Yashiro Odaira, Sarahaku-shi, Nagano Nagano Electronics Co., Ltd. 72) Inventor Kazushi Nakazawa 1393 Yashiro, Osamu, Saraburo-shi, Nagano Nagano Electronics Co., Ltd.

Claims (5)

[Claims] 1. When manufacturing a semiconductor substrate formed by bonding a silicon wafer and another wafer to each other, an oxide film such as SiO ₂ is formed on a bonding surface of the silicon wafer to the other wafer. A method for manufacturing a semiconductor substrate, which comprises squeezing and then superimposing and bonding the other wafer. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the other wafer is a sapphire wafer or a silicon wafer. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the oxide film has a thickness of 50 angstroms or more. 4. An oxide film such as SiO ₂ is formed on a bonding surface of a silicon wafer and superposed on a sapphire wafer at room temperature, and the temperature of the superposed wafers is kept at around 270 ° C. to prevent cracking. 0.5 to
Bonding by raising the temperature for about 5 hours, and then grinding the bonded silicon wafer layer to a thickness of 10 μm or less, and then performing etching to reduce the thickness of the silicon wafer layer to at least 3 μm. A method of manufacturing a semiconductor substrate, comprising: 5. A semiconductor substrate in which the thickness of the silicon wafer layer is reduced to about 3 μm by the method of claim 4, and the semiconductor substrate is heat-treated at a temperature range of 300 to 1000 ° C. for 0.5 to 5 hours. 5. The semiconductor substrate according to claim 4, wherein the thickness of the silicon wafer layer is then gradually reduced by polishing until the thickness becomes 0.1 to 3 μm, preferably 0.1 to 1 μm. Production method.