JPH0878646A - Semiconductor substrate and manufacturing method - Google Patents
Semiconductor substrate and manufacturing methodInfo
- Publication number
- JPH0878646A JPH0878646A JP21104594A JP21104594A JPH0878646A JP H0878646 A JPH0878646 A JP H0878646A JP 21104594 A JP21104594 A JP 21104594A JP 21104594 A JP21104594 A JP 21104594A JP H0878646 A JPH0878646 A JP H0878646A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- silicon wafer
- layer
- insulating layer
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims description 46
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 112
- 239000010703 silicon Substances 0.000 claims abstract description 112
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 109
- 235000012431 wafers Nutrition 0.000 claims abstract description 82
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 40
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 15
- 239000010409 thin film Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000007787 solid Substances 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 150000003376 silicon Chemical class 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000006104 solid solution Substances 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000002011 beta-particle spectroscopy Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁層上にシリコン層
（以下、ＳＯＩ層という）を形成したＳＯＩ（Silicon-
On-Insulator）基板を得るための半導体基板に関する。
更に詳しくは、２枚のシリコンウェーハを絶縁層を介し
て貼り合わせる半導体基板の製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon-type) in which a silicon layer (hereinafter referred to as an SOI layer) is formed on an insulating layer.
The present invention relates to a semiconductor substrate for obtaining an on-insulator) substrate.
More specifically, the present invention relates to a method for manufacturing a semiconductor substrate in which two silicon wafers are bonded together via an insulating layer.
【０００２】[0002]
【従来の技術】近年、高集積ＣＭＯＳ（Complementary
Metal Oxide Semiconductor）、ＩＣ、高耐圧素子など
がＳＯＩ基板を利用して製作されるようになってきてい
る。絶縁層の上にデバイス作製領域として使用される単
結晶シリコン層を形成したＳＯＩ基板は、高集積ＣＭＯ
Ｓの場合にはラッチアップ（寄生回路による異常発振現
象）の防止に、また高耐圧素子の場合にはベース基板と
の絶縁分離にそれぞれ有効である。このＳＯＩ基板の製
造方法には、シリコンウェーハ同士を二酸化シリコン層
（以下、シリコン酸化層という）、即ち絶縁層を介して
貼り合わせる方法、絶縁性基板又は絶縁性薄膜を表面に
有する基板の上にまず多結晶シリコン薄膜をＣＶＤ（Ch
emical Vapor Deposition）法により堆積させ、次いで
レーザーアニールによって単結晶化するＺＭＲ法、シリ
コン基板内部に高濃度の酸素イオンを注入した後、高温
でアニール処理してこのシリコン基板表面から所定の深
さの領域に埋込みシリコン酸化層（絶縁層）を形成し、
その表面側のシリコン層を活性領域とするＳＩＭＯＸ法
などがある。これらの方法の中でも、貼り合わせ法によ
り作製されたＳＯＩ基板は、ＳＯＩ層の結晶性が極めて
良好であることから、有望視されて来ている。2. Description of the Related Art In recent years, highly integrated CMOS (Complementary
Metal Oxide Semiconductors), ICs, high breakdown voltage elements, etc. have been manufactured using SOI substrates. An SOI substrate in which a single crystal silicon layer used as a device manufacturing region is formed on an insulating layer is a highly integrated CMO.
In the case of S, it is effective in preventing latch-up (abnormal oscillation phenomenon due to a parasitic circuit), and in the case of a high breakdown voltage element, it is effective in insulating and separating from the base substrate. This SOI substrate manufacturing method includes a method of bonding silicon wafers to each other through a silicon dioxide layer (hereinafter referred to as a silicon oxide layer), that is, an insulating layer, an insulating substrate or a substrate having an insulating thin film on the surface. First, a polycrystalline silicon thin film is formed by CVD (Ch
ZMR method in which a single crystal is formed by laser annealing, and high-concentration oxygen ions are implanted into the inside of the silicon substrate, and then annealed at a high temperature to obtain a predetermined depth from the surface of the silicon substrate. A buried silicon oxide layer (insulating layer) is formed in the region,
There is a SIMOX method in which a silicon layer on the surface side is used as an active region. Among these methods, the SOI substrate manufactured by the bonding method is regarded as promising because the crystallinity of the SOI layer is extremely good.
【０００３】このシリコンウェーハの貼り合わせ法は、
具体的にはそれぞれ約６００μｍの２枚のシリコンウェ
ーハをシリコン酸化層からなる絶縁層を介して接合し、
熱処理した後、２枚のシリコンウェーハの一方のシリコ
ンウェーハの表面を砥石で研削し、更に研磨布で研磨し
てこのシリコンウェーハの厚さを約１〜１０μｍの範囲
にし、この研磨した側の厚さ約１〜１０μｍのシリコン
層をデバイス形成用のＳＯＩ層としている。また、この
種のシリコンウェーハはチョクラルスキー法（以下、Ｃ
Ｚ法という）で引上げたシリコン単結晶棒から作製され
た場合には、通常このシリコンウェーハの酸素濃度は
１．０〜１．５×１０18／ｃｍ3（旧ＡＳＴＭ値：以下
同じ）である。これに対して、酸素に起因する結晶欠陥
を低減させるために、デバイス形成用の上記ＳＯＩ層に
要求される酸素濃度は１．０×１０17／ｃｍ3以下であ
る。しかし、上記従来の貼り合わせ法で作られた上記Ｓ
ＯＩ層では、酸素濃度が依然として１．０×１０17／ｃ
ｍ3を越えており、このＳＯＩ層のより一層の低酸素濃
度化が求められていた。This silicon wafer bonding method is as follows.
Specifically, two silicon wafers each having a thickness of about 600 μm are bonded via an insulating layer made of a silicon oxide layer,
After the heat treatment, the surface of one of the two silicon wafers is ground with a grindstone, and further polished with a polishing cloth so that the thickness of this silicon wafer is in the range of about 1 to 10 μm. A silicon layer having a thickness of about 1 to 10 μm is used as an SOI layer for device formation. Further, this type of silicon wafer is manufactured by the Czochralski method (hereinafter, C
When produced from a silicon single crystal ingot pulled up by the Z method), the oxygen concentration of this silicon wafer is usually 1.0 to 1.5 × 10 18 / cm 3 (old ASTM value: the same applies hereinafter). . On the other hand, in order to reduce crystal defects caused by oxygen, the oxygen concentration required for the SOI layer for device formation is 1.0 × 10 17 / cm 3 or less. However, the S made by the conventional pasting method is used.
In the OI layer, the oxygen concentration is still 1.0 × 10 17 / c
Since it exceeds m 3 , there is a demand for further lowering the oxygen concentration of this SOI layer.
【０００４】この点を解決した半導体基板が特開平２−
４６７７０号公報に提案されている。この半導体基板は
シリコン支持基板上にＳｉＯ2膜（絶縁層）が形成さ
れ、このＳｉＯ2膜上には０．１〜１０μｍ程度のシリ
コン薄膜が形成されるＳＯＩ構造の基板であって、シリ
コン支持基板の酸素濃度が１０17〜１０19／ｃｍ3の範
囲にあり、デバイスを形成するその上層のシリコン薄膜
の酸素濃度が１０17／ｃｍ3以下の濃度であることを特
徴とする。この半導体基板は酸素濃度１０18／ｃｍ3の
ＣＺ成長シリコン基板と、表面を酸化してＳｉＯ2膜
（絶縁層）を形成した酸素濃度１０18／ｃｍ3以下のＦ
Ｚ成長シリコン基板とを接合し、熱処理して貼り合わせ
た後、ＦＺ成長シリコン基板を研磨することにより０．
１〜１０μｍ程度の厚さを有する１０17／ｃｍ3以下の
酸素濃度のシリコン薄膜を得ている。ＦＺ法（フローテ
ィングゾーン法）から作られたシリコン結晶棒は結晶育
成時に石英るつぼを使用せず、単結晶中への酸素の混入
を非常に小さくできるため、ＦＺ成長シリコン基板はＣ
Ｚシリコン基板に比較して酸素の固溶量が少ない特長が
ある。A semiconductor substrate that solves this problem is disclosed in Japanese Patent Laid-Open No.
It is proposed in Japanese Patent No. 46770. This semiconductor substrate is an SOI structure substrate in which a SiO 2 film (insulating layer) is formed on a silicon supporting substrate, and a silicon thin film of about 0.1 to 10 μm is formed on the SiO 2 film. The oxygen concentration of the substrate is in the range of 10 17 to 10 19 / cm 3 , and the oxygen concentration of the upper silicon thin film forming the device is 10 17 / cm 3 or less. A CZ-grown silicon substrate of the semiconductor substrate oxygen concentration of 10 18 / cm 3, an oxygen concentration to form an SiO 2 film (insulating layer) by oxidizing the surface 10 18 / cm 3 or less of F
After bonding with the Z-grown silicon substrate and heat-bonding them together, the FZ-grown silicon substrate is polished to a 0.
A silicon thin film having a thickness of about 1 to 10 μm and an oxygen concentration of 10 17 / cm 3 or less is obtained. A silicon crystal rod made by the FZ method (floating zone method) does not use a quartz crucible during crystal growth, and oxygen contamination into the single crystal can be made very small.
Compared with the Z silicon substrate, it has the feature that the solid solution amount of oxygen is small.
【０００５】[0005]
【発明が解決しようとする課題】しかし、特開平２−４
６７７０号公報に示される半導体基板では、ＦＺ成長シ
リコン基板に特有の結晶欠陥、例えば過剰な格子間シリ
コン原子により形成される、いわゆるＡ，Ｂスワール
や、凍結された原子空孔により形成される、いわゆるＤ
欠陥等が多く見られ、しかもＣＺ成長シリコン基板と接
合したときに酸素の固溶量が少ないことに起因してスリ
ップを生じ易く、依然として機械的強度が十分高くない
不具合があった。また現在ＣＺ法では直径１２インチ程
度の大口径のシリコン結晶棒が開発されつつあるのに対
して、ＦＺ法では最大でも直径８インチ程度のシリコン
結晶棒しか作製できないため、ＦＺ成長シリコン基板は
大径のものは得られず、ＤＲＡＭ等の高集積度に伴い大
口径化する半導体基板の量産性に劣る問題があった。However, Japanese Patent Laid-Open No. 2-4
In the semiconductor substrate disclosed in 6770, crystal defects peculiar to the FZ-grown silicon substrate, for example, so-called A and B swirls formed by excessive interstitial silicon atoms and frozen atomic vacancies are formed. So-called D
There were many defects, and moreover, when bonded to a CZ-grown silicon substrate, slip was likely to occur due to the small amount of oxygen solid solution, and the mechanical strength was still not sufficiently high. In addition, while a large-diameter silicon crystal rod having a diameter of about 12 inches is currently being developed by the CZ method, an FZ-grown silicon substrate is large because the FZ method can produce only a silicon crystal rod having a diameter of about 8 inches at the maximum. The diameter of the semiconductor substrate cannot be obtained, and there is a problem in that the mass productivity of a semiconductor substrate, which has a large diameter with the high integration degree of DRAM and the like, is poor.
【０００６】本発明の目的は、ＣＺ成長シリコンウェー
ハを２枚貼り合わせて作られる絶縁層上のＳＯＩ層の全
域の酸素濃度が１．０×１０17／ｃｍ3以下である半導
体基板を提供することにある。本発明の別の目的は、２
枚のシリコンウェーハの接合時にスリップを生じないた
め機械的強度が十分高く、量産に優れた半導体基板及び
その製造方法を提供することにある。An object of the present invention is to provide a semiconductor substrate having an oxygen concentration of 1.0 × 10 17 / cm 3 or less in the entire SOI layer on an insulating layer, which is made by bonding two CZ grown silicon wafers. Especially. Another object of the present invention is 2
It is an object of the present invention to provide a semiconductor substrate which has sufficiently high mechanical strength and is excellent in mass production because a slip does not occur at the time of joining two silicon wafers, and a manufacturing method thereof.
【０００７】[0007]
【課題を解決するための手段】本発明者らは、従来の熱
処理後の貼り合わせた２枚のシリコンウェーハの表面か
らシリコン酸化層（絶縁層）に向うに従って変化する酸
素濃度を調べたところ、表面側のＳＯＩ層と絶縁層との
界面に酸素の固溶限が示されることに着目し、この固溶
限をより小さくし、かつ絶縁層に面する所定の領域のＳ
ＯＩ層の酸素濃度を低減する条件を見出すことにより、
本発明に到達した。Means for Solving the Problems The inventors of the present invention investigated the oxygen concentration changing from the surface of two conventional bonded silicon wafers after heat treatment toward the silicon oxide layer (insulating layer), Paying attention to the fact that the solid solubility limit of oxygen is shown at the interface between the SOI layer on the front surface side and the insulating layer, this solid solubility limit is made smaller, and the S in a predetermined region facing the insulating layer is reduced.
By finding the conditions for reducing the oxygen concentration of the OI layer,
The present invention has been reached.
【０００８】図１（ｅ）に示すように、本発明はシリコ
ンウェーハ１１上に絶縁層１３が形成され、この絶縁層
１３上にデバイス形成用のＳＯＩ層１２ａが形成され、
シリコンウェーハ１１の酸素濃度が１．０〜１．５×１
０18／ｃｍ3の範囲にある半導体基板の改良である。そ
の特徴ある構成は、ＳＯＩ層１２ａの酸素濃度が０．５
〜１．０×１０17／ｃｍ3であって、かつ上記シリコン
ウェーハ１１がＣＺ法で引上げたシリコン結晶棒から作
製されたシリコンウェーハからなり、上記ＳＯＩ層１２
ａがＣＺ法で引上げたシリコン結晶棒から作製されたシ
リコンウェーハを薄膜化して形成されたことにある。As shown in FIG. 1 (e), according to the present invention, an insulating layer 13 is formed on a silicon wafer 11, and an SOI layer 12a for device formation is formed on the insulating layer 13.
The oxygen concentration of the silicon wafer 11 is 1.0 to 1.5 × 1
It is an improvement of the semiconductor substrate in the range of 0 18 / cm 3 . The characteristic structure is that the oxygen concentration of the SOI layer 12a is 0.5.
.About.1.0 × 10 17 / cm 3 , and the silicon wafer 11 is a silicon wafer manufactured from a silicon crystal rod pulled by the CZ method, and the SOI layer 12
a is formed by thinning a silicon wafer produced from a silicon crystal rod pulled up by the CZ method.
【０００９】また図１（ａ）〜図１（ｅ）に示すよう
に、本発明はＣＺ法で引上げたシリコン結晶棒からそれ
ぞれ作製された第１シリコンウェーハ１１と第２シリコ
ンウェーハ１２とを絶縁層１３を介して接合し、接合し
た第１及び第２シリコンウェーハ１１，１２を熱処理し
て貼り合わせた後、第１シリコンウェーハ１１又は第２
シリコンウェーハ１２を所定の厚さに研削研磨してデバ
イス形成用のＳＯＩ層１２ａとする半導体基板の製造方
法の改良である。その特徴ある構成は、上記接合した第
１及び第２シリコンウェーハ１１，１２を１１００〜１
２００℃、好ましくは１１００〜１１５０℃の温度範囲
で１〜１０時間熱処理して貼り合わせた後、研削前に４
００〜９００℃、好ましくは７００〜９００℃、更に好
ましくは８００〜９００℃の温度範囲で再度熱処理する
ことにある。Further, as shown in FIGS. 1 (a) to 1 (e), the present invention insulates a first silicon wafer 11 and a second silicon wafer 12 each made from a silicon crystal rod pulled by the CZ method. The first and second silicon wafers 11 and 12 bonded together via the layer 13 are heat-treated and bonded together, and then the first silicon wafer 11 or the second silicon wafer 11 or
This is an improvement of a method for manufacturing a semiconductor substrate in which a silicon wafer 12 is ground and polished to a predetermined thickness to form an SOI layer 12a for device formation. The characteristic configuration is that the bonded first and second silicon wafers 11 and 12 are 1100 to 1
After laminating by heat treatment in a temperature range of 200 ° C., preferably 1100 to 1150 ° C. for 1 to 10 hours, 4 before grinding.
It is to heat-treat again in the temperature range of 00 to 900 ° C, preferably 700 to 900 ° C, and more preferably 800 to 900 ° C.
【００１０】本発明の第１及び第２シリコンウェーハは
ともにＣＺ法で引上げたシリコン単結晶棒から作製され
る。このシリコン単結晶棒を切断して仕上げられたシリ
コンウェーハの酸素濃度は１．０〜１．５×１０18／ｃ
ｍ3の範囲にある。絶縁層は第１シリコンウェーハ又は
第２シリコンウェーハのいずれか一方又は双方の片面に
形成される。接合を良好にするために、絶縁層はいずれ
か一方のシリコンウェーハの片面に形成されることが好
ましい。図１（ａ）に示すように、図では第２シリコン
ウェーハ１２の片面に絶縁層１３が形成される。貼り合
わせ後の絶縁層とＳＯＩ層との界面として、２枚のシリ
コンウェーハの接合界面（図１ではシリコンウェーハ１
１との界面）と、接合前に絶縁層を形成したシリコンウ
ェーハとの界面（図１ではシリコンウェーハ１２との界
面）がある。本発明のＳＯＩ層１２ａと絶縁層１３との
界面は、前者の接合界面であるよりも後者の絶縁層を形
成したウェーハとの界面である方が、界面の連続性に優
れているため好ましい。即ち、図１（ｅ）に示すように
ＳＯＩ層１２ａが形成されるシリコンウェーハ１２をＳ
ＯＩ層用のシリコン基板とし、別のシリコンウェーハ１
１をその支持基板とすることが好ましい。Both the first and second silicon wafers of the present invention are made from silicon single crystal ingots pulled by the CZ method. The oxygen concentration of the silicon wafer finished by cutting this silicon single crystal ingot is 1.0 to 1.5 × 10 18 / c.
It is in the range of m 3 . The insulating layer is formed on one surface of either the first silicon wafer or the second silicon wafer or both surfaces. For good bonding, the insulating layer is preferably formed on one side of either one of the silicon wafers. As shown in FIG. 1A, the insulating layer 13 is formed on one surface of the second silicon wafer 12 in the figure. As an interface between the insulating layer and the SOI layer after bonding, a bonding interface between two silicon wafers (the silicon wafer 1 in FIG.
1) and an interface with a silicon wafer on which an insulating layer is formed before bonding (an interface with the silicon wafer 12 in FIG. 1). The interface between the SOI layer 12a and the insulating layer 13 of the present invention is preferably the interface with the wafer on which the latter insulating layer is formed rather than the former bonding interface because the continuity of the interface is excellent. That is, the silicon wafer 12 on which the SOI layer 12a is formed as shown in FIG.
Another silicon wafer as a silicon substrate for the OI layer 1
1 is preferably used as the supporting substrate.
【００１１】絶縁層の厚さは約０．５〜１．０μｍの範
囲にあり、絶縁層はシリコン酸化層（ＳｉＯ2層）であ
って、シリコンウェーハを熱酸化することにより、或い
はＣＶＤ法によりウェーハの片面に形成される。図１
（ｂ）に示すように２枚のシリコンウェーハを絶縁層を
介して接合する前に、接合しようとする表面を活性化す
るために所定の洗浄液でシリコンウェーハを洗浄するこ
とが好ましい。図１（ｃ）に示すように、接合した後の
熱処理は２枚のシリコンウェーハ１１，１２を接合した
状態で窒素（Ｎ2）雰囲気又は酸素（Ｏ2）雰囲気中で１
１００〜１２００℃、好ましくは１１００〜１１５０℃
の温度範囲で１〜１０時間、好ましくは２〜５時間行
う。これにより接合界面でシリコンの共有結合が生じ、
２枚のシリコンウェーハ１１，１２は貼り合わされ、両
者の結晶格子は一体化する。図１（ｄ）に示すように、
一体化した２枚のシリコンウェーハ１１，１２が放冷さ
れ室温になった後に、上記熱処理雰囲気と同一雰囲気中
で、４００〜９００℃、好ましくは７００〜９００℃、
更に好ましくは８００〜９００℃の温度範囲で再度熱処
理する。この熱処理時間は目標とするＳＯＩ層の厚さと
酸素の拡散距離との関係から求めれば良いが、通常は２
時間程度が好ましい。図１（ｅ）に示すように再熱処理
後、シリコン基板となる第２シリコンウェーハ１２を砥
石で研削し、その後研磨布で研磨して、約１〜１０μｍ
の厚さの薄膜に加工する。これにより厚さ約１〜１０μ
ｍのデバイス形成用のＳＯＩ層１２ａが絶縁層１３上に
得られる。[0011] The thickness of the insulating layer is in the range of about 0.5 to 1.0 [mu] m, the insulating layer is a silicon oxide layer (SiO 2 layer), by the silicon wafer is thermally oxidized, or by a CVD method Formed on one side of the wafer. FIG.
Before bonding two silicon wafers via an insulating layer as shown in (b), it is preferable to clean the silicon wafers with a predetermined cleaning liquid to activate the surfaces to be bonded. As shown in FIG. 1C, the heat treatment after the bonding is performed in a nitrogen (N 2 ) atmosphere or an oxygen (O 2 ) atmosphere with the two silicon wafers 11 and 12 bonded together.
100 to 1200 ° C, preferably 1100 to 1150 ° C
The temperature range is 1 to 10 hours, preferably 2 to 5 hours. This causes covalent bonding of silicon at the bonding interface,
The two silicon wafers 11 and 12 are bonded together, and the crystal lattices of both are integrated. As shown in FIG. 1 (d),
After the two integrated silicon wafers 11 and 12 are left to cool to room temperature, 400 to 900 ° C., preferably 700 to 900 ° C., in the same atmosphere as the heat treatment atmosphere.
More preferably, the heat treatment is performed again in the temperature range of 800 to 900 ° C. This heat treatment time may be obtained from the relationship between the target SOI layer thickness and the oxygen diffusion distance, but is usually 2
Time is preferable. As shown in FIG. 1 (e), after the re-heat treatment, the second silicon wafer 12 serving as a silicon substrate is ground with a grindstone, and then polished with a polishing cloth to have a thickness of about 1 to 10 μm.
Processed into a thin film with a thickness of. As a result, the thickness is about 1-10μ
The SOI layer 12a for device formation of m is obtained on the insulating layer 13.
【００１２】[0012]
【作用】接合した２枚のシリコンウェーハを１１００〜
１２００℃で１〜１０時間熱処理すると、２枚のシリコ
ンウェーハ内の格子間酸素原子が外方拡散して、２枚の
シリコンウェーハ中の酸素濃度を低減させる。この状態
の２枚のシリコンウェーハを４００〜９００℃の温度範
囲で再度熱処理すると、絶縁層１３であるシリコン酸化
層、或いはＳＯＩ層１２ａとの界面がゲッタリングサイ
ト（源）として機能し、ＳＯＩ層１２ａ中の酸素が絶縁
層１３との接合界面に向かって拡散し、ＳＯＩ層１２ａ
と絶縁層１３との界面における酸素の固溶限を更に低下
させる。再度の熱処理の温度が４００℃未満では、上記
固溶限は低下するけれども、次の式（１）及び（２）の
関係から格子間酸素原子の拡散距離は短くなり、絶縁層
１３近傍の極めて微小な範囲のＳＯＩ層１２ａ内の酸素
のみが絶縁層１３に届くだけであって、その濃度は低減
しない。 Ｌ ＝ （Ｄ・ｔ）1/2 …… （１） Ｄ ＝ Ｂ・ｅｘｐ（−Ｅ／ｋ・Ｔ）…… （２） ここで、Ｌは拡散距離、Ｄは拡散係数、ｔは時間、Ｂは
定数、Ｅは活性化エネルギー、ｋはボルツマン定数であ
る。代表的な値として、Ｂ＝０．１３［ｃｍ2／ｓ］、
Ｅ ＝ ２．５３［ｅＶ］が知られている。また９００
℃を越えると、酸素の固溶限は１０17／ｃｍ3程度まで
上昇してしまうため、ＳＯＩ層１２ａの酸素濃度はやは
り低減せず、上記再熱処理の温度範囲が決められる。[Operation] Two bonded silicon wafers 1100-
When heat treatment is performed at 1200 ° C. for 1 to 10 hours, interstitial oxygen atoms in the two silicon wafers are diffused outward, and the oxygen concentration in the two silicon wafers is reduced. When the two silicon wafers in this state are heat-treated again in the temperature range of 400 to 900 ° C., the interface with the silicon oxide layer which is the insulating layer 13 or the SOI layer 12a functions as a gettering site (source), and the SOI layer Oxygen in 12a diffuses toward the bonding interface with the insulating layer 13, and the SOI layer 12a
The solid solubility limit of oxygen at the interface between the insulating layer 13 and the insulating layer 13 is further reduced. When the temperature of the second heat treatment is less than 400 ° C., the solid solubility limit is lowered, but the diffusion distance of interstitial oxygen atoms is shortened from the relationship of the following equations (1) and (2), and the extremely near the insulating layer 13 is extremely reduced. Only oxygen in the SOI layer 12a in a minute range reaches the insulating layer 13, and the concentration thereof does not decrease. L = (D · t) 1/2 (1) D = B · exp (−E / k · T) (2) where L is the diffusion distance, D is the diffusion coefficient, t is the time, B is a constant, E is an activation energy, and k is a Boltzmann constant. As a typical value, B = 0.13 [cm 2 / s],
E = 2.53 [eV] is known. Again 900
When the temperature exceeds 0 ° C., the solid solution limit of oxygen rises to about 10 17 / cm 3, so that the oxygen concentration of the SOI layer 12a still does not decrease, and the temperature range of the above-mentioned reheat treatment is determined.
【００１３】[0013]
【実施例】次に、本発明の実施例を図面に基づいて詳し
く説明する。 ＜実施例１＞図１（ａ）に示すように、それぞれ直径５
インチで厚さ６２５μｍの第１シリコンウェーハ１１及
び第２シリコンウェーハ１２を用意した。第２シリコン
ウェーハ１２の片面にはこのウェーハを湿潤酸素（ｗｅ
ｔＯ2）雰囲気中、１０００℃で３時間熱処理してシリ
コン酸化層からなる絶縁層１３を形成した。２枚のシリ
コンウェーハ１１，１２をＨ2Ｏと比重１．１のＨ2Ｏ2
水溶液と比重０．９のＮＨ4ＯＨの水溶液とをＨ2Ｏ：Ｈ
2Ｏ2：ＮＨ4ＯＨ＝７：２：１の容量比で混合して調製
したＳＣ１（Standard Cleaning 1）の洗浄液で洗浄し
て２枚のシリコンウェーハの表面を活性化した。Embodiments of the present invention will now be described in detail with reference to the drawings. <Example 1> As shown in FIG.
A first silicon wafer 11 and a second silicon wafer 12 having a thickness of 625 μm in inches were prepared. On one side of the second silicon wafer 12, this wafer is wet oxygen (we
Heat treatment was performed at 1000 ° C. for 3 hours in an atmosphere of tO 2 ) to form an insulating layer 13 made of a silicon oxide layer. Two silicon wafers 11 and 12 are combined with H 2 O and H 2 O 2 having a specific gravity of 1.1.
An aqueous solution and an aqueous solution of NH 4 OH having a specific gravity of 0.9 are added to H 2 O: H.
The surfaces of two silicon wafers were activated by cleaning with a cleaning solution of SC1 (Standard Cleaning 1) prepared by mixing at a volume ratio of 2 O 2 : NH 4 OH = 7: 2: 1.
【００１４】図１（ｂ）に示すように、２枚のシリコン
ウェーハ１１，１２を絶縁層１３を介して重ね合せ接合
した。次いで図１（ｃ）に示すように室温から８００℃
に設定された熱処理炉中に１０〜１５ｃｍ／分の速度で
挿入し、窒素雰囲気中で８００℃から１０℃／分の速度
で昇温し、１１００℃に達したところで５時間維持し、
次いで４℃／分の速度で降温し、８００℃まで冷却した
後、１０〜１５ｃｍ／分の速度で炉から室温中に取り出
した。続いて図１（ｄ）に示すように、同じ窒素雰囲気
中で同様に昇温し、９００℃に達したところで２時間維
持し、次いで同様に降温した。 更に図１（ｅ）に示す
ように、シリコンウェーハ１２の表面を砥石で研削し、
続いて柔らかい研磨布で研磨し、絶縁層１３上に厚さ１
〜１０μｍのＳＯＩ層１２ａを形成した。As shown in FIG. 1 (b), two silicon wafers 11 and 12 were superposed and bonded via an insulating layer 13. Then, as shown in FIG. 1 (c), room temperature to 800 ° C.
It was inserted into the heat treatment furnace set at 10 to 15 cm / min, the temperature was raised from 800 ° C. to 10 ° C./min in a nitrogen atmosphere, and the temperature was maintained at 1100 ° C. for 5 hours.
Then, the temperature was lowered at a rate of 4 ° C./min, the temperature was cooled to 800 ° C., and the sample was taken out of the furnace at room temperature at a rate of 10 to 15 cm / min. Subsequently, as shown in FIG. 1D, the temperature was similarly raised in the same nitrogen atmosphere, and when the temperature reached 900 ° C., the temperature was maintained for 2 hours, and then the temperature was similarly lowered. Further, as shown in FIG. 1 (e), the surface of the silicon wafer 12 is ground with a grindstone,
Then, it is polished with a soft polishing cloth to a thickness of 1 on the insulating layer 13.
An SOI layer 12a having a thickness of 10 μm was formed.
【００１５】＜比較例１＞図１（ｃ）に示す熱処理にお
いて１１００℃で２時間維持し、かつ図１（ｄ）に示す
再熱処理を省略した以外は、実施例１と同様にして絶縁
層１３上にＳＯＩ層１２ａを形成した。Comparative Example 1 An insulating layer was prepared in the same manner as in Example 1 except that the heat treatment shown in FIG. 1C was maintained at 1100 ° C. for 2 hours and the reheat treatment shown in FIG. 1D was omitted. The SOI layer 12 a was formed on the layer 13.
【００１６】＜評価＞実施例１の研削研磨加工した半導
体基板と、比較例１の研削研磨加工した半導体基板につ
いて、それぞれ二次イオン質量分析（Secondary Ion Ma
ss Spectroscopy, ＳＩＭＳ）法にてそれぞれのＳＯＩ
層１２ａ及び絶縁層１３の一部に固溶している格子間酸
素濃度を測定した。これらのＳＩＭＳ法による測定結果
を表１に示す。<Evaluation> Secondary ion mass spectrometry (Secondary Ion Ma) was performed on each of the ground and polished semiconductor substrate of Example 1 and the ground and polished semiconductor substrate of Comparative Example 1.
ss Spectroscopy (SIMS) method for each SOI
The concentration of interstitial oxygen dissolved in part of the layer 12a and the insulating layer 13 was measured. Table 1 shows the measurement results by the SIMS method.
【００１７】[0017]
【表１】 [Table 1]
【００１８】ＳＩＭＳ法による測定結果及び表１から、
比較例１の接合界面における固溶限が１０17／ｃｍ3を
越えているのに対して、実施例１の接合界面における固
溶限は１０17／ｃｍ3以下であって、しかも絶縁層１３
の界面から７．５μｍの全領域のＳＯＩ層１２ａの酸素
濃度は０．５〜１．０×１０17／ｃｍ3の範囲にあるこ
とが判明した。From the measurement results by the SIMS method and Table 1,
The solid solubility limit at the bonding interface of Comparative Example 1 exceeds 10 17 / cm 3 , whereas the solid solubility limit at the bonding interface of Example 1 is 10 17 / cm 3 or less, and the insulating layer 13 is also present.
It was found that the oxygen concentration of the SOI layer 12a in the entire region of 7.5 μm from the interface was in the range of 0.5 to 1.0 × 10 17 / cm 3 .
【００１９】[0019]
【発明の効果】以上述べたように、本発明の半導体基板
の製造方法によれば、接合した２枚のシリコンウェーハ
を１１００〜１２００℃の温度範囲で１〜１０時間熱処
理して貼り合わせた後に４００〜９００℃で再度熱処理
を行うことにより、ウェーハ中の酸素濃度を低下させた
後、絶縁層とＳＯＩ層との界面での酸素の固溶限を低下
させ、絶縁層に隣接するＳＯＩ層の全域の酸素濃度を１
０17／ｃｍ3以下にすることができ、結果として酸素に
起因する結晶欠陥の発生が抑制された高品質のデバイス
形成用のＳＯＩ層が絶縁層上に得られる。As described above, according to the method for manufacturing a semiconductor substrate of the present invention, two bonded silicon wafers are heat-treated at a temperature range of 1100 to 1200 ° C. for 1 to 10 hours and then bonded. By performing heat treatment again at 400 to 900 ° C., the oxygen concentration in the wafer is reduced, and then the solid solubility limit of oxygen at the interface between the insulating layer and the SOI layer is reduced, so that the SOI layer adjacent to the insulating layer is reduced. The oxygen concentration of the whole area is 1
0 17 / cm 3 can be below, the results SOI layer for device formation of high quality suppressed occurrence of crystal defects due to oxygen is obtained on the insulating layer as.
【００２０】また２枚のシリコンウェーハはＣＺ成長の
シリコンウェーハであるため、本発明の半導体基板は特
開平２−４６７７０号公報の半導体基板と異なり、接合
時にスリップを生じない。これにより本発明の半導体基
板は機械的強度が十分高く、量産性に優れる特長もあ
る。Further, since the two silicon wafers are CZ-grown silicon wafers, the semiconductor substrate of the present invention does not cause a slip at the time of bonding, unlike the semiconductor substrate disclosed in Japanese Patent Laid-Open No. 2-46770. As a result, the semiconductor substrate of the present invention has features of sufficiently high mechanical strength and excellent mass productivity.
【図１】本発明実施例の半導体基板の製造方法を示す部
分断面図。FIG. 1 is a partial sectional view showing a method for manufacturing a semiconductor substrate according to an embodiment of the present invention.
１１ 第１シリコンウェーハ １２ 第２シリコンウェーハ １２ａ ＳＯＩ層 １３ 絶縁層（シリコン酸化層） 11 first silicon wafer 12 second silicon wafer 12a SOI layer 13 insulating layer (silicon oxide layer)
Claims (2)
形成され、前記絶縁層(13)上にデバイス形成用のＳＯＩ
層(12a)が形成され、前記シリコンウェーハ(11)の酸素
濃度が１．０〜１．５×１０18／ｃｍ3の範囲にある半
導体基板において、 前記ＳＯＩ層(12a)の酸素濃度が０．５〜１．０×１０
17／ｃｍ3であって、かつ前記シリコンウェーハ(11)が
ＣＺ法で引上げたシリコン結晶棒から作製されたシリコ
ンウェーハからなり、前記ＳＯＩ層(12a)がＣＺ法で引
上げたシリコン結晶棒から作製されたシリコンウェーハ
を薄膜化して形成されたことを特徴とする半導体基板。1. An insulating layer (13) is formed on a silicon wafer (11), and SOI for device formation is formed on the insulating layer (13).
In the semiconductor substrate in which the layer (12a) is formed and the oxygen concentration of the silicon wafer (11) is in the range of 1.0 to 1.5 × 10 18 / cm 3 , the oxygen concentration of the SOI layer (12a) is 0. 0.5 to 1.0 x 10
17 / cm 3 , and the silicon wafer (11) is made of a silicon crystal rod made by the CZ method, and the SOI layer (12a) is made of a silicon crystal rod made by the CZ method. A semiconductor substrate formed by thinning the formed silicon wafer.
れぞれ作製された第１シリコンウェーハ(11)と第２シリ
コンウェーハ(12)とを絶縁層(13)を介して接合し、前記
接合した第１及び第２シリコンウェーハ(11,12)を熱処
理して貼り合わせた後、前記第１シリコンウェーハ(11)
又は第２シリコンウェーハ(12)を所定の厚さに研削研磨
してデバイス形成用のＳＯＩ層(12a)とする半導体基板
の製造方法において、 前記接合した第１及び第２シリコンウェーハ(11,12)を
１１００〜１２００℃の温度範囲で１〜１０時間熱処理
して貼り合わせた後、研削前に４００〜９００℃の温度
範囲で再度熱処理することを特徴とする半導体基板の製
造方法。2. A first silicon wafer (11) and a second silicon wafer (12), each made of a silicon crystal rod pulled up by the CZ method, are bonded together via an insulating layer (13), and the bonded first silicon wafer (11) and the second silicon wafer (12) are bonded together. After the first and second silicon wafers (11, 12) are heat-treated and bonded together, the first silicon wafer (11)
Alternatively, in a method for manufacturing a semiconductor substrate, in which a second silicon wafer (12) is ground and polished to a predetermined thickness to form an SOI layer (12a) for device formation, the bonded first and second silicon wafers (11, 12) Is heat-treated in the temperature range of 1100 to 1200 ° C. for 1 to 10 hours to be bonded, and then heat-treated again in the temperature range of 400 to 900 ° C. before grinding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21104594A JP3262190B2 (en) | 1994-09-05 | 1994-09-05 | Method of manufacturing SOI substrate and SOI substrate manufactured by this method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21104594A JP3262190B2 (en) | 1994-09-05 | 1994-09-05 | Method of manufacturing SOI substrate and SOI substrate manufactured by this method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0878646A true JPH0878646A (en) | 1996-03-22 |
| JP3262190B2 JP3262190B2 (en) | 2002-03-04 |
Family
ID=16599472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21104594A Expired - Fee Related JP3262190B2 (en) | 1994-09-05 | 1994-09-05 | Method of manufacturing SOI substrate and SOI substrate manufactured by this method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3262190B2 (en) |
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| KR100592965B1 (en) * | 1998-06-02 | 2006-06-23 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing method of SOI substrate |
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1994
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|---|---|---|---|---|
| FR2782572A1 (en) * | 1998-04-17 | 2000-02-25 | Nec Corp | "SILICON-SUR-INSULATING" (SOI) SUBSTRATE AND MANUFACTURING METHOD THEREOF |
| FR2834821A1 (en) * | 1998-04-17 | 2003-07-18 | Nec Corp | "SILICON-SUR-INSULATOR" (SOI) SUBSTRATE AND MANUFACTURING METHOD THEREOF |
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| JP2006041135A (en) * | 2004-07-26 | 2006-02-09 | Sumitomo Bakelite Co Ltd | Electronic device and manufacturing method thereof |
| WO2007072624A1 (en) | 2005-12-19 | 2007-06-28 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi substrate, and soi substrate |
| US7749861B2 (en) | 2005-12-19 | 2010-07-06 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI substrate and SOI substrate |
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| US9379239B2 (en) | 2012-11-07 | 2016-06-28 | Sony Corporation | Semiconductor device, method of manufacturing semiconductor device, and antenna switch module |
| US9537005B2 (en) | 2012-11-07 | 2017-01-03 | Sony Corporation | Semiconductor device, method of manufacturing semiconductor device, and antenna switch module |
| US10553550B2 (en) | 2012-11-07 | 2020-02-04 | Sony Corporation | Semiconductor device, method of manufacturing semiconductor device, and antenna switch module |
| JP2016111337A (en) * | 2014-10-09 | 2016-06-20 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Method for manufacturing semiconductor wafer and semiconductor device having low concentration of interstitial oxygen |
| US9728395B2 (en) | 2014-10-09 | 2017-08-08 | Infineon Technologies Ag | Method for manufacturing a semiconductor wafer, and semiconductor device having a low concentration of interstitial oxygen |
| US10014400B2 (en) | 2014-10-09 | 2018-07-03 | Infineon Technologies Ag | Semiconductor device having a defined oxygen concentration |
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