JPH0870100A - Ferroelectric capacitor manufacturing method - Google Patents

Abstract

(57) Abstract: A method for manufacturing a capacitor provided with a ferroelectric film is provided. A low dielectric pattern is formed on a semiconductor substrate.
After forming 0, the capacitor lower electrode 74 and the material layer are sequentially formed. After the material layer and the capacitor lower electrode 74 are sequentially polished by a chemical mechanical polishing (CMP) method to pattern the capacitor lower electrode 74, a ferroelectric film 78 and an upper electrode 80 are sequentially formed. Accordingly, the capacitor lower electrode 74 can be easily patterned, and malfunction of the device due to the coupling capacitance between the capacitor and the adjacent capacitor can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor for a semiconductor device, and more particularly to a method of manufacturing a capacitor having a ferroelectric film.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memor)
y) Due to the increased integration of the device, many methods have been proposed to increase the capacitance within a limited cell area, but usually they can be classified into the following three types. That is, (1) a method of thinning the dielectric film, (2) a method of increasing the effective area of the dielectric film of the capacitor, and (3) a method of using a substance having a large dielectric constant.

Of these, the first method is that, when the thickness of the dielectric film is reduced to 100 Å or less, the reliability is deteriorated by the Fowler-Nordheim current.
It is difficult to apply to a large capacity memory device. Second
The method (1) also has a drawback that the process is complicated and the cost is high because a capacitor having a three-dimensional structure is manufactured.

Therefore, recently, as a third method, a ferroelectric substance having a perovskite structure, for example, PZT (PbZrTiO ₃ ) is used.
It has been proposed to use BST (BaSrTiO ₃ ) or the like as a dielectric film. The ferroelectric film is an existing oxide film, silicon nitride film or tantalum pentoxide (Ta ₂ O 3
₅ ) Different from a film, it refers to a substance having a spontaneous polarization phenomenon and a dielectric constant of usually several hundred to 1,000. When such a ferroelectric is used as a dielectric film, the equivalent-oxide film can be thinned to 10 Å or less even if the ferroelectric is formed into a thick film of several hundred Å.

[0005]

When PZT, BST or the like is used as a dielectric film, the material forming the electrode of the capacitor is such that a perovskite structure can be formed on the electrode. It is necessary to satisfy the conditions that a low dielectric film is not formed at the interface, that constituent atoms of silicon and the ferroelectric can be prevented from interdiffusing, and that patterning is easy. However, currently PZT
Platinum (Pt), which is most frequently used as a capacitor electrode material such as a BST dielectric film, satisfies the above-mentioned conditions (1) to (4) but does not satisfy the conditions (1) to (3). This is because platinum is an extremely hard heat-resistant metal, so it is difficult to react with other chemical substances and is not easily etched by the reactive ion etching method.

Furthermore, a PZT or BST dielectric film, etc.
In order to apply to a DRAM of 56 Mb class or higher, it is desirable to prevent malfunction of the device due to the coupling capacitance between these capacitors, considering that the distance between the capacitors and the adjacent capacitors gradually decreases. In order to prevent such malfunction, a method of forming an oxide spacer on the sidewall of the capacitor has been proposed.
A cross section of a memory cell having a capacitor according to the above method is shown in FIG.

Referring to FIG. 1, the field oxide film 12 is formed.
After forming the transistor having the drain region 18a, the source region 18b and the gate electrode 16 and the lower bit line 20 connected to the drain region 18a on the semiconductor substrate 10 divided into the active region and the isolation region by An insulating layer is formed on the entire surface of the object. Next, after forming a contact hole exposing the source region 18b, the inside of the contact hole is filled with a conductive material to form a conductive plug 22. Next, a barrier conductive layer 24 and a capacitor lower electrode 26 made of platinum are sequentially formed on the resultant structure, and subsequently an oxide spacer 28 is formed on the sidewalls of the barrier conductive layer 24 and the lower electrode 26. Then, a ferroelectric film 30 made of BST and a capacitor upper electrode 32 are sequentially formed on the resultant structure, and then an upper bit line 34 and an aluminum wiring 36 are sequentially formed by a normal manufacturing method.

According to the conventional method described above, not only is it difficult to pattern platinum, but a coupling capacitance is generated between the capacitor and the adjacent capacitor to cause a malfunction of the device. here,
The coupling capacitance Ccp is expressed by the following equation (1). 1 / Ccp = 1 / Cox ₁ + 1 / Cox ₂ + 1 / Cfe = 2 / Cox + 1 / Cfe (1) where Cfe is the capacitance generated in the ferroelectric film, and Cox ₁ and Cox ₂ Is the oxidation capacitance as shown in FIG. 1 and is assumed to be identical to Cox, for example. As a result, 1 / Ccp = (2Cfe + Cox) / CoxCfe (2) or Ccp = CoxCfe / (2Cfe + Cox) (3).

Next, assuming that Cfe is larger than Cox, Ccp ≈ Cox / 2 (4), and therefore Ccp ≈ (ε _ox / 2) (Aox / dox) (5) ).

Where Aox is the area of the contact region, dox is the thickness of the oxide spacer, and ε _ox is the dielectric constant of oxide. Assuming that the storage node is a cylinder, the area Ao where the oxide spacer contacts the storage node
x is given by "height of storage node x circumference of storage node". Therefore, when the integration degree of the memory cell is further improved to increase the area Aox or the spacer thickness dox is reduced, the problem of the malfunction of the operation due to the coupling capacitance becomes more serious.

It is an object of the present invention to provide a method of manufacturing a capacitor having a ferroelectric film, which can solve the above-mentioned problems of the conventional method.

[0012]

In order to achieve the above object, the present invention provides a step of forming a low dielectric pattern on a semiconductor substrate, and a lower electrode on the resultant product on which the low dielectric pattern is formed. And sequentially forming the material layer, and sequentially polishing the material layer and the lower electrode by a chemical mechanical polishing method to pattern the lower electrode so that the lower electrode remains between the low dielectric pattern. A method of manufacturing a capacitor, comprising: a step of forming a ferroelectric film on the patterned result of the lower electrode; and a step of forming the upper electrode on the ferroelectric film. I will provide a.

According to a preferred embodiment of the present invention, as a material forming the low dielectric pattern, a high temperature oxide (Hi
gh Temperature Oxide; HTO), USG (Undoped Si)
licaGlass) and BPSG (Boron Phosphorous doped)
Use one selected from the Silica Glass group,
As a material forming the ferroelectric film, PZT (PbZrTi
O ₃ ), BST (BaSrTiO ₃ ), SrTiO ₃ , BaTiO ₃ , PbTiO ₃ and Bi ₄ Ti ₃ O ₁₂ It is desirable to use any one selected from the group. Platinum (Pt), tantalum (Ta), iridium (I)
It is desirable to use a heat-resistant metal such as r) or ruthenium (Ru) or a conductive oxide such as ruthenium oxide (RuO ₂ ) or iridium oxide (IrO ₂ ). Spin-On Glass (hereinafter referred to as “substance” as a substance forming the substance layer)
SOG ") is preferred.

The chemical mechanical polishing (Chemical Mecha
It is preferable that polishing of the material layer and the lower electrode by a method of nical polishing (hereinafter referred to as “CMP”) is performed until the surface of the low dielectric pattern is exposed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the accompanying drawings. 2 to 6 are cross-sectional views for sequentially explaining a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention. Figure 2
A step of forming the contact hole 67 and the conductive plug 68 on the semiconductor substrate 50 is shown. Field oxide film 5
A gate oxide film 54 and a gate electrode 56 are formed on the semiconductor substrate 50 divided into active regions and isolation regions by 2. Then, by using the gate electrode 56 as an ion implantation mask to implant impurity ions, the drain region 60a and the source region 60b are formed in the substrate 50. Next, a first insulating film 58 is formed on the resultant structure, and the drain region 60a is exposed by anisotropically etching the first insulating film 58 and capped with a second insulating film 64 on the drain region 60a. The bit line 62 is formed. Then
A planarization layer 66 is formed on the entire surface of the resultant structure in order to planarize the surface of the substrate 50 that is bent due to the formation of the transistor and the bit line 62. Next, the planarization layer 6 laminated on the source region 60b by the photolithography process.
6 and the first insulating film 58 are etched to form a contact hole 67 for connecting the lower electrode of the capacitor to be formed later to the source region 60b. Then, a conductive material, for example, polysilicon doped with impurities is deposited on the substrate 50 in which the contact hole 67 is formed, and then etched back to fill the inside of the contact hole 67 with the conductive material to form a conductive plug 68. To do.

FIG. 3 shows a step of forming the low dielectric pattern 70. A material having a low dielectric constant, for example, an oxide of several hundreds to 2000 is formed on the resultant product having the conductive plug 68 formed therein.
After being deposited to a thickness of about Å, the low dielectric pattern 70 is formed by patterning this with a photo-etching process. Here, the thickness of the low dielectric pattern 70 can be adjusted according to the thickness of the capacitor lower electrode.
Oxide series such as O, USG and BPSG and other low dielectric constant materials can be used.

FIG. 4 shows the steps of forming the barrier conductive layer 72, the capacitor lower electrode 74 and the material layer 76. A conductive material, for example, titanium (Ti) or titanium nitride (TiN), is formed on the resultant structure on which the low dielectric pattern 70 is formed.
Are deposited by a sputtering method to form a barrier conductive layer 72. Then, a refractory conductive material, for example, platinum (Pt) is deposited on the barrier conductive layer 72 by a sputtering method to form a capacitor lower electrode 74, and then SO 2 is formed thereon.
The material layer 76 is formed by applying G thickly. At this time, the surface of the resultant product is flattened by the material layer 76 made of SOG.

FIG. 5 illustrates the material layer 76, the bottom electrode 74 and the lower electrode 74 until the surface of the low dielectric pattern 70 is exposed using the CMP method, for example, until the low dielectric pattern 70 is polished to less than about 100Å. A step of patterning the capacitor lower electrode 74 by sequentially polishing the barrier conductive layer 72 is shown. FIG. 6 shows a step of forming the ferroelectric film 78 and the capacitor upper electrode 80. A material having a ferroelectric constant, for example, BST, is sputtered on the patterned result of the lower electrode 74, chemical vapor deposition (CV).
D) method, liquid source CVD method or sol-gel method is used to deposit the ferroelectric film 78 of the capacitor. Then, a conductive material such as platinum (Pt) is deposited on the ferroelectric film 78 to form the upper electrode 80 of the capacitor.

In the capacitor manufactured according to one embodiment of the present invention, the low dielectric pattern 70 fills the entire area between the capacitor and the adjacent capacitor. When the distance between the capacitor and the adjacent capacitor is indicated by d, the coupling capacitance (Ccp) is expressed by the following equation (6). Ccp = ε (A / d) (6) Here, ε is a dielectric constant, and A is the area of the storage node according to one embodiment of the present invention, and the area of the coupling capacitor according to the conventional method. It is the same as (Aox).
However, the thickness d of the coupling capacitor according to the present invention is
Is a general expected value of 1 Giga DRAM, assuming that the spacing between storage nodes is 0.2 μm and the thickness of the oxide spacer is 500 Å, the thickness obtained by the conventional method is
At least 4 times larger than dox. Therefore, since the coupling capacitance according to the present invention is more than twice as small as that of the conventional method, malfunction of the device can be prevented.

[0020]

As described above, according to the present invention,
Since the lower electrode of the capacitor is patterned using the CMP method, the lower electrode can be easily patterned as compared with the conventional method. Further, since both the capacitor and the region between the adjacent capacitors are filled with the low dielectric pattern, malfunction of the device due to coupling capacitance can be prevented.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor memory device having a ferroelectric capacitor according to a conventional method.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention.

[Explanation of symbols]

 50 semiconductor substrate 52 field oxide film 54 gate oxide film 56 gate electrode 58 first insulating film 60a drain region 60b source region 62 bit line 64 second insulating film 66 flattening layer 67 contact hole 68 conductive plug 70 low dielectric pattern 72 Barrier conductive layer 74 Capacitor lower electrode (lower electrode) 76 Material layer 78 Ferroelectric film 80 Upper electrode

Claims (7)

[Claims] 1. A method of forming a low dielectric pattern on a semiconductor substrate, sequentially forming a lower electrode and a material layer on the resultant product having the low dielectric pattern formed thereon, and chemical mechanical polishing (CMP). Patterning the lower electrode so that the lower electrode remains between the low dielectric patterns by sequentially polishing the material layer and the lower electrode by a method, and patterning the lower electrode on the patterned product. A method of manufacturing a capacitor, comprising: forming a ferroelectric film; and forming the upper electrode on the ferroelectric film. 2. The method of manufacturing a capacitor according to claim 1, wherein any one selected from the group consisting of HTO, USG and BPSG is used as a material forming the low dielectric pattern. 3. The substance constituting the ferroelectric film,
PZT (PbZrTiO ₃ ), BST (BaSrTiO ₃ ), SrTiO ₃ , BaTi
2. The method for manufacturing a capacitor according to claim 1, wherein any one selected from the group consisting of O ₃ , PbTiO ₃ and Bi ₄ Ti ₃ O ₁₂ is used. 4. The method of manufacturing a capacitor according to claim 1, wherein a refractory metal or a conductive oxide is used as a material forming the lower electrode. 5. The heat resistant metal is platinum (Pt), tantalum (Ta), iridium (Ir), ruthenium (Ru).
5. The method for manufacturing a capacitor according to claim 4, wherein the capacitor is formed by using any one of them. 6. The conductive oxide is ruthenium oxide (Ru).
5. The method for manufacturing a capacitor according to claim 4, wherein O ₂ ) or iridium oxide (IrO ₂ ) is used. 7. The method of manufacturing a capacitor according to claim 1, wherein spin-on glass (SOG) is used as a material forming the material layer.