JPH0862296A - Logic comparator - Google Patents

Abstract

PURPOSE: To shorten the required time of a test of classifying the difference signal output time with respect to an input signal, by providing a generator and a comparator for timing, comparing the output of a flip-flop and an expected value, and providing a comparison-result holding circuit, which holds the output of the level of the expected value. CONSTITUTION: This logic comparator is constituted of the following parts. A timing comparator 22 makes the signal outputted from a level comaprator 11, which determines H and L levels of the output signal Dout of DUT 10 possible to perform timing comparison, and detects whether the output of the gate is at H level or L level at the comparison timing when the comparison timing signal is generated. A timing generator 23 generates the comparison timing signal. An expected-value-level comaprator 14 compares the output of the comparator 22 and the expected value. A comparison-result holding circuit 15 holds the result of the comparison with the expected value level with the comparison timing signal. When the number of expandable parts is N, the timing of the classification based on the difference of the signal output time with respect to the input signal can be shortened to the time of 1/N in comparison with the conventional circuit, and the testing time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical comparator for performing classification according to a difference in signal output time with respect to an input signal of a device under test.

[0002]

2. Description of the Related Art As shown in FIG. 3, when an input signal is applied to a device under test (DUT) 10 in a basic period T, each DUT 10 outputs with a delay time that varies from device to device. Generate a signal. Therefore,
The DUT 10 may be classified according to the width of the delay time. Here, for a certain input signal, the output signal changes from the H level to the L level, and the change points are DUT1 during the time T1, DUT2 during the time T2, DUT3 during the time T3, DUT during time T4
Suppose there was 4.

In order to distinguish this difference in output time, the circuit of FIG. 4 has been conventionally used. The conventional circuit of FIG. 4 includes a level comparator 11 that determines the H level and the L level of the DUT 10 output signal Dout, and a gate that controls the signal output from the level comparator 11 with a comparison control signal that enables timing comparison. Signal (STROB)
Timing comparator 12 that detects whether the output of the gate is H level or L level when the occurrence of the above occurs, a timing generator 13 that generates STROB, and an expected value level comparator that compares the output signal of the timing comparator 12 with an expected value. 14. The comparison result holding circuit 15 holds the comparison result with the expected value level at the rear end of the STROB signal.

FIG. 5 shows that the output signal changes from the H level to the L level for a certain input signal, and the change point is the time T.
FIG. 6 is a test timing diagram for DUT2 lying between 2; The output Dout of the DUT2 changes from the H level to the L level during the time T2. The output Dout is compared with the comparison voltage VO by the level comparator 11, and is delayed by the propagation delay time of the level comparator 11 to change from the H level to the L level.

STR which is the output of the timing generator 13.
In the first basic cycle T, the OB changes from the L level to the H level at the rear end of the time T1, and changes from the H level to the L level at the rear end of the first basic cycle T. STRO
At the rising edge of B, the clear terminal of the flip-flop in the timing comparator 12 is at H level because the output of the level comparator 11 and the comparison control signal are at H level, and the output of the flip-flop, that is, the timing comparator 1
The output of 2 holds H level. In this example, the expected value is L level and the output of the expected value level comparator 14 is H level, so the comparison result holding circuit 15 is provided at the rear end of STROB.
Is held at the H level. Since the comparison result H level indicates disagreement with the expected value, it becomes FAIL in this case.

In the subsequent second basic cycle T, STR
OB changes from the L level to the H level at the rear end of the time T2, and changes from the H level to the L level at the rear end of the second basic cycle T. At the rise of STROB, the clear terminal of the flip-flop in the timing comparator 12 is at the L level because the output of the level comparator 11 is at the L level and the comparison control signal is at the H level. The output of the container 12 changes from H level to L level. The expected value is the L level, and the output of the expected value level comparator 14 becomes the L level.
The comparison result holding circuit 15 holds the L level at the rear end of OB. Since the comparison result L level indicates a match with the expected value, it is PASS in this case.

In the subsequent third basic cycle T, STR
OB changes from the L level to the H level at the rear end of time T3, and changes from the H level to the L level at the rear end of the third basic cycle T. At the rise of STROB, the clear terminal of the flip-flop in the timing comparator 12 becomes 2
Like the basic cycle T of the first time, it is at L level,
The output of the timing comparator 12 changes from H level to L level. Since the output of the expected value level comparator 14 becomes L level, the comparison result holding circuit 15 holds L level at the rear end of STROB. Since the comparison result L level indicates a match with the expected value, it is PASS in this case.

In the following fourth basic cycle T, STR
OB changes from the L level to the H level at the rear end of the time T4, and changes from the H level to the L level at the rear end of the fourth basic cycle T. At the rise of STROB, the clear terminal of the flip-flop in the timing comparator 12 becomes 2
Like the basic cycle T of the first time, it is at L level,
The output of the timing comparator 12 changes from H level to L level. Since the output of the expected value level comparator 14 becomes L level, the comparison result holding circuit 15 holds L level at the rear end of STROB. Since the comparison result L level indicates a match with the expected value, it is PASS in this case.

Since the change point of the output signal from the H level to the L level of DUT1 is during time T1, DUT3 is during time T3, and DUT4 is during time T4, the first, second, and In the third and fourth basic cycles T, the following test results can be obtained, and DU
Classification can be performed according to the difference in signal output time of T10. DUT1 DUT2 DUT3 DUT4 1st PASS FAIL FAIL FAIL 2nd PASS PASS FAIL FAIL 3rd PASS PASS PASS 4th PASS PASS PASS

[0010]

As described above, in the conventional circuit, the basic period T is executed several times, and ST is executed each time.
The rising timing of ROB is changed, and classification is performed according to the difference in signal output time of DUT 10 based on the comparison result for each time. Focusing only on this part of the test, in the case of the above conventional example, T × 4 time is required for classification. As described above, in the circuit of the conventional method, when an attempt is made to classify by the difference in the signal output time of the DUT, the STR
It is necessary to change the OB generation timing to execute the test several times, and there is a drawback that the test time increases. It is an object of the present invention to realize a logical comparator that performs classification according to a difference in signal output time with respect to an input signal of a device under test in a short test time.

[0011]

In order to achieve the above object, the present invention provides a timing generator for generating a plurality of comparison timing signals in classification according to a difference in signal output time with respect to an input signal of a device under test. It is provided. Each of the comparison timing signals is input to each clock terminal, and the output of the device under test is input to the clear terminal through the level comparator and the gate controlled by the comparison control signal. A timing comparator is installed. Then, a plurality of expected value level comparators for comparing the outputs of the plurality of flip-flops and expected values are provided. The outputs of the plurality of expected value level comparators are held in the plurality of comparison result holding circuits at the trailing end of the comparison timing signal. In the logical comparator configured as described above, the number of classifications depending on the difference in signal output time with respect to the input signal can be arbitrarily set by increasing or decreasing the expandable section.

[0012]

In the logical comparison circuit configured as described above, a plurality of comparison timing signals are generated during one basic period T, and classification can be performed according to a plurality of signal output time differences with respect to an input signal. Therefore, if the number of classifications is N, the classification time can be shortened to 1 / N as compared with the conventional circuit.

[0013]

EXAMPLE As shown in FIG. 3, in the basic period T, D
When an input signal is applied to the UT10, the output signal of the DUT10 changes from the H level to the L level, and the change point thereof is the DUT1 located between the time T1 and the DU located between the time T2.
It is assumed that there is a DUT3 located between T2 and time T3 and a DUT4 located between time T4.

In order to distinguish this difference in output time, the circuit of FIG. 1 is used in the present invention. The circuit of FIG.
The UT10 includes a level comparator 11 that determines the H level and the L level of the output signal Dout, and a gate that controls the signal output from the level comparator 11 with a comparison control signal that enables timing comparison, and the comparison timing signals (STROB1, ST
ROB2, STROB3, STROB4), a timing comparator 22 for detecting whether the output of the gate is H level or L level at each comparison timing, a timing generator 23 for generating a comparison timing signal, and a timing comparator 22. An expected value level comparator 14 that compares the output signal with the expected value, and a comparison result holding circuit 15 that holds the comparison result with the expected value level at the rear end of the comparison timing signal.

In FIG. 2, the output signal changes from the H level to the L level for a certain input signal, and the change point is the time T.
FIG. 6 is a test timing diagram for DUT2 lying between 2; The output Dout of the DUT2 changes from the H level to the L level during the time T2. The output Dout is compared with the comparison voltage VO by the level comparator 11, and is delayed by the propagation delay time of the level comparator 11 to change from the H level to the L level.

STR which is the output of the timing generator 23
OB1 changes from the L level to the H level at the rear end of the time T1, and changes from the H level to the L level at the rear end of the basic period T. At the rise of STROB1, the clear terminal of the flip-flop F / F1 in the timing comparator 22 is at H level because the output of the level comparator 11 and the comparison control signal are at H level, and the output of F / F1 is at H level. Hold the level. In this embodiment, the expected value is the L level and the output of the expected value level comparator 14 is the H level, so that the comparison result holding circuit 15 holds the H level at the rear end of STROB1. Since the H level of the comparison result 1 indicates disagreement with the expected value, it becomes FAIL in this case.

Then, STROB2, which is the output of the timing generator 23, changes from the L level to the H level at the rear end of the time T2.
The level changes to H level from the H level to the L level at the rear end of the basic cycle T. At the rise of STROB2, the clear terminal of the flip-flop F / F2 in the timing comparator 22 is at the L level because the output of the level comparator 11 is at the L level and the comparison control signal is at the H level.
The output of F2 changes from H level to L level. In this embodiment, the expected value is the L level and the output of the expected value level comparator 14 is the L level, so that the comparison result holding circuit 15 holds the L level at the rear end of STROB2.
Since the L level of the comparison result 2 indicates a match with the expected value, it is PASS in this case.

Then, STROB3, which is the output of the timing generator 23, changes from the L level to the H level at the rear end of the time T3.
The level changes to H level from the H level to the L level at the rear end of the basic cycle T. At the rising of STROB3, the clear terminal of the flip-flop F / F3 in the timing comparator 22 is the same as at the rising of STROB2.
It is at the L level, and the output of the F / F3 changes from the H level to the L level. In the present embodiment, the expected value is L level, and the output of the expected value level comparator 14 is L level. Therefore, the comparison result holding circuit 1 is provided at the rear end of STROB3.
The L level is held at 5. Since the L level of the comparison result 3 indicates a match with the expected value, it is PASS in this case.

Then, STROB4, which is the output of the timing generator 23, changes from the L level to the H level at the rear end of the time T4.
The level changes to H level from the H level to the L level at the rear end of the basic cycle T. At the rising edge of STROB4, the clear terminal of the flip-flop F / F4 in the timing comparator 22 is the same as that at the rising edge of STROB2.
It is at the L level, and the output of the F / F4 changes from the H level to the L level. In this embodiment, the expected value is L level and the output of the expected value level comparator 14 is L level, so that the comparison result holding circuit 1 is provided at the rear end of STROB4.
The L level is held at 5. Since the L level of the comparison result 4 indicates a match with the expected value, it is PASS in this case.

DUT1 has a change point from the H level to the L level of the output signal during time T1, DUT3 is during time T3, and DUT4 is during time T4. Therefore, comparison result 1 and comparison result The following test results can be obtained in each of 2, Comparative result 3 and Comparative result 4. Therefore, classification based on the difference in signal output time of the DUT 10 is possible in one basic cycle T. DUT1 DUT2 DUT3 DUT4 Comparison result 1 PASS FAIL FAIL FAIL Comparison result 2 PASS PASS FAIL FAIL Comparison result 3 PASS PASS PASS FAIL Comparison result 4 PASS PASS PASS PASS

In the present embodiment, classification is performed according to the difference in signal output time for four types of input signals.
By increasing / decreasing the expandable unit 30, it is possible to classify an arbitrary number N, and the classification time can be shortened to 1 / N as compared with the conventional circuit.

[0022]

Since the present invention is configured as described above, when the number of expandable parts is N, the classification according to the difference in signal output time with respect to the input signal is 1 compared with the conventional circuit. / N, which is effective in shortening the test time.

[Brief description of drawings]

FIG. 1 is a block diagram of a logical comparison circuit according to the present invention.

FIG. 2 is a timing chart according to the embodiment of the present invention.

FIG. 3 is a timing chart showing an example of an input signal and a device under test output signal.

FIG. 4 is a block diagram of a conventional logical comparison circuit.

FIG. 5 is a timing diagram in a conventional logic comparison circuit.

[Explanation of symbols]

 10 device under test (DUT) 11 level comparator 12, 22 timing comparator 13, 23 timing generator 14 expected value level comparator 15 comparison result holding circuit 30 expandable part

Claims (1)

[Claims] 1. A timing generator (23) for generating a plurality of comparison timing signals is provided for classification according to a difference in signal output time with respect to an input signal of a device under test (10), and each comparison timing signal is input to a terminal. Then, the output of the device under test (10) is input to another terminal through the level comparator (11) and the gate controlled by the comparison control signal, and is input to another terminal. 22), a plurality of expected value level comparators (14) for comparing the outputs of the plurality of flip-flops with expected values, and a plurality of comparisons for holding the outputs of the plurality of expected value level comparators (14). A logical comparator comprising a result holding circuit (15) and comprising the above.