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JPH086058A - Liquid crystal display - Google Patents

Liquid crystal display

Info

Publication number
JPH086058A
JPH086058A JP15821994A JP15821994A JPH086058A JP H086058 A JPH086058 A JP H086058A JP 15821994 A JP15821994 A JP 15821994A JP 15821994 A JP15821994 A JP 15821994A JP H086058 A JPH086058 A JP H086058A
Authority
JP
Japan
Prior art keywords
semiconductor chip
input side
chip mounting
wirings
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15821994A
Other languages
Japanese (ja)
Other versions
JP3264103B2 (en
Inventor
Masamitsu Kishigami
政光 岸上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15821994A priority Critical patent/JP3264103B2/en
Publication of JPH086058A publication Critical patent/JPH086058A/en
Application granted granted Critical
Publication of JP3264103B2 publication Critical patent/JP3264103B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To make it possible to reduce the size of the above device and to simplify the structure of a flexible wiring board. CONSTITUTION:Four pieces of wirings for connecting power source input sides 37 connect power source input side connecting electrodes 34c, 34b corresponding to each other of a semiconductor chip mounted at a semiconductor chip mounting area 8 on the left side and a semiconductor chip mounted at a semiconductor chip mounting area 9 of a right side to each other and connect two sets of the power source input side connecting electrodes 34b, 34c corresponding to each other of the semiconductor chip mounted at the semiconductor chip mounting area 9 of the right side to each other. The wirings described above are formed continuously across the respective semiconductor chip mounting areas 8, 9. The respective right ends are integrally arranged at the right end of the projecting part of the transparent substrate 7 on the lower side. Then, the size is made smaller than in the case of conducting and connecting the flexible wiring board having the wirings for connection on both surfaces to the plural semiconductor chips; in addition, the structure of the flexible wiring board is simplified.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は液晶表示装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device.

【0002】[0002]

【従来の技術】図4(A)は従来の液晶表示装置の一例
を示したものであり、図4(B)はその配線構造を示し
たものである。この液晶表示装置では、液晶表示パネル
1、3つの半導体チップ2〜4、フレキシブル配線基板
5、図示しない制御回路用回路基板等を備えている。こ
のうち液晶表示パネル1は、相対向する面にそれぞれ図
示しない表示電極が設けられた2枚の透明基板6、7の
間に図示しない液晶が封入されたものからなっている。
下側の透明基板7の下辺および右辺は上側の透明基板6
のそれぞれ対応する下辺および右辺から突出されてい
る。下側の透明基板7の下辺側の突出部の上面には、鎖
線で示す2つの半導体チップ搭載エリア8、9が設けら
れ、半導体チップ搭載エリア8、9の各上端部にそれぞ
れ複数本の出力側接続用配線10、11が設けられ、半
導体チップ搭載エリア8、9の各下端部にそれぞれ複数
本の入力側接続用配線12、13が設けられている。出
力側接続用配線10、11の各一端部は下側の表示電極
の駆動素子に接続され、各他端部は半導体チップ搭載エ
リア8、9内に突出されている。入力側接続用配線1
2、13の各一端部は半導体チップ搭載エリア8、9内
に突出され、各他端部は下側の透明基板7の下端部に配
置されている。また、下側の透明基板7の右辺側の突出
部の上面には、鎖線で示す1つの半導体チップ搭載エリ
ア14が設けられ、半導体チップ搭載エリア14の左端
部に複数本の出力側接続用配線15が設けられ、半導体
チップ搭載エリア14の右端部に複数本の入力側接続用
配線16が設けられ、所定の箇所に1本のコモン電極側
接続用配線17が設けられている。出力側接続用配線1
5の各一端部は下側の表示電極の駆動素子に接続され、
各他端部は半導体チップ搭載エリア14内に突出されて
いる。入力側接続用配線16の各一端部は半導体チップ
搭載エリア14内に突出され、各他端部は下側の透明基
板7の右端部に配置されている。コモン電極側接続用配
線17の一端部はクロス材18を介して上側の表示電極
と接続され、他端部は下側の透明基板7の右端部に配置
されている。
2. Description of the Related Art FIG. 4 (A) shows an example of a conventional liquid crystal display device, and FIG. 4 (B) shows its wiring structure. This liquid crystal display device includes a liquid crystal display panel 1, three semiconductor chips 2 to 4, a flexible wiring board 5, a control circuit circuit board (not shown), and the like. Of these, the liquid crystal display panel 1 is composed of two transparent substrates 6, 7 each having a display electrode (not shown) provided on opposite surfaces thereof, and a liquid crystal (not shown) sealed between the two transparent substrates 6, 7.
The lower and right sides of the lower transparent substrate 7 are the upper transparent substrate 6
Are projected from the corresponding lower and right sides, respectively. Two semiconductor chip mounting areas 8 and 9 shown by chain lines are provided on the upper surface of the lower side protruding portion of the lower transparent substrate 7, and a plurality of output lines are provided at the respective upper ends of the semiconductor chip mounting areas 8 and 9. Side connection wirings 10 and 11 are provided, and a plurality of input side connection wirings 12 and 13 are provided at the lower ends of the semiconductor chip mounting areas 8 and 9, respectively. One end of each of the output side connecting wirings 10 and 11 is connected to the drive element of the lower display electrode, and the other end thereof is projected into the semiconductor chip mounting areas 8 and 9. Input side connection wiring 1
One end of each of 2 and 13 is projected into the semiconductor chip mounting areas 8 and 9, and the other end of each is located at the lower end of the lower transparent substrate 7. Further, one semiconductor chip mounting area 14 shown by a chain line is provided on the upper surface of the right side protruding portion of the lower transparent substrate 7, and a plurality of output side connecting wirings are provided at the left end portion of the semiconductor chip mounting area 14. 15 is provided, a plurality of input side connection wirings 16 are provided at the right end of the semiconductor chip mounting area 14, and one common electrode side connection wiring 17 is provided at a predetermined position. Output side connection wiring 1
Each one end of 5 is connected to the driving element of the lower display electrode,
Each other end is projected into the semiconductor chip mounting area 14. Each one end of the input side connection wiring 16 is projected into the semiconductor chip mounting area 14, and each other end is arranged at the right end of the lower transparent substrate 7. One end of the common electrode side connection wiring 17 is connected to the upper display electrode via the cross member 18, and the other end is arranged at the right end of the lower transparent substrate 7.

【0003】半導体チップ2〜4の下面には、図5に示
すように、上辺のすぐ内側に複数の出力側接続電極(バ
ンプ電極)19が設けられ、下辺のすぐ内側に複数の入
力側接続電極(バンプ電極)20が設けられている。そ
して、このうち所定の2つの半導体チップ2、3は下側
の透明基板7の下辺側の突出部の上面の各半導体チップ
搭載エリア8、9にそれぞれ搭載されている。この場
合、各入力側接続電極20および各出力側接続電極19
が異方導電性接着剤等を介して各半導体チップ搭載エリ
ア8、9内の各入力側接続用配線12、13および各出
力側接続用配線10、11とそれぞれ導電接続されてい
る。また、同様にして、残りの1つの半導体チップ4は
下側の透明基板7の右辺側の突出部の上面の半導体チッ
プ搭載エリア14に搭載されている。
On the lower surfaces of the semiconductor chips 2 to 4, a plurality of output side connecting electrodes (bump electrodes) 19 are provided just inside the upper side and a plurality of input side connecting electrodes are provided just inside the lower side, as shown in FIG. Electrodes (bump electrodes) 20 are provided. Of these, the predetermined two semiconductor chips 2 and 3 are mounted in the respective semiconductor chip mounting areas 8 and 9 on the upper surface of the lower side protruding portion of the lower transparent substrate 7. In this case, each input side connection electrode 20 and each output side connection electrode 19
Are conductively connected to the respective input side connecting wirings 12 and 13 and the respective output side connecting wirings 10 and 11 in the respective semiconductor chip mounting areas 8 and 9 through an anisotropic conductive adhesive or the like. Similarly, the remaining one semiconductor chip 4 is mounted on the semiconductor chip mounting area 14 on the upper surface of the protrusion on the right side of the lower transparent substrate 7.

【0004】フレキシブル配線基板5はほぼL字状であ
って、その一端側5aの下面には下側の透明基板7の下
辺側の突出部の上面に設けられた各入力側接続用配線1
2、13に対応する2組の接続用配線21、22が設け
られ、その他端側5bの下面には下側の透明基板7の右
辺側の突出部の上面に設けられた入力側接続用配線16
およびコモン電極側接続用配線17に対応する接続用配
線23、24が設けられた構造となっている。この場
合、フレキシブル配線基板5の一端側5aは、1群のス
ルーホール導通部25を介して接続用配線21が両面配
線され、別の1群のスルーホール導通部26を介して2
組の接続用配線21、22が共通配線として導電接続さ
れている。そして、フレキシブル配線基板5の一端側5
aの各接続用配線21、22および他端側5bの各接続
用配線23、24が異方導電性接着剤等の接続部材を介
して対応する各接続用配線12、13および各接続用配
線16、17と導電接続され、フレキシブル配線基板5
の所定の箇所が制御回路用回路基板の所定の箇所と導電
接続されている。
The flexible wiring board 5 is substantially L-shaped, and each input side connection wiring 1 provided on the lower surface of the lower transparent substrate 7 on the lower surface of one end 5a thereof is provided on the upper surface of the projecting portion.
Two sets of connection wirings 21 and 22 corresponding to Nos. 2 and 13 are provided, and an input side connection wiring provided on the upper surface of the right side protrusion of the lower transparent substrate 7 on the lower surface of the other end side 5b. 16
And the connection wirings 23 and 24 corresponding to the common electrode side connection wiring 17 are provided. In this case, on one end side 5a of the flexible wiring board 5, the connecting wiring 21 is double-sided via a group of through-hole conducting portions 25, and is connected via another group of through-hole conducting portions 26.
The pair of connecting wires 21 and 22 are conductively connected as a common wire. Then, one end side 5 of the flexible wiring board 5
The connection wirings 21 and 22 of a and the connection wirings 23 and 24 of the other end side 5b corresponding to the connection wirings 12 and 13 and the connection wirings through a connection member such as an anisotropic conductive adhesive. Flexible wiring board 5 that is conductively connected to 16 and 17
Is conductively connected to a predetermined portion of the control circuit circuit board.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
このような液晶表示装置では、接続用配線21〜24を
備えたほぼL字状のフレキシブル配線基板5を液晶表示
パネル1の各半導体チップ2〜4にそれぞれ導電接続し
ているので、フレキシブル配線基板5の占有面積が大き
くなって大型化するという問題があった。また、2つの
半導体チップ2、3に対する接続用配線21、22を共
通配線として導電接続する関係から、フレキシブル配線
基板5がスルーホール導通部25、26を介した両面配
線構造となるので、フレキシブル配線基板5の構造が複
雑でコスト高になるという問題があった。このようなこ
とは、半導体チップ2、3の数が多くなればなるほど、
顕著である。この発明の目的は、小型化することができ
るとともに、フレキシブル配線基板の構造を単純化する
ことができる液晶表示装置を提供することにある。
However, in such a conventional liquid crystal display device, the substantially L-shaped flexible wiring substrate 5 having the connection wirings 21 to 24 is used to form the semiconductor chips 2 to 2 of the liquid crystal display panel 1. Since they are electrically conductively connected to each of the wirings 4, there is a problem that the area occupied by the flexible wiring board 5 becomes large and the size becomes large. Further, since the connection wirings 21 and 22 for the two semiconductor chips 2 and 3 are conductively connected as a common wiring, the flexible wiring board 5 has a double-sided wiring structure via the through-hole conducting portions 25 and 26, and therefore flexible wiring. There is a problem that the structure of the substrate 5 is complicated and the cost is high. This is because as the number of semiconductor chips 2 and 3 increases,
It is remarkable. An object of the present invention is to provide a liquid crystal display device which can be downsized and which can simplify the structure of a flexible wiring board.

【0006】[0006]

【課題を解決するための手段】請求項1記載の発明は、
相対向する2枚の基板のうち少なくとも一方の基板が他
方の基板の少なくとも一辺から突出されて突出部が形成
され、この突出部の一面に前記他方の基板の一辺に沿っ
て複数の半導体チップ搭載エリアが設けられ、前記各半
導体チップ搭載エリアに複数の半導体チップがそれぞれ
搭載されてなる液晶表示装置において、前記突出部の一
面に、前記他方の基板の一辺に沿って搭載される前記複
数の半導体チップの相対応する入力側接続電極同士を導
電接続する互いに交差しない複数本の接続用配線を前記
各半導体チップ搭載エリアにわたって連続して設け、前
記接続用配線の各一端部を前記突出部の一面の一箇所に
まとめて配置したものである。請求項2記載の発明は、
前記複数本の接続用配線が前記複数の半導体チップ搭載
エリア内を通過するものである。請求項3記載の発明
は、前記半導体チップは互いに対応する2組の入力側接
続電極を有し、前記2組の入力側接続電極がそれぞれ対
応する接続用配線に導電接続されたものである。請求項
4記載の発明は、前記半導体チップの互いに対応する2
組の入力側接続電極がチップ内部で結線されているもの
である。
According to the first aspect of the present invention,
At least one substrate of the two substrates facing each other is projected from at least one side of the other substrate to form a protrusion, and a plurality of semiconductor chips are mounted on one surface of the protrusion along one side of the other substrate. In a liquid crystal display device in which an area is provided and a plurality of semiconductor chips are mounted in each of the semiconductor chip mounting areas, the plurality of semiconductors mounted on one surface of the protrusion along one side of the other substrate A plurality of non-intersecting connection wirings for conductively connecting corresponding input side connection electrodes of the chip are continuously provided over the respective semiconductor chip mounting areas, and one end of each of the connection wirings is provided on one surface of the projecting portion. It is arranged in one place. The invention according to claim 2 is
The plurality of connecting wirings pass through the plurality of semiconductor chip mounting areas. According to a third aspect of the present invention, the semiconductor chip has two sets of input side connection electrodes corresponding to each other, and the two sets of input side connection electrodes are conductively connected to corresponding connection wirings. According to a fourth aspect of the present invention, two semiconductor chips corresponding to each other are provided.
The input side connection electrodes of the set are connected inside the chip.

【0007】[0007]

【作用】請求項1記載の発明によれば、各半導体チップ
搭載エリアに搭載される複数の半導体チップの相対応す
る入力側接続電極同士を導電接続する互いに交差しない
複数本の接続用配線を各半導体チップ搭載エリアにわた
って連続して設け、接続用配線の各一端部を前記突出部
の一面の一箇所にまとめて配置したので、両面に接続用
配線を備えたフレキシブル配線基板を複数の半導体チッ
プに導電接続する場合と比較して、小型化することがで
きるとともに、フレキシブル配線基板の構造を単純化す
ることができる。請求項2記載の発明によれば、複数本
の接続用配線が複数の半導体チップ搭載エリア内を通過
するので、その分突出部の幅を狭くすることができ、こ
の結果小型化することができる。請求項3および4記載
の発明によれば、半導体チップは互いに対応する2組の
入力側接続電極を有し、2組の入力側接続電極がそれぞ
れ対応する接続用配線に導電接続され、かつ半導体チッ
プの互いに対応する2組の入力側接続電極がチップ内部
で結線されているので、半導体チップの互いに対応する
2組の入力側接続電極間において半導体チップの結線と
接続用配線とが並列し、この結果接続用配線の配線抵抗
を低くすることができる。
According to the first aspect of the invention, a plurality of connecting wirings which do not intersect each other for conductively connecting the corresponding input side connecting electrodes of the plurality of semiconductor chips mounted in each semiconductor chip mounting area are provided. The flexible wiring board having the connection wirings on both sides is provided in a plurality of semiconductor chips because the connection wirings are continuously provided over the semiconductor chip mounting area and one end of each of the connection wirings is collectively arranged on one surface of the protruding portion. The size of the flexible wiring board can be reduced and the structure of the flexible wiring board can be simplified as compared with the case of conductive connection. According to the second aspect of the present invention, since the plurality of connecting wirings pass through the plurality of semiconductor chip mounting areas, the width of the protruding portion can be narrowed correspondingly, and as a result, the size can be reduced. . According to the inventions of claims 3 and 4, the semiconductor chip has two sets of input-side connection electrodes corresponding to each other, and the two sets of input-side connection electrodes are conductively connected to the corresponding connection wirings, respectively, and the semiconductor Since the two sets of input side connection electrodes corresponding to each other of the chip are connected inside the chip, the connection of the semiconductor chip and the connection wiring are arranged in parallel between the two sets of input side connection electrodes corresponding to each other of the semiconductor chip, As a result, the wiring resistance of the connection wiring can be reduced.

【0008】[0008]

【実施例】図1はこの発明による液晶表示装置の一実施
例を示したものであり、図2(A)および(B)はその
配線構造を示したものである。これらの図において、図
4(A)および(B)と同一名称部分には同一の符号を
付し、その説明を適宜省略する。この液晶表示装置の下
側の透明基板7の下辺側の突出部の上面には、従来と同
様に半導体チップ搭載エリア8、9が設けられている。
この半導体チップ搭載エリア8、9には、従来の半導体
チップ2、3の代わりに半導体チップ31、32が搭載
される。この半導体チップ31、32の下面には、図3
(A)に示すように、上辺のすぐ内側に複数の出力側接
続電極33が設けられ、右辺のすぐ内側に4つの信号入
力側接続電極34aが設けられ、下辺のすぐ内側の2箇
所に4つの電源入力側接続電極34b、34cがそれぞ
れ設けられている。この場合、左側の電源入力側接続電
極34bと互いに対応する右側の電源入力側接続電極3
4cとがチップ内部で結線されている。また、下側の透
明基板7の右辺側の突出部の上面にも、従来と同様に半
導体チップ搭載エリア14が設けられている。この半導
体チップ搭載エリア14には、従来の半導体チップ4の
代わりに半導体チップ35が搭載される。この半導体チ
ップ35の下面には、図3(B)に示すように、上辺の
すぐ内側に複数の出力側接続電極33が設けられ、左辺
のすぐ内側に4つの信号入力側接続電極34aが設けら
れ、下辺のすぐ内側の2箇所に4つの電源入力側接続電
極34b、34cがそれぞれ設けられている。この場合
も、左側の電源入力側接続電極34bと互いに対応する
右側の電源入力側接続電極34cとがチップ内部で結線
されている。
FIG. 1 shows an embodiment of the liquid crystal display device according to the present invention, and FIGS. 2A and 2B show the wiring structure thereof. In these figures, parts having the same names as those in FIGS. 4A and 4B are designated by the same reference numerals, and the description thereof will be appropriately omitted. The semiconductor chip mounting areas 8 and 9 are provided on the upper surface of the protruding portion on the lower side of the transparent substrate 7 on the lower side of the liquid crystal display device as in the conventional case.
In the semiconductor chip mounting areas 8 and 9, semiconductor chips 31 and 32 are mounted instead of the conventional semiconductor chips 2 and 3. The bottom surface of the semiconductor chips 31 and 32 is shown in FIG.
As shown in (A), a plurality of output side connecting electrodes 33 are provided immediately inside the upper side, four signal input side connecting electrodes 34a are provided immediately inside the right side, and four output side connecting electrodes 34a are provided immediately inside the lower side. Two power supply input side connection electrodes 34b and 34c are provided, respectively. In this case, the power source input side connecting electrode 34b on the left side and the power source input side connecting electrode 3 on the right side corresponding to each other
4c is connected inside the chip. Further, the semiconductor chip mounting area 14 is provided on the upper surface of the right side protruding portion of the lower transparent substrate 7 as in the conventional case. In the semiconductor chip mounting area 14, a semiconductor chip 35 is mounted instead of the conventional semiconductor chip 4. On the lower surface of the semiconductor chip 35, as shown in FIG. 3B, a plurality of output side connection electrodes 33 are provided immediately inside the upper side, and four signal input side connection electrodes 34a are provided immediately inside the left side. Therefore, four power supply input side connection electrodes 34b and 34c are provided at two positions just inside the lower side. In this case as well, the power supply input side connection electrode 34b on the left side and the power supply input side connection electrode 34c on the right side corresponding to each other are connected inside the chip.

【0009】下側の透明基板7の下辺側の突出部の上面
には、従来の入力側接続用配線12、13の代わりに互
いに交差しない4本の信号入力側接続用配線36および
4本の電源入力側接続用配線37が設けられている。4
本の信号入力側接続用配線36は、左側の半導体チップ
搭載エリア8に搭載される半導体チップ31と右側の半
導体チップ搭載エリア9に搭載される半導体チップ32
との互いに対応する信号入力側接続電極34a、34a
同士をそれぞれ接続し、両半導体チップ搭載エリア8、
9にわたって連続して設けられ、各右端部が下側の透明
基板7の突出部の右端部にまとめて配置されている。4
本の電源入力側接続用配線37は、左側の半導体チップ
搭載エリア8に搭載される半導体チップ31と右側の半
導体チップ搭載エリア9に搭載される半導体チップ32
との互いに対応する電源入力側接続電極34c、34b
同士をそれぞれ接続するとともに、右側の半導体チップ
搭載エリア9に搭載される半導体チップ32の互いに対
応する両電源入力側接続電極34b、34c同士をそれ
ぞれ接続し、各半導体チップ搭載エリア8、9にわたっ
て連続して設けられ、各右端部が下側の透明基板7の突
出部の右端部にまとめて配置されている。また、下側の
透明基板7の右辺側の突出部の上面には、従来の入力側
接続用配線16の代わりに互いに交差しない4本の信号
入力側接続用配線38および4本の電源入力側接続用配
線39が設けられている。4本の信号入力側接続用配線
38は、各上端部が半導体チップ搭載エリア14に搭載
される半導体チップ35の信号入力側接続電極34aに
接続され、各下端部が下側の透明基板7の突出部の右端
部にまとめて配置されている。4本の電源入力側接続用
配線39は、各上端部が半導体チップ搭載エリア14に
搭載される半導体チップ35の電源入力側接続電極34
bに接続され、各下端部が下側の透明基板7の突出部の
右端部にまとめて配置されている。なお、図2(A)お
よび(B)では、半導体チップ31、32、35の各接
続電極33、34a〜34cが黒丸で示されている。
On the upper surface of the projecting portion on the lower side of the lower transparent substrate 7, instead of the conventional input side connecting wirings 12 and 13, four signal input side connecting wirings 36 and 4 which do not intersect each other are provided. A power supply input side connection wiring 37 is provided. Four
The signal input side connection wiring 36 of the book includes a semiconductor chip 31 mounted on the left semiconductor chip mounting area 8 and a semiconductor chip 32 mounted on the right semiconductor chip mounting area 9.
Signal input side connection electrodes 34a, 34a corresponding to
Connected to each other, both semiconductor chip mounting area 8,
9 are continuously provided, and the respective right ends thereof are collectively arranged at the right ends of the protruding portions of the lower transparent substrate 7. Four
The power supply input side connection wiring 37 of the book includes a semiconductor chip 31 mounted in the semiconductor chip mounting area 8 on the left side and a semiconductor chip 32 mounted in the semiconductor chip mounting area 9 on the right side.
And power supply input side connection electrodes 34c, 34b corresponding to
The semiconductor chips 32 mounted on the right side semiconductor chip mounting area 9 are connected to each other, and the power supply input side connecting electrodes 34b and 34c corresponding to each other are connected to each other, and the semiconductor chip mounting areas 8 and 9 are continuously connected. The right end portions are collectively arranged at the right end portions of the protruding portions of the lower transparent substrate 7. Further, on the upper surface of the right side protruding portion of the lower transparent substrate 7, instead of the conventional input side connecting wiring 16, four signal input side connecting wirings 38 and four power input side which do not intersect each other are provided. Connection wiring 39 is provided. Each of the four signal input side connecting wirings 38 has its upper end connected to the signal input side connecting electrode 34a of the semiconductor chip 35 mounted in the semiconductor chip mounting area 14, and each lower end of the lower transparent substrate 7. They are collectively arranged at the right end of the protrusion. Each of the four power supply input side connection wirings 39 has its upper end portion connected to the power supply input side connection electrode 34 of the semiconductor chip 35 mounted in the semiconductor chip mounting area 14.
The lower ends of the transparent substrates 7 are connected together to the right end of the protruding portion of the lower transparent substrate 7. 2A and 2B, the connection electrodes 33, 34a to 34c of the semiconductor chips 31, 32, 35 are shown by black circles.

【0010】そして、所定の2つの半導体チップ31、
32は下側の透明基板7の下辺側の突出部に設けられた
2つの半導体チップ搭載エリア8、9にそれぞれ搭載さ
れる。この場合、半導体チップ31、32の各信号入力
側接続電極34aは、異方導電性接着剤等の接続部材を
介して半導体チップ搭載エリア8、9の相対応する信号
入力側接続用配線36にそれぞれ導電接続され、各電源
入力側接続電極34b、34cは、異方導電性接着剤等
の接続部材を介して半導体チップ搭載エリア8、9の相
対応する電源入力側接続用配線37にそれぞれ導電接続
され、各出力側接続電極33は、従来と同様に、異方導
電性接着剤等の接続部材を介して半導体チップ搭載エリ
ア8、9の相対応する出力側接続用配線10、11にそ
れぞれ導電接続される。また、残りの1つの半導体チッ
プ4も同様にして所定の1つの半導体チップ搭載エリア
14に搭載される。
Then, two predetermined semiconductor chips 31,
32 is mounted on each of the two semiconductor chip mounting areas 8 and 9 provided on the projecting portion on the lower side of the lower transparent substrate 7. In this case, the signal input side connecting electrodes 34a of the semiconductor chips 31 and 32 are connected to the corresponding signal input side connecting wirings 36 of the semiconductor chip mounting areas 8 and 9 via a connecting member such as an anisotropic conductive adhesive. Each of the power source input side connecting electrodes 34b and 34c is electrically conductively connected to the corresponding power source input side connecting wiring 37 of the semiconductor chip mounting areas 8 and 9 through a connecting member such as an anisotropic conductive adhesive. Each of the output side connection electrodes 33 is connected to the corresponding output side connection wirings 10 and 11 of the semiconductor chip mounting areas 8 and 9 through a connection member such as an anisotropic conductive adhesive as in the conventional case. Conductive connection. Further, the remaining one semiconductor chip 4 is similarly mounted in the predetermined one semiconductor chip mounting area 14.

【0011】このように、この液晶表示装置では、各半
導体チップ搭載エリア8、9に搭載される各半導体チッ
プ31、32の相対応する入力側接続電極34a〜34
c同士を導電接続する互いに交差しない複数本の接続用
配線36、37を各半導体チップ搭載エリア8、9にわ
たって連続して設け、接続用配線36、37の各一端部
を下側の透明基板7の突出部の一面の右端部にまとめて
配置したので、図4に示すような従来の両面に接続用配
線21を備えたフレキシブル配線基板5を複数の半導体
チップ2、3に導電接続する場合と比較して、小型化す
ることができるとともに、フレキシブル配線基板5の構
造を単純化することができる。また、複数の信号入力側
接続用配線36が右側の半導体チップ搭載エリア9内を
通過するので、その分下側の透明基板7の下辺側の突出
部の幅を狭くすることができ、この結果小型化すること
ができる。また、半導体チップ31、32の互いに対応
する2組の電源入力側接続電極34b、34cがそれぞ
れ対応する電源入力側接続用配線37に導電接続される
ので、電源入力側接続電極34b、34cが2組あって
も配線数を増やすことなく導電接続することができる。
さらに、半導体チップ31、32の互いに対応する2組
の電源入力側接続電極34b、34cがチップ内部で結
線されているので、半導体チップ31、32の互いに対
応する2組の電源入力側接続電極34b、34c間にお
いて、半導体チップ32の結線と電源入力側接続用配線
37とが並列することになり、この結果フレキシブル配
線基板5から遠い左側の半導体チップ搭載エリア8に搭
載される半導体チップ31に対して配線抵抗を低くする
ことができ、また左側の半導体チップ搭載エリア8に搭
載される半導体チップ31の両電源入力側接続電極34
b、34c間を接続する電源入力側接続用配線37を省
略することができる。
As described above, in this liquid crystal display device, the input side connection electrodes 34a to 34 corresponding to the semiconductor chips 31 and 32 mounted in the semiconductor chip mounting areas 8 and 9 are provided.
A plurality of non-intersecting connecting wirings 36 and 37 for conductively connecting c to each other are continuously provided over the respective semiconductor chip mounting areas 8 and 9, and one end of each of the connecting wirings 36 and 37 is provided on the lower transparent substrate 7 Since they are collectively arranged on the right end of one surface of the projecting portion, the flexible wiring board 5 having the connection wirings 21 on both surfaces of the related art as shown in FIG. 4 is conductively connected to the plurality of semiconductor chips 2 and 3. In comparison, the size can be reduced and the structure of the flexible wiring board 5 can be simplified. Further, since the plurality of signal input side connection wirings 36 pass through the inside of the semiconductor chip mounting area 9 on the right side, the width of the lower side protruding portion of the transparent substrate 7 on the lower side can be narrowed by that amount. It can be miniaturized. Further, since the two sets of power supply input side connection electrodes 34b and 34c corresponding to each other of the semiconductor chips 31 and 32 are conductively connected to the corresponding power supply input side connection wirings 37, the power supply input side connection electrodes 34b and 34c are not connected to each other. Even if assembled, conductive connection can be made without increasing the number of wires.
Further, since two sets of power supply input side connection electrodes 34b, 34c of the semiconductor chips 31, 32 corresponding to each other are connected inside the chip, two sets of power supply input side connection electrodes 34b of the semiconductor chips 31, 32 corresponding to each other are connected. , 34c, the wiring of the semiconductor chip 32 and the power input side connecting wiring 37 are arranged in parallel, and as a result, the semiconductor chip 31 mounted on the semiconductor chip mounting area 8 on the left side far from the flexible wiring board 5 is Wiring resistance can be reduced, and both power supply input side connection electrodes 34 of the semiconductor chip 31 mounted in the semiconductor chip mounting area 8 on the left side can be reduced.
It is possible to omit the power supply input side connection wiring 37 that connects between b and 34c.

【0012】なお、上記実施例では、下側の透明基板7
の下辺側の突出部の上面に2つの半導体チップ31、3
2を搭載し、これら2つの半導体チップ31、32のそ
れぞれ対応する入力側接続電極34a〜34c同士を入
力側接続用配線36、37を介して導電接続する場合に
ついて説明したが、これに限定されるものではなく、例
えば、下側の透明基板7の下辺側の突出部の上面に3つ
の半導体チップ31、32を搭載し、これら3つの半導
体チップ31、32のそれぞれ対応する入力側接続電極
34a〜34c同士を入力側接続用配線36、37を介
して導電接続するようにしてもよい。また、上記実施例
では、半導体チップ31、32、35の下面に1組の信
号入力側接続電極34aを設けた場合について説明した
が、これに限定されず、電源入力側接続電極34b、3
4cと同様に、半導体チップ31、32、35に互いに
対応する2組の信号入力側接続電極34aを設け、2組
の信号入力側接続電極34aをそれぞれ対応する信号入
力側接続用配線36に導電接続し、かつ半導体チップ3
1、32、35の対応する2組の信号入力側接続電極3
4aを互いに内部で結線するようにしてもよい。
In the above embodiment, the lower transparent substrate 7
Two semiconductor chips 31 and 3 are provided on the upper surface of the protrusion on the lower side.
2 has been mounted and the corresponding input side connection electrodes 34a to 34c of these two semiconductor chips 31 and 32 are conductively connected via the input side connection wirings 36 and 37, but the present invention is not limited to this. For example, three semiconductor chips 31 and 32 are mounted on the upper surface of the lower side protruding portion of the lower transparent substrate 7, and the input side connection electrodes 34a corresponding to the three semiconductor chips 31 and 32, respectively. 34c may be conductively connected to each other through the input side connecting wirings 36 and 37. Further, in the above embodiment, the case where one set of signal input side connecting electrodes 34a is provided on the lower surface of the semiconductor chips 31, 32, 35 has been described, but the present invention is not limited to this, and the power input side connecting electrodes 34b, 3 are provided.
Similar to 4c, two sets of signal input side connection electrodes 34a corresponding to each other are provided on the semiconductor chips 31, 32, 35, and the two sets of signal input side connection electrodes 34a are electrically connected to the corresponding signal input side connection wirings 36, respectively. Connected and semiconductor chip 3
Two sets of signal input side connecting electrodes 3 corresponding to 1, 32 and 35
4a may be internally connected to each other.

【0013】[0013]

【発明の効果】以上説明したように、請求項1記載の発
明によれば、各半導体チップ搭載エリアに搭載される複
数の半導体チップの相対応する入力側接続電極同士を導
電接続する互いに交差しない複数本の接続用配線を各半
導体チップ搭載エリアにわたって連続して設け、接続用
配線の各一端部を前記突出部の一面の一箇所にまとめて
配置したので、両面に接続用配線を備えたフレキシブル
配線基板を複数の半導体チップに導電接続する場合と比
較して、小型化することができるとともに、フレキシブ
ル配線基板の構造を単純化することができる。請求項2
記載の発明によれば、複数本の接続用配線が複数の半導
体チップ搭載エリア内を通過するので、その分突出部の
幅を狭くすることができ、この結果小型化することがで
きる。請求項3および4記載の発明によれば、半導体チ
ップは互いに対応する2組の入力側接続電極を有し、2
組の入力側接続電極がそれぞれ対応する接続用配線に導
電接続され、かつ半導体チップの互いに対応する2組の
入力側接続電極がチップ内部で結線されているので、半
導体チップの互いに対応する2組の入力側接続電極間に
おいて半導体チップの結線と接続用配線とが並列し、こ
の結果接続用配線の配線抵抗を低くすることができる。
As described above, according to the first aspect of the present invention, the corresponding input side connection electrodes of the plurality of semiconductor chips mounted in each semiconductor chip mounting area are conductively connected and do not intersect each other. Since a plurality of connecting wirings are continuously provided over each semiconductor chip mounting area and one end portion of each connecting wiring is arranged in one place on one surface of the projecting portion, a flexible wiring having connecting wirings on both sides is provided. As compared with the case where the wiring board is conductively connected to the plurality of semiconductor chips, the size can be reduced and the structure of the flexible wiring board can be simplified. Claim 2
According to the invention described above, since the plurality of connecting wirings pass through the plurality of semiconductor chip mounting areas, the width of the protruding portion can be narrowed by that much, and as a result, the size can be reduced. According to the invention described in claims 3 and 4, the semiconductor chip has two sets of input-side connection electrodes corresponding to each other.
Since two sets of input side connecting electrodes are conductively connected to corresponding connecting wirings and two sets of corresponding input side connecting electrodes of the semiconductor chip are connected inside the chip, two sets of semiconductor chip corresponding to each other are connected. The connection of the semiconductor chip and the connection wiring are arranged in parallel between the input-side connection electrodes, and as a result, the wiring resistance of the connection wiring can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明による液晶表示装置の一実施例の平面
図。
FIG. 1 is a plan view of an embodiment of a liquid crystal display device according to the present invention.

【図2】(A)は同液晶表示装置の配線構造の平面図、
(B)はその要部の平面図。
FIG. 2A is a plan view of a wiring structure of the liquid crystal display device,
(B) is a plan view of the main part thereof.

【図3】(A)はこの液晶表示装置で使用される所定の
2つの半導体チップの平面図、(B)は同液晶表示装置
で使用される残りの1つの半導体チップの平面図。
FIG. 3A is a plan view of two predetermined semiconductor chips used in this liquid crystal display device, and FIG. 3B is a plan view of the remaining one semiconductor chip used in the same liquid crystal display device.

【図4】(A)は従来の液晶表示装置の一例の平面図、
(B)はその配線構造の平面図。
FIG. 4A is a plan view of an example of a conventional liquid crystal display device,
(B) is a plan view of the wiring structure.

【図5】同液晶表示装置で使用される半導体チップの平
面図。
FIG. 5 is a plan view of a semiconductor chip used in the liquid crystal display device.

【符号の説明】[Explanation of symbols]

1 液晶表示パネル 5 フレキシブル配線基板 6、7 透明基板 8、9、14 半導体チップ搭載エリア 31、32、35 半導体チップ 34a 信号入力側接続電極 34b、34c 電源入力側接続電極 36、38 信号入力側接続用配線 37、39 電源入力側接続用配線 1 liquid crystal display panel 5 flexible wiring substrate 6, 7 transparent substrate 8, 9, 14 semiconductor chip mounting area 31, 32, 35 semiconductor chip 34a signal input side connecting electrode 34b, 34c power input side connecting electrode 36, 38 signal input side connection Wiring 37, 39 Wiring for power supply input side connection

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 相対向する2枚の基板のうち少なくとも
一方の基板が他方の基板の少なくとも一辺から突出され
て突出部が形成され、この突出部の一面に前記他方の基
板の一辺に沿って複数の半導体チップ搭載エリアが設け
られ、前記各半導体チップ搭載エリアに複数の半導体チ
ップがそれぞれ搭載されてなる液晶表示装置において、 前記突出部の一面に、前記他方の基板の一辺に沿って搭
載される前記複数の半導体チップの相対応する入力側接
続電極同士を導電接続する互いに交差しない複数本の接
続用配線を前記各半導体チップ搭載エリアにわたって連
続して設け、前記接続用配線の各一端部を前記突出部の
一面の一箇所にまとめて配置したことを特徴とする液晶
表示装置。
1. A projection is formed by projecting at least one substrate of two substrates facing each other from at least one side of the other substrate, and one surface of the projection is provided along one side of the other substrate. A liquid crystal display device having a plurality of semiconductor chip mounting areas, wherein a plurality of semiconductor chips are mounted in each of the semiconductor chip mounting areas, wherein the semiconductor chip mounting area is mounted on one surface of the protrusion along one side of the other substrate. A plurality of non-intersecting connection wirings for conductively connecting corresponding input side connection electrodes of the plurality of semiconductor chips are continuously provided over the respective semiconductor chip mounting areas, and each one end of the connection wirings is provided. A liquid crystal display device, characterized in that the protrusions are collectively arranged on one surface.
【請求項2】 前記複数本の接続用配線が前記複数の半
導体チップ搭載エリア内を通過することを特徴とする請
求項1記載の液晶表示装置。
2. The liquid crystal display device according to claim 1, wherein the plurality of connection wirings pass through the plurality of semiconductor chip mounting areas.
【請求項3】 前記半導体チップは互いに対応する2組
の入力側接続電極を有し、前記2組の入力側接続電極が
それぞれ対応する接続用配線に導電接続されたことを特
徴とする請求項1または2記載の液晶表示装置。
3. The semiconductor chip has two sets of input side connection electrodes corresponding to each other, and the two sets of input side connection electrodes are conductively connected to the corresponding connection wirings. 3. The liquid crystal display device according to 1 or 2.
【請求項4】 前記半導体チップの互いに対応する2組
の入力側接続電極がチップ内部で結線されていることを
特徴とする請求項3記載の液晶表示装置。
4. The liquid crystal display device according to claim 3, wherein two sets of input side connection electrodes corresponding to each other of the semiconductor chip are connected inside the chip.
JP15821994A 1994-06-17 1994-06-17 Liquid crystal display Expired - Fee Related JP3264103B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15821994A JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15821994A JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPH086058A true JPH086058A (en) 1996-01-12
JP3264103B2 JP3264103B2 (en) 2002-03-11

Family

ID=15666890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15821994A Expired - Fee Related JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Country Status (1)

Country Link
JP (1) JP3264103B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002311451A (en) * 2001-04-19 2002-10-23 Seiko Epson Corp Electrode driving device and electronic equipment
US6507384B1 (en) 1999-03-26 2003-01-14 Seiko Epson Corporation Flexible printed wiring board, electro-optical device, and electronic equipment
US6590629B1 (en) 1999-02-05 2003-07-08 Sharp Kabushiki Kaisha Liquid crystal display having a plurality of mounting substrates with common connection lines connecting the mounting substrates
US7027043B2 (en) 2002-03-25 2006-04-11 Sharp Kabushiki Kaisha Wiring substrate connected structure, and display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590629B1 (en) 1999-02-05 2003-07-08 Sharp Kabushiki Kaisha Liquid crystal display having a plurality of mounting substrates with common connection lines connecting the mounting substrates
US6507384B1 (en) 1999-03-26 2003-01-14 Seiko Epson Corporation Flexible printed wiring board, electro-optical device, and electronic equipment
JP2002311451A (en) * 2001-04-19 2002-10-23 Seiko Epson Corp Electrode driving device and electronic equipment
US7126571B2 (en) 2001-04-19 2006-10-24 Seiko Epson Corporation Electrode driving apparatus and electronic equipment
US7027043B2 (en) 2002-03-25 2006-04-11 Sharp Kabushiki Kaisha Wiring substrate connected structure, and display device

Also Published As

Publication number Publication date
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