JPH0833851B2 - Virtual machine monitoring method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a virtual computer monitoring method, and more particularly to monitoring information of a virtual computer running by a monitor function of a central processing unit and monitor information of an input / output processing device. This relates to a monitoring method that is effective when collecting data at the same time.

[Conventional technology]

The central processing unit of the real computer has a monitor function,
The operating status of the virtual computer system can be monitored by hardware. This hardware counter is OS
(Operating Systems) Used for performance measurement. However, in a virtual computer system that allows multiple OSs to run simultaneously under one real computer, there is a demand to monitor the operating status of each virtual computer at the same time, which was not possible in the past. It was Further, the input / output processing device of the real computer has a channel monitoring function for collecting the usage status of each input / output device in the area on the main memory designated by the OS. However, in a virtual computer system in which multiple OSs can run simultaneously under one real computer, when using this channel monitoring function, multiple virtual computers cannot use it simultaneously. There is a problem that only one virtual machine can be used. In this case, there is also a demand for simultaneous channel monitoring of a plurality of virtual computers.

Hereinafter, the conventional virtual computer system will be described in more detail. FIG. 2 is a schematic configuration diagram of a real computer system, and FIG. 3 is a schematic diagram of a virtual computer system (hereinafter referred to as VMS) using the real computer of FIG.

In FIG. 1, a real computer system 1 includes a central processing unit (hereinafter, referred to as CPU) 2, a main storage device 3, an input / output processing device (hereinafter, referred to as IOP) 4, and an input / output control device (hereinafter, I).
5), and signal lines 100, 101, and
Connected by 102 and 103. An OS is stored on the main storage device 3, and this controls the entire computer system.

Next, also in FIG. 2, the actual computer system 1 itself is exactly the same as that in FIG. 1, but in that the control program of VMS (hereinafter, referred to as VMCP) is stored in the main memory 3, Different from Figure 1.

The VMCP function for simulating hardware realizes one or a plurality of logical computers (virtual computers, hereinafter referred to as VMs) having an architecture similar to that of the real computer system 1. That is, in FIG.
VM1-1, VM1-2, VM1-3 connected to VMCP by a broken line are virtual computers, and each VM is a logical CPU2-i (i = 1,2,
3), logical main memory 3-i, logical IOP4-i, logical IOC
It is composed of 5-i.

The CPU2-i of each VM is the CPU2 of the real computer system 1
It is realized by allocating to each VM in time division. Each VM
The main storage device 3-i is allocated as a virtual space created and managed by VMCP. In addition, IOP4-i and IOC5 of each VM
-I is realized by occupying or sharing the counterpart of the real computer system 1.

Next, the monitor information collecting function of the CPU 2 will be described in detail. FIG. 4 is an explanatory diagram of a conventional hardware monitor. In FIG. 4, an instruction execution circuit 6,
Hardware monitor mechanism 8, interception execution circuit 1
2, and a VM switching mechanism 24 are provided. An instruction execution microprogram 7 is provided in the instruction execution circuit 6, and a hardware counter group 9, a counter register 10, and a status bit 11 are provided in the hardware monitor mechanism 8. The counter register 10-k (k = 1,2, ... n) is
A counter that monitors specific events in CPU2,
When the corresponding status bit 11-k is "1", the updating of the counter is triggered by the occurrence of the corresponding event. Also,
The interception execution circuit 12 is a mechanism for passing control to the VMCP when an event of passing control to the VMCP occurs during VM running. The VM switching mechanism 24 is a mechanism for switching VMs by hardware and a microprogram.

FIG. 5 is an explanatory diagram of instructions related to the hardware counter in FIG. The instructions related to the hardware counter include (a) read counter instruction, (b) start counter instruction, stop counter instruction, (c) reset counter instruction, and (d) read and reset counter instruction. First, when the read counter instruction is issued, the instruction execution circuit 6 and the instruction execution microprogram 7 read the values of the counter registers 10-1 to 10-n via the line 104, and read the first operand address D1.
The line 100 stores the contents of all counters in the order of the counter numbers in the area on the main storage device 3 designated by (B1). Next, when the start counter instruction is issued, the instruction execution circuit 6 and the instruction execution microprogram 7 cause the status bit 11-k of the counter register 10-k designated by the first operand address D1 (B1) via the line 104. To “1”.
As a result, the update of the counter register 10-k is started.

When the stop counter instruction is generated, the instruction execution circuit 6
And the instruction execution microprogram 7 sets the status bit 11-k of the counter register 10-k designated by the first operand address D1 (B1) via the line 104 to "0". As a result, the update of the counter register 10-k is stopped.

When the reset counter instruction is issued, the instruction execution circuit 6
And the instruction execution microprogram 7 resets the counter register 10-k designated by the first operand address D1 (B1) via the line 104.

When the read and reset counter instructions are issued, the instruction execution circuit 6 and the instruction execution microprogram 7 are
The values of the counter registers 10-1 to 10-n are read out via 104, and the contents of all the counters are stored in the area of the main storage device 3 designated by the first operand address D1 (B1) in the order of the counter numbers. Further, the instruction execution circuit 6 and the instruction execution microprogram 7 reset all the counter registers 10-k (k = 1 to n) via the line 104. Note that as an example of performing performance measurement using the hardware monitor mechanism, IBM System Journal Vol. 18 No. 1 19
79 "Virtual Machine / 370" (IBM System Journal Volume Ei
ghteen Number One "Virtual Machine Facility / 370 (M
ackinnon) 24 pages).

Next, the channel monitoring function in the IOP (input / output processing device) will be described in detail.

 FIG. 10 is an explanatory diagram of a resident VM.

The CPU2-i of each VM is the CPU2 of the real computer system 1
It is realized by allocating to each VM in time division. Each VM
The main storage device 3-i of FIG. 10 is generally allocated as a virtual space created and managed by VMCP. However, like the main storage devices 26 and 27 of the resident VM shown in FIG.
By dividing and allocating the continuous area of, the real storage device address can be made equal to the main storage device address of the virtual machine plus a fixed value. A VM having such a main storage device is called a resident VM. The OS is stored in the main storage device 3-i of each VM,
The main memory 3-i of the resident VM exists on the main memory 3. Furthermore, the IOP4-i and IOC5-i of each VM are realized by occupying or sharing the counterparts of the real computer system 1. For the channel monitoring function, refer to the IBM manual "Operating principle of IBM System 370 Extended Architecture" (IBM System / 370 Extended Arc
hitecture Principles of Operation 17-2).

FIG. 11 is an explanatory diagram of a conventional channel monitoring mechanism. The main memory 3 has a unit control word (hereinafter, UCW) 28-k for storing the state of the input / output device corresponding to each input / output device. Also, in each UCW28-k,
There is an input / output device monitoring valid bit 29-k that indicates whether or not to perform channel monitoring, and a measurement byte index (hereinafter MBI) 30-k that indicates the displacement from the start address (hereinafter MBO) of the monitoring information area. . On the other hand, the IOP4 has a channel monitoring valid bit register 31 indicating whether the real computer system 1 performs channel monitoring and a measurement block origin register (hereinafter referred to as MBO) which holds a start address of an area for storing monitored information. There is a measurement block key register 37 used as a memory protection key when the register) 32 and the channel monitoring mechanism 36 update the main memory 3. The ON / OFF of the channel monitoring valid bit register 31 and the setting of the MBO register 32 are performed by the input / output instruction SCHM (Set Channel Monitor). I / O device monitoring valid bit 29-
The turning on / off of k and the setting of MBI.30-k are performed by the input / output instruction MSCH (Modify Subchannel).

FIG. 12 is an explanatory diagram of the SCHM instruction. The SCHM instruction is an S format instruction. The measurement block key and the channel monitoring valid bit are specified in the general-purpose register GR1 in the CPU2, and the MBO is specified in the general-purpose register GR2. When the SCHM instruction is issued, the CPU 2 sends the values of the registers GR1 and GR2 to the channel monitoring mechanism 16 via the line 101 in FIG. Then, the value of the measurement block key in the register GR1 is set in the measurement block key register 37, the value of the channel monitoring valid bit is set in the channel monitoring valid bit 31, and the value of the register GR2 is set in the MBO register 32.

 FIG. 13 is an explanatory diagram of the MSCH instruction.

The MSCH instruction is an S format instruction. General-purpose register GR1
Is a number that specifies a particular UCW. The second operand address (D2 / B2) is the address of the sub-channel information block (hereinafter, SCHIB) table. The SCHIB stores the I / O device monitoring valid bit specified in the UCW specified by the register GR1 and the MBI. Issuing the MSCH command
As shown in FIG. 11, if the input / output device indicated by the register GR1 via the line 100 is free, the CPU2 will output the corresponding UCW28
-K I / O device monitoring enable bit 29 and MBI
・ Set the value specified by SCHIB to 30.

The channel monitoring valid bit register 31 is "1" and the I / O device monitoring valid bit 2 of UCW28-k
When 9 is "1", the input / output device corresponding to this UCW28-k is to be monitored. Then, every time an event to be monitored occurs in this input / output device, the channel monitoring mechanism 16 sets the measurement block key register in the area on the main storage device 3 which is obtained from the MBO register and the MBI.30. Access with 37 as the protection key and update the monitor information.

[Problems to be solved by the invention]

As described above, the hardware monitor mechanism 8 is
It has a function of collecting the status of the CPU2 and reporting it to the OS by an instruction. However, when the hardware monitor mechanism 8 is used in a virtual computer system, information of the entire system is collected in the counter register 10, and there is a problem that it is not possible to collect monitor information for each VMCP or VM.

Also, as described above, the IOP of the computer with the extended architecture has a channel monitoring mechanism that collects the usage status of each I / O device.However, when trying to perform channel monitoring in a virtual computer system, the MBO register 32 is transferred to the system. Since there is only one, there is a problem that multiple VMs cannot be used at the same time.

A first object of the present invention is to improve the conventional problems as described above, and collect the hardware monitor information during VMCP running and VM running separately and simultaneously collect the hardware information for each VM. It is to provide a monitoring method of VMS that can be done. A second object of the present invention is to provide a VMS monitoring method capable of collecting the usage status of an input / output device for each VM using the input / output device.

[Means for solving problems]

In order to achieve the above object, the VMS monitoring method according to the present invention is provided with a counter register for collecting monitor information of the central processing unit in the central processing unit, and designated by an instruction from the central processing unit. An I / O processor that collects the usage status of I / O devices is connected to the measurement area on the main memory, and a control program that manages the simultaneous running of one or more OSs is provided to the OSs. A virtual computer system that realizes a virtual computer is characterized by having at least one of the counter register or the address of the measurement area designated by the OS and the identifier of the virtual computer, or both of them, respectively. Further, the central processing unit has means for identifying whether the virtual computer is running or the control program is running,
In one of the counter registers of the set or more, the central processing unit collects monitor information while the control program is running,
Another one or more is characterized in that the central processing unit collects monitor information while the virtual computer is running. further,
It is characterized in that an identifier of a virtual computer that is currently using the input / output device is provided for each input / output device, and the usage status of the input / output device of the virtual computer is collected in the measurement area of the OS on the virtual computer.

[Action]

In the present invention, the CPU is provided with a register for identifying that the VM is running and a register for identifying that the VMCP is running, and two sets of counter registers are provided. One counter collects the monitor information while the VMCP is running, and the other counter collects the monitor information while the VM is running. In that case, the above-mentioned counter register read instruction, update start instruction, update stop instruction, reset instruction, and read / reset instruction are used.

Further, in the present invention, one or a plurality of sets of registers for setting the MBO of the VM and unique numbers for identifying the VM are provided in the IOP, and the CPU sets these in the registers. Further, the CPU identifies which VM is in use for each IOP.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a VMS showing a first embodiment of the present invention, and FIG. 6 is an explanatory diagram of hardware monitor related instructions.

As shown in FIG. 1, in this embodiment, two sets of hardware counter groups 9-1 and 9-2 are provided in the hardware monitor mechanism 8 of the CPU 2. The hardware counter group 9-1 collects monitor information while the VMCP is running, and the hardware counter group 9-2 collects monitor information when the VM is running. Further, a traveling mode display register 14 is newly provided. The running mode display register 14 is "1" while the VMCP is running and is "0" while the VM is running.

First, a method of setting the traveling mode display register 14 will be described. When an event of passing control to VMCP occurs during running of the VM, the interception execution circuit 12 and the interception microprogram 13 set “1” in the traveling mode display register 14 via the line 109. Also, VMCP is VM
Is dispatched, the instruction execution circuit 6 and the instruction execution microprogram 7 are executed by the dispatch instruction.
Sets “0” in the traveling mode display register 14 via the line 107.

Next, updating of the hardware counter groups 9-1 and 9-2 will be described. Value of drive mode display register 14 is "1"
And the status bit 11- of the counter register 10-1-k
If 1-k is "1", the counter register 10-1-k of the VMCP hardware counter group 9-1 is being updated. The value of the running mode display register 14 is "0" and the status bit 11 of the corresponding counter register 10-2-k is 11
If "-2-k" is "1", the counter register 10-2-k of the VM hardware counter group 9-2 is being updated. In cases other than the above, counter registers 10-1-k,
None of 10-2-k is updated.

Next, the instructions relating to the hardware counter according to this embodiment will be described with reference to FIG. In FIG.
The mode instruction bit 15 set in the general-purpose register GR1 is
In the case of "1", it is instructed to operate the hardware counter group 9-1, and in the case of "0", it is instructed to operate the hardware counter group 9-2. The read counter extension instruction, the start counter extension instruction, the stop counter extension instruction, the reset counter extension instruction, and the read / reset counter extension instruction shown in FIG. 6 are all hardware counter groups 9-1 designated by the general-purpose register GR1. Alternatively, the same processing as the above-described respective instructions (read counter instruction, start counter instruction, stop counter instruction, reset counter instruction, read / reset counter instruction) is performed on 9-2. The instruction code existing in the related art and its extension instruction, for example, the read counter instruction and the read counter extension instruction may have the same instruction code. If they are the same, when the command is issued, the running mode display register
When 14 is “1”, that is, when VMCP issues,
It processes the extended instruction issued by this issue. When the traveling mode display register 14 is “0” at the time of issuing an instruction, that is, when the VM issues it, the instruction of the hardware monitor existing in the past is processed.

FIG. 7 is a block diagram of a VMS showing a second embodiment of the present invention. In the embodiment of FIG. 7, in addition to the configuration of FIG.
A save area address register 16 is provided. The save area address register 16 holds the address of the save area 17-i (1,2) for saving the state of the CPU of the VM currently running. The save area 17-i is required to start the VM.
CPU information is stored, and the hardware counter group 9 of the corresponding VM is also included in the information.

When the dispatch instruction of the VM is issued by designating the address of the save area 17-i, the following processing is performed. First, the instruction execution circuit 6 and the instruction execution microprogram 7 are
The address of the save area 17-i is set in the save area address register 16 via 105, and "0" is set in the running mode display register 14 via the line 107. In addition, the contents of the hardware counter group of the corresponding VM stored in the save area 17-i via the line 100 and the line 104 are displayed in the hardware counter group 9-
Set to 2. After that, the VM is dispatched by setting the status information of the corresponding VM stored in the save area 17-i to the CPU 2 via the line 100.

When an event occurs in which control is passed to VMCP while the VM is running, the interception execution circuit 12 and the interception microprogram 13 execute the following processing.
First, “1” is displayed in the traveling mode display register 14 via the line 109.
And save area address register 16 via line 105
Save area 17-
In i, the contents of the hardware counter group 9-2 are saved via the lines 114 and 100. In addition, the CPU via line 100
The state information of 2 is saved in the save area 17-i. Then VMC
Pass control to P.

Next, when the VM is switched by the VM switching mechanism 24, the following processing is performed. First, the contents of the save area address register 16 are read via the line 116, and the hardware counter group 9-2 is placed in the save area 17-1 having this address.
And the other states of the CPU 2 are saved via the line 100.
Then, the VM switching mechanism 24 is an evacuation area for the VM to be run next.
Select 17-2. In addition, the escape area 17-
Set the address of 2 to the save area address register 16,
The contents of the hardware counter group of the corresponding VM stored in the save area 17-2 are set in the hardware counter group 9-2 via the lines 100 and 115. Further, the state information of the VM stored in the save area 17-2 is set in the CPU 2 via the line 100, and the VM is dispatched. The method of updating the hardware counter groups 9-1 and 9-2 is exactly the same as in the first embodiment.

As for the instruction related to the hardware counter, the instruction related to the hardware counter when the VM is running, that is, when the running mode display register 14 is “0” may operate the hardware counter group 9-2. Also,
The instruction regarding the hardware counter when the VMCP is running, that is, when the running mode display register 14 is "1", is the same as that described in the first embodiment, as long as the hardware counter group 9-1 is operated. .

FIG. 8 is a block diagram of a VMS showing a third embodiment of the present invention, and FIG. 9 is an explanatory diagram of hardware monitor-related instructions in the third embodiment.

In FIG. 8, unlike the second embodiment, the value of the hardware counter group of the corresponding VM is not saved in the save area 17-i. Further, there is a VMid field in the save area 17-i, which holds a number specified by VMCP uniquely for each VM. As shown in FIG. 8, in the third embodiment, the structure of the second embodiment shown in FIG.
The VMid register 23 and the local storage 18 are added. Reference numeral 19 in the local storage 18 is a save area table. The backup area table 19 is the VM in the local storage
It consists of multiple sets of id20 and local storage save area address 21. As the save area for the hardware counter group of the VM, the save area in the local storage 22-pointed to by the save area address 21 in the local storage paired with the VMid 20-p in the local storage having a value that matches the VMid of this VM p is used.

When the VM dispatch instruction is issued with the save area address specified, the following processing is performed. First, the instruction execution circuit 6 and the instruction execution microprogram 7 set the address of the save area 17-i in the save area address register 16 via the line 105, and set “0” in the running mode display register 14 via the line 107. Set "and also traveling via line 110 VMi
d Set VMid in register 23. Further, the contents of the local storage evacuation area 22-p corresponding to the VMid set in the running VMid register 23 via the line 106 are set to the hardware counter group 9-2 via the line 104. further,
Instruction execution circuit 6 and instruction execution microprogram 7
Shows the status information of VM stored in the save area 17-i.
Dispatch the VM by setting it to CPU2 via 100.

Next, when an event of passing control to VMCP occurs during VM running, the interception execution circuit 12 and the interception microprogram 13 perform the following processing. First, the line
Set “1” in the driving mode display register 14 via 109. Further, the contents of the running VMid register 23 are taken out via the line 111, and the contents of the hardware counter group 9-2 are put into the save area 22-p in the local storage having this as VMid via the lines 114 and 112. evacuate.

Next, when the VM is switched via the VM switching mechanism 24, the following processing is performed. First, the contents of the save area address register 16 are read via the line 116, and the state of the CPU 2 is saved via the line 100 to the save area 17-1 having this address. Next, the value of the running VMid register 23 is read via the line 117, and the state of the hardware counter group 9-2 is saved to the save area 22-p in the local storage corresponding thereto via the lines 114 and 118. Next, VM switching mechanism
24 sets the address of the save area 17-2 of the VM to be run next in the save area address register 16 and sets the corresponding VMid in the running VMid register 23 via the line 117. The save area in the local storage corresponding to this VMid
The contents of 22-p are set in the hardware counter group 9-2 via the lines 118 and 115. Furthermore, the method of updating the hardware counter groups 9-1 and 9-2 is exactly the same as in the first embodiment.

For instructions on hardware counters, see Section 9.
The extended instruction shown in the figure is used, and an instruction related to the hardware counter when the VM is running, that is, when the running mode display register 14 is “0” operates the hardware counter group 9-2. Further, as for the instruction regarding the hardware counter when the VMCP is running, that is, when the running mode display register 14 is "1", as shown in FIG.
Specify VMid for. If the VMid is "0", the hardware counter group 9-1 is operated, and if the VMid is other than "0", the save area 22-p in the local storage 18 of the corresponding VM is operated.

Although not described in detail, as the VMid, a correspondence table of the software VMid specified by VMCP and the hardware VMid used in the hardware may be prepared, and the hardware VMid may be used in the hardware. . In this case, the hardware VMid is set in the running VMid register 22 in FIG. When the VM is dispatched, the software VMid is converted into the hardware VMid by the correspondence table and set in the running VMid register 23. Further, in the instruction related to the hardware counter, the software VMid may be designated, the instruction execution circuit 6 and the instruction execution microprogram 7 may convert the instruction into the hardware VMid, and the corresponding save area 22 in the local storage may be processed. It is possible.

As described above, in the first, second, and third embodiments, the hardware monitor information during VMCP running of the VMS and the hardware monitor information during VM running are separately extracted, and the hardware monitor information for each VM is collected at the same time. Both can be done.

Next, the channel monitoring function in IOP will be described in detail. FIG. 14 shows a fourth embodiment of the present invention.
FIG. 15 is a configuration diagram of the VMS, and FIGS. 15 and 16 are explanatory diagrams of instructions used in this embodiment.

As shown in FIG. 14, this embodiment is different from the conventional channel monitoring mechanism 36 shown in FIG. 11 in that it has two or more MBO registers 32. Although two MBO registers 32-1 and 32-2 are provided in FIG. 14, it is of course possible to provide three or more. Also, for each MBO register 32-j, channel monitoring valid bit 31-j, measurement block key register 37-j,
It has a VMid field 34-j. VMid field 34
A number uniquely given to each VM by VMCP is set in -j. Further, in the present embodiment, the in-use VMid field 35-k is provided in the UCW 28-k.

First, in-use VMi of the UCW28-k provided in this embodiment
d Field 35-k setting method and channel monitoring enable bit 31-j in IOP4, MBO register 32-j, V
Each setting method of the Mid field 34-j will be described.

First, SCHME (Set C
channel monitor enable bit 31-1, the MBO register 32-j, and the VMid field 34-j are set. As shown in FIG. 15, the SCHME instruction is a so-called S format instruction. General-purpose register GR1
Specifies the measurement block key, VMid, and channel monitoring enable bit, and the general-purpose register GR2 contains MBO.
Is set. Issuing the SCHME instruction causes CPU2 to go to line 1
The values of the general-purpose registers GR1 and GR2 are sent to the channel monitoring mechanism 36 'in IOP4 via 01. The channel monitoring mechanism 36 ', if there is a field having a VMid field 34-j that matches the VMid shown in the general register GR1,
The field is targeted for updating, but if there is no corresponding field, the field whose channel monitoring valid bit 34-j is "0" is targeted for updating. If there is no field to be updated, 3 is returned as the condition code. When the update field is present, the value specified in the general register GR1 is set in the channel monitoring valid bit 31-j of the corresponding field, and the MBO register 32 is set.
-J is the value of general register GR2, and VMid field 34-
VMid indicated in the general-purpose register GR1 is set in j.

Next, the setting method of the input / output device monitoring valid bit 29-k, MBI 30-k, and VMid field 35-k in use of the UCW 28-k will be described. This is performed by a new instruction MBCHE (Modify Subchannel Extended) instruction in this embodiment. As shown in FIG. 16, the MSCHE instruction is a so-called S format instruction. Second operand address (D2
/ B2) is a SCIBE that has a VMid in SCHIB (SCHIB Ex
tended) The address of the table. Further, a number for identifying the input / output device is designated in the general-purpose register GR1. MSC
It is the same as the MSCH instruction in that when the HE instruction is executed by the CPU2, the contents of the SCIBE table are set to UCW28-k via the line 100. Here, UCW28-k corresponds to the input / output device indicated in the general-purpose register GR1. further,
In the MSCHE instruction, the value of VMid in SCIBE is in use VMi
Set in d field 35-k. As an opportunity to issue the MSCHE instruction, if the input / output device is exclusively used by a specific VM, the currently used VMid field 35-k is set when the input / output device is occupied. Furthermore, in the case of an I / O device that is shared by multiple VMs, by issuing MSCHE for each I / O command from the VM, the VMid in use
Set field 35-k.

Finally, the channel monitoring mechanism in this embodiment
36 'will be described. Channel monitoring mechanism 3
The usage status of each I / O device collected by 6'is that the I / O device monitoring valid bit 29-k in UCW28-k is "1".
When the VMid field 31-j corresponding to the used VMid field 35-k exists and the channel monitoring valid bit 34-j is "1", the content of the MBO register 32-j is M.
The storage protection key is accessed as the measurement block key register 37-j in the area to which the value of BI30-k is added, and this is updated. However, in this embodiment, it is not applied to all VMs, but only to resident VMs. This is because the usage status of each I / O device collected by the channel monitoring mechanism 36 'is directly updated on the main storage device 3, so that the main storage device 3-i of the VM is stored on the main storage device 3. This is because the page needs to be fixed.
Although not described in detail in this embodiment, VMCP is a resident VM.
At the same time, this channel monitoring mechanism 36 'can be used.

As described above, in this embodiment, it is possible to simultaneously support channel monitoring for a plurality of resident VMs, and it is also possible to simultaneously support channel monitoring of VMCP and one or more resident VMs.

〔The invention's effect〕

As described above, according to the present invention, when running VMCP
It is possible to collect the hardware monitor information when the VM is running individually, and to collect the hardware monitor information for each VM at the same time. Furthermore, according to the present invention, it becomes possible to collect the usage status of the input / output device for each VM that has used the input / output device.

[Brief description of drawings]

FIG. 1 is a block diagram of a virtual computer system (VMS) that executes a hardware monitoring method according to a first embodiment of the present invention, FIG. 2 is a configuration diagram of a general real computer system, and FIG. VMS configuration diagram, FIG. 4 is a configuration diagram of a VMS that executes a conventional hardware monitoring system, FIG. 5 is an explanatory diagram of conventional hardware monitor related instructions, and FIG. 6 is a hardware monitor related instruction in the present invention. 7 is a block diagram of a VMS that executes the hardware monitoring method according to the second embodiment of the present invention, and FIG. 8 is a block diagram of the VMS that executes the hardware monitoring method according to the third embodiment of the present invention. FIG. 9 is a block diagram of a VMS that executes the VMS, FIG. 9 is an explanatory diagram of hardware monitor related instructions of the third embodiment, FIG. 10 is an explanatory diagram of a resident VM, and FIG. 11 is a block diagram of a VMS that executes a conventional channel monitoring method. FIG. 12 and FIG. 13 are explanatory diagrams of conventional channel monitoring related instructions, FIG. 14 is a block of VMS for executing the channel monitoring method showing the fourth embodiment of the present invention, FIG. 15 and FIG. The figure is an illustration of the channel monitor related instructions in the present invention. 1: Real computer system, 2: Central processing unit (CPU), 3: Main memory, 4: Input / output processing unit (IOP), 5: Input / output control unit (IOC), 6: Instruction execution circuit, 7: Instruction Execution microprogram, 8: Hardware monitor mechanism, 9: Hardware counter group, 10: Counter register, 11: Status bit, 12: Interception execution circuit, 13: Interception microprogram, 14: Running mode display register, 15: Mode instruction bit, 16: Save area address register, 17: Save area, 18: Local storage, 19: Save area table, 2
0: VMid in local storage, 21: save area in local storage, 23: running VMid register, 24: VM switching mechanism,
26, 27: Main memory of resident VM, 28: UCW (Unit Control Wor
d), 29: I / O device monitoring enable bit, 30: MBI
(Measurement byte index), 31: channel monitoring valid bit, 32: MBO (measurement block origin) register, 33: measurement block, 34: VMid field, 35: VMid field in use,
36, 36 ': Channel monitoring mechanism, 37: Measurement block key register.

Claims (6)

[Claims] 1. A central processing unit is provided with a counter register for collecting monitor information of the central processing unit, and an input / output device is provided in a measurement area on a main memory designated by an instruction from the central processing unit. In a virtual computer system that connects an input / output processing device that collects usage status and has a control program that manages simultaneous running of one or more OSs, and realizes a virtual computer for the OSs, A monitoring system for a virtual computer system, characterized in that it has at least one or both of a combination of an address of the measurement area and an identifier of a virtual computer designated by a register or an OS, or both. 2. A central processing unit is provided with a counter register for collecting monitor information of the central processing unit, and an input / output device is provided in a measurement area on a main storage device designated by an instruction from the central processing unit. In a virtual computer system that connects an input / output processing device that collects usage status and has a control program that manages simultaneous running of one or more OSs, and realizes a virtual computer for the OSs, Whether the virtual computer is running or the control program is running in the central processing unit, with one or both of the combination of the address of the measurement area specified by the register or the OS and the identifier of the virtual computer, or both. For monitoring the running information of the control program in the central processing unit in one of the two or more sets of counter registers. Monitoring method of a virtual computer system virtual machine and wherein to collect monitor information traveling in the central processing unit is more than the other one. 3. The control program counter register and the virtual computer counter register set a read command, an update start command, an update stop command, a reset command, and a read / reset command for the counter register, respectively. A method of monitoring a virtual computer system according to claim 2. 4. The counter register has a save area for storing the contents of the counter register and a save area for a status bit indicating whether the counter register is being updated or stopped, for each virtual computer, in a main memory unit or a central processing unit. It is installed in the local storage inside and when running a virtual machine,
If the status bit of the save area of the relevant virtual computer indicates that the counter is being updated, the update is stopped, and if control is passed to the control program or another virtual computer while the virtual computer is running, the above The monitor information is collected for each virtual computer by saving the values of the counter register and the status bit for the virtual computer in the save area of the virtual computer.
The method of monitoring the virtual computer system described in the item. 5. The central processing unit is provided with a counter register for collecting monitor information of the central processing unit, and the input / output unit of the input / output unit is provided in a measurement area on a main memory designated by an instruction from the central processing unit. In a virtual computer system that connects an input / output processing device that collects usage status and has a control program that manages simultaneous running of one or more OSs, and realizes a virtual computer for the OSs, One or both of the combination of the address of the measurement area specified by the register or the OS and the identifier of the virtual computer, or two or more pairs each, and the identifier of the virtual computer currently using the I / O device for each I / O device A monitoring method for a virtual computer system, characterized in that the usage status of the input / output device of the virtual computer is collected in the measurement area of the OS on the virtual computer. 6. For a combination of an address of a measurement area of an OS on the virtual machine and an identifier of the virtual machine, an instruction to set the combination and the input / output device currently using the input / output device. And a command for setting the identifier of the virtual computer according to claim 5, wherein the monitoring method of the virtual computer system according to claim 5.