JPH0833720B2 - Display controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image display device, and more particularly to a display control device that displays a cursor on a display screen.

[Conventional technology]

Using a CRT display as a display device, text (hereinafter referred to as text) stored in a memory (for example, a refresh memory using dynamic memory), graphics,
A function of displaying information such as an image (hereinafter referred to as a graphic) is one of important functions of the display processing device.

Recently, new media-related devices such as personal computers, word processors and captain systems have spread to general households, and the importance of display processing as a man-machine interface is increasing, including in fields related to business such as office automation equipment. It is increasing more and more, and at the same time, screen display forms are diversifying.

Conventionally, in this type of display device, information to be displayed on the screen, such as text and graphics, is stored in a refresh memory, which is sequentially read out in synchronization with the scanning timing of the CRT, converted into a video signal, and converted into a video signal. A method of displaying by supplying is adopted.

In particular, in the diversifying screen display modes, dividing the text screen or the graphic screen into a plurality of areas to display the text screen and the graphic screen allows the text screen and the graphic screen to be mixed and displayed at the same time. It is an indispensable function in applications such as executing multiple tasks on a console, and there is a demand for screen displays that are easier to see and have better operability.

When editing, such as inserting, deleting, or changing the display information on the display screen using a keyboard or the like,
It is common to display a cursor on a display screen and use it as a pointing device. Further, as a method of not only displaying the cursor pattern as it is, but also clearly distinguishing it from the original display information, a method of blinking the pattern at a fixed time interval (hereinafter referred to as blink) is generally adopted.

FIG. 9 is a block diagram showing an example of the conventional display device described above.

In the device of FIG. 9, the microprocessor 101 controls the operation of the entire system via the system bus 102, causes the main memory 103 to store the programs and processing data executed by the microprocessor 101, and the peripheral control circuit 106. Interface with a keyboard 107 or a disk device 108 for external storage, and manipulates the display data of the refresh memory 104 via the display control circuit 105 to perform a desired CRT display, thereby realizing various processing functions. Display control circuit 105
Generates an address for the refresh memory 104 in synchronization with the display timing generated by itself. The read display data is subjected to parallel-serial conversion by the video signal generation circuit 109 to generate a serial video signal and supplied to the CRT 110.

FIG. 10 is a block diagram showing a cursor display circuit in a conventional display control device.

The cursor address register 201 stores a memory storage address of display data at a position where a cursor can be displayed, which can be written from the microprocessor 101. The display address generation circuit 202 generates the display address of the refresh memory 104 of FIG. 9 based on the display timing information generated by the display control circuit 105 of FIG. The outputs of the cursor address register 201 and the display address generation circuit 202 are input to the comparison circuit 203, and the cursor generation timing signal 208 is generated at the timing when the two coincide. The cursor-on period designation register 204 and the cursor-off period designation register 205 are writable by the microprocessor 101, and store the lighting time interval and the extinction time interval in the blinking operation of the cursor, respectively. The cursor display timing generation circuit 206 uses the cursor-on period designation register 204.
The time counting operation is performed based on the setting data of the cursor off period designation register 205 and the cursor display signal 209 is controlled to drive the cursor pattern generation circuit 207. The cursor display pattern output from the cursor pattern generation circuit 207 is the video signal generation circuit of FIG.
It is combined with the display data in 109 and output to the CRT 110.

[Problems to be solved by the invention]

The conventional display control device described above has the following disadvantages.

(1) When displaying a split screen as described above, since only one cursor having a uniform shape can be displayed over each of the split screens, for example, a plurality of similar screens can be simultaneously displayed and displayed from the keyboard. The operability is poor in terms of distinguishing these screens when trying to edit data, and warnings when the cursor is moved to a screen area where data cannot be written.

(2) On the other hand, in order to control the cursor display in correspondence with each of the divided screens, dedicated complicated hardware for determining the display area is required, and the entire system becomes large-scale and economical. Not. Further, if an attempt is made to control the cursor display in such a split screen by a general-purpose microprocessor, complicated processing for managing the display address and display area of each screen in the split screen is required. The load on the processor increases and the screen response speed decreases.

An object of the present invention is to improve the operability of cursor display during such split screen display, improve the performance of the entire display system, and minimize the load on the microprocessor.
It is an object of the present invention to provide a display control device with good responsiveness and good economy.

[Means for solving problems]

The display control device of the present invention outputs a refresh memory in which character code data is stored, an address of the refresh memory and a sync signal of a CRT display, and counts and outputs a raster address of a character row, A timing control circuit including a raster counter that outputs the carry of the count as an interrupt signal; a character pattern is stored; and the character pattern is read based on the character code data and the raster address read from the refresh memory. A character generator, a rewritable control flag that stores the display form of the cursor, a cursor address register that stores display position information on the CRT of the cursor, and display address information that is output from the timing control circuit. And a display position information of the cursor address register, and outputs a cursor generation timing signal when the two coincide with each other, and a cursor when the cursor generation timing signal is output and the control flag is in a predetermined state. A cursor display circuit for generating a display pattern, a video signal generation circuit for inputting and combining the character pattern and the cursor display pattern and sending out as a video signal to a CRT display, and when an interrupt signal from the timing control circuit is input. In a predetermined character line, a microprocessor that performs interrupt processing for rewriting the contents of the control flag, and a program memory that stores the interrupt processing program executed by the microprocessor are included.

[Action]

The present invention provides a control flag for storing information designating a display form of a cursor, and by executing a process of rewriting the content of the control flag in a desired display area by a program activated in synchronization with display timing. ,
This is to make it possible to easily realize high-performance cursor display control while significantly reducing the conventional hardware.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the display control device of the present invention.

1 controls the operation of the entire system by a microprocessor 1, stores a program to be executed by the microprocessor 1 in a program memory 2, a processing data of the microprocessor 1 in a data memory 3, and outputs the data through a multiplexer 6. By operating the display data of the refresh memory 7, a desired CRT display is realized. Character code data is stored in the refresh memory 7 as display information. The timing control circuit 5 synchronizes with the display timing generated by itself and refresh memory 7
Display address 510 for the character generator 8, raster address 58 for the character generator 8, and the video signal generation circuit 9
And a sync signal 511 for the CRT 10 are generated. The character code data 701 read from the refresh memory 7 is supplied to the character generator 8, and a character pattern 801 such as a character is read from the character generator 8 based on the raster address 58. This character pattern 801
Is supplied to the video signal generating circuit 9 and is sent to the CRT 10 as the video signal 901 together with the synchronizing signal 511. The address decoder 4 outputs strobe signals 41 and 42, respectively, when the microprocessor 1 reads and writes the contents of a line counter 55 and a control flag 13 described later. During the blanking period of the synchronizing signal 511, the multiplexer 6 switches the address of the refresh memory 7 to the address bus 11 of the microprocessor 1 so that the data in the refresh memory 7 can be rewritten. If it is not during the blanking period, the output of the display address 510 from the timing generation circuit 5 is connected. As a variable to be processed by the program in the data memory 3, a blink bit BL indicating the content of the control flag 13 for designating the presence / absence of cursor display, obtained by keyboard input, etc., and an on-count number indicating the lighting time of the blink cycle of the cursor. ONC and OFF count number OFFC that indicates disappearance time, field count number FC that stores the count number of cursor blink synchronization time, blink start line position that indicates the blink effective area of the cursor in the split screen
BSP, blink end line position BEP, and total line number TN indicating the total number of lines in one screen field are assigned.

FIG. 2 is a detailed block diagram of the timing control circuit 5 shown in FIG. OSC51 CRT character pattern
A dot clock 57 for serial transmission to 10 is generated, and the dot counter 52 generates 1 based on the dot clock 57.
Count the number of horizontal dots of the character. The character counter 53 counts the number of characters in one horizontal scanning line based on the carry of the dot counter 52. The raster counter 54 is 1 based on the carry of the character counter 53.
Count the raster address of a character line. The carry output of the raster counter 54 is supplied to the microprocessor 1 as an interrupt signal 59. The line counter 55 counts the number of character lines on one display screen based on the carry of the raster counter 54, and is selected by the strobe signal 41 and can be read from the microprocessor 1. The address generation circuit 56 generates a display address 510 from the outputs of the character counter 53 and the line counter 55 and supplies it to the refresh memory 7 and a cursor display circuit 20 described later. The output of the raster counter 54 is supplied to the character generator 8 as a raster address 58. The synchronizing signal generation circuit 512 generates a synchronizing signal 510 for horizontal scanning and vertical scanning based on the dot clock 57 and supplies it to the CRT 10.

FIG. 3 is a detailed block diagram of the control flag 13 and the cursor display circuit 20 shown in FIG. The control flag 13 is a 1-bit register that stores the status of cursor display. It is writable by the microprocessor 1 and is selected by the strobe signal 42. The cursor address register 21 is writable by the microprocessor 1,
The storage address in the refresh memory 7 of the display data at the position where the cursor should be displayed is stored. The output of the cursor address register 21 is input to the comparison circuit 22 together with the output of the display address 510 of the refresh memory 7 from the address generation circuit 56, and activates the cursor generation timing signal 23 when they match. The cursor generation timing signal 23 becomes a cursor display signal 25 as a result of AND logic with the output of the control flag 13 by the AND circuit 24, and drives the cursor pattern generation circuit 26 at the timing when the cursor display signal 25 is active. The rectangle output from the cursor pattern generation circuit 26,
The cursor display pattern 27 such as an underline is combined with the character pattern 801 by the video signal generation circuit 9 in FIG.
Output to RT10.

FIG. 4 is a flow chart of the interrupt program processing of the microprocessor 1 activated for each row by the interrupt signal 59 from the raster counter 54. 1 according to FIG.
Control flag for blinking and displaying 4 cursors
The update process of 13 will be described.

First, the contents of the line counter 55 are read out and compared with the total number of lines TN in one screen (step 61), and it is judged whether they match (step 62). If they do not match, the line of the line counter 55 continues. Count value and blink start line position BSP and blink end line position B
A comparison is made with the EP (step 63), and it is determined whether or not it is a blink effective area (step 64). If it is not the blink valid area, the control flag 13 is set (step 65). If it is the blink valid area, the contents of the blink bit BL are set to the control flag 13 (step 66), and then the interrupt program processing is terminated and the main program is finished. Return to processing. On the other hand, if the contents of the line counter 55 and the total line number TN match, the field count number FC is decremented by -1 (step 67). It is determined whether the field count FC is zero (step 68), and if it is not zero, the contents of the blink bit BL are set in the control flag 13 (step 66), the interrupt program processing is terminated, and the main program processing is resumed. . Also, the field count
If FC is zero, the state of the blink bit BL is checked (step 69). It is determined whether the blink bit BL is in the reset state (step 70), and if it is in the set state, the field count number FC is set to the off count number OFFC (step 71), the blink bit BL is reset (step 72), and then the blink bit is set. The contents of BL are set in the control flag 13 (step 66), the interrupt program processing is terminated, and the processing returns to the main program processing. Meanwhile, blink bit
If BL is in the reset state, set the on-count number ONC to the field count number FC (step 73) and set the blink bit BL (step 74).
Is set in the control flag 13 (step 66), the interrupt program process is terminated, and the process returns to the main program process.

Through the series of processes described above, as shown in FIG. 5, the blink start line position BSP and the blink start line position BSP according to the display position of the screen (hereinafter referred to as the active screen) currently being edited out of the plurality of split screens. Only by setting the end line position BEP, the blinking operation is performed only when the cursor is in the active screen area, and when the cursor is not in the active screen area, the blinking operation is fixed and displayed.

Further, as shown in FIG. 6, by setting appropriate values to the on-count number ONC and the off-count number OFFC, the blinking cycle and the ratio of the lighting time to the extinction time can be arbitrarily changed to move the cursor. Can be displayed.

At this time, the processing of the microprocessor 1 is only simple comparison, calculation, and transfer by interruption, and the processing time is extremely short.

 Next, a second embodiment of the present invention will be described.

The block diagram of the display control device of the second embodiment is the same as the first embodiment.
This is the same as the block diagram of the first embodiment shown in FIGS. 2, 2 and 3, and its operation is the same as that of the first embodiment, so its detailed description is omitted.

As the variables to be processed by the program in the data memory 3, the contents of the control flag 13 for designating the presence / absence of cursor display obtained by keyboard input or the like are shown in accordance with the display areas of the split screen A, split screen B, and split screen C, respectively. Blink bit BLA, BLB, BLC, ON count number that indicates lighting time of each blink cycle of cursor ONCA, ONC
B, ONCC and OFF count number OFF indicating the disappearance time of each
Field count number FC that stores each count number of CA, OFFCB, OFFCC, and blink cycle time of cursor
Cursor A display address CDA, cursor B display address CDB, cursor C display address CDC, split screen that indicates the display memory address position of the cursor displayed for each of A, FCB, FCC, split screen A, split screen B, and split screen C A,
The screen A start position SPA indicating the display start line position of each of the split screens B and C, the screen B start position SPB, the screen C start position SPC, and the total line number TN indicating the total line number of one screen field are allocated. ing.

FIG. 7 is a flow chart of the interrupt program process of the microprocessor 1 which is activated line by line by the interrupt signal 59 from the raster counter 54. According to FIG.
A process of updating the control flag 13 and the cursor address register 21 for blinking and displaying a plurality of cursors will be described.

First, the content of the line counter 55 is read and compared with the total number of lines TN in one screen (step 81), and it is determined whether they match (step 82). If they do not match, the line count value of the line counter 55 is used. The screen A start position SPA, the screen B start position SPB, and the screen C start position SPC are compared (step 83) to determine whether the current line is the screen A display area, the screen B display area, or the screen C display area ( Step 84). If it is the screen A display area, the cursor A display address CDA is set in the cursor address register 21 (step 85), the content of the blink bit BLA is set in the control flag 13 (step 86), and then the interrupt program processing is terminated, and the main Return to program processing. If it is the screen B display area, the cursor B display address CDB is set in the cursor address register 21 (step 87), the content of the blink bit BLB is set in the control flag 13 (step 88), and then the interrupt program processing is terminated, and the main Return to program processing. If it is the screen C display area, the cursor C display address CDC is set in the cursor address register 21 (step 89), the content of the blink bit BLC is set in the control flag 13 (step 90), and then the interrupt program processing is terminated, and the main Return to program processing. On the other hand, if the contents of the line counter 55 and the total number of lines TN match in step 82, the blink bits BLA, BLB, BLC are updated for each of the cursors A, B, C, but for each cursor. Except that the processing variable names differ among the three types of cursors, a series of procedures from step 67 to step 74 in the flowchart of the interrupt program processing of the first embodiment shown in FIG. Since it is the same as,
The cursor A blink processing (step 91), the cursor B blink processing (step 92), and the cursor C blink processing (step 93) will be referred to for each of B and C, and detailed description thereof will be omitted. Cursor A blink process (step 91), Cursor B blink process (step 9)
2) After the blinking of the blink bits BLA, BLB, BLC by the cursor C blink processing (step 93), the interrupt program processing is terminated and the main program processing is resumed.

By the above series of processing, when there are a plurality of split screens on the display screen, one cursor is displayed on each split screen at a time in a one-to-one correspondence, and the cursors are independently displayed. The blinking cycle and the ratio of lighting time to extinction time are controlled and displayed.

FIG. 8 is a timing chart of the cursor blink operation when the blink operation cycle and the ratio of the lighting time to the extinction time are specified under different conditions for each of the three types of cursors.

Although the blinking operation of one or a plurality of cursors in the divided text screen is shown in the above-mentioned embodiment, the color display of the cursor and the display of the graphic cursor in the graphic screen can be easily performed by using the device of the present invention. It can be easily inferred that the same control can be realized.

〔The invention's effect〕

As described above, the present invention can improve the operability of cursor display during split screen display, and can provide a display control device having an advanced cursor control function.
Highly flexible display control device with minimal hardware, such as simple processing by a microprocessor that enables advanced display processing without the need for special dedicated hardware. There is also an effect that can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the display control device of the present invention, FIG. 2 is a detailed block diagram of the timing control circuit 5 of FIG. 1, and FIG. 3 is a control flag 13 of FIG. FIG. 4 is a detailed block diagram of the cursor display circuit 20, FIG. 4 is a flowchart of the interrupt program processing of the first embodiment, FIG. 5 is a display example of the first embodiment, and FIG. 6 is the first embodiment. FIG. 7 is a timing chart of the cursor blink operation in FIG. 7, FIG. 7 is a flowchart of the interrupt program processing of the second embodiment of the present invention, FIG. 8 is a timing chart of the cursor blink operation in the embodiment of FIG. 7, and FIG. FIG. 10 is a block diagram of a cursor display circuit in a conventional display device. 1... Microprocessor, 2... Program memory,
3 ... data memory, 4 ... address decoder, 5 ...
Timing control circuit, 6 ... Multiplexer, 7 ... Refresh memory, 8 ... Character generator, 9
...... Video signal generation circuit, 10 ...... CRT, 11 ...... Address bus, 12 ...... Data bus, 13 ...... Control flag, 20 ...... Cursor display circuit, 21 ...... Cursor address register, 22
…… Comparison circuit, 23 …… Cursor generation timing signal, 24
...... AND circuit, 25 ...... Cursor display signal, 26 ...... Cursor pattern generation circuit, 27 ...... Cursor display pattern,
41,42 …… Strobe signal, 51 …… OSC, 52 …… Dot counter, 53 …… Character counter, 54 …… Raster counter, 55 …… Line counter, 56 …… Address generation circuit, 57 …… Dot clock, 58 …… Raster address, 59
…… Interrupt signal. 510 ... display address, 511 ... sync signal, 512 ... sync signal generation circuit, 701 ... character code data, 801 ...
… Character pattern, 901… Video signal.

Claims (2)

[Claims] 1. A refresh memory in which character code data is stored, an address of the refresh memory and a sync signal of a CRT display are output, and a raster address of a character row is counted and output. A timing control circuit that includes a raster counter that outputs a carry as an interrupt signal, and a character generator that stores a character pattern and that reads the character pattern based on the character code data and the raster address read from the refresh memory. A rewritable control flag for storing the display form of the cursor, a cursor address register for storing display position information on the CRT of the cursor, the display address information output from the timing control circuit and the car A comparison circuit that compares the display position information of the sol address register and outputs a cursor generation timing signal when the two match, and a cursor display pattern when the cursor generation timing signal is output and the control flag is in a predetermined state. , A video signal generation circuit for inputting and combining the character pattern and the cursor display pattern and sending them as a video signal to a CRT display, and when an interrupt signal from the timing control circuit is input, a predetermined In the character line, a display control device having a microprocessor for performing an interrupt process for rewriting the contents of the control flag, and a program memory for storing a program for the interrupt process executed by the microprocessor. 2. The control flag is 1 bit, the control flag is rewritten to a first logic state or a second logic state by the interrupt processing, and the cursor display circuit outputs the cursor generation timing signal. The cursor display pattern is generated when the control flag is in the first logic state, and the cursor display pattern is not generated when the control flag is in the second logic state. Display control circuit.