JPH0831485B2 - Method for manufacturing field effect transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a self-aligned manufacturing method of a field effect transistor (hereinafter abbreviated as FET) having a Schottky gate electrode.

(Prior Art) Generally, when a FET having an extremely short gate length is produced by photolithography, a process using a multiple deposition method is used. To give an example of the most basic formation of the gate portion, first, as shown in FIG.
5,000 Å of SiN film 22 is formed and 7000 using photoresist
Open a window of length Å (Fig. 2 (a)). Next, SiN film 2
The n-conductivity type GaAs layer 21 is etched by 800 Å using 2 as a mask to form a recess 23 (FIG. 2B). And recess
23 and the SiN film 22 so as to cover the SiN film 24 by the multiple deposition method.
5000Å is formed (Fig. 2 (c)). After that, the SiN film 24 is etched from above by using an anisotropic etching method such as a RIE method, and an opening having a length of about 1500Å is formed on the recess 23 (FIG. 2 (d)). Next, as the gate electrode, Ti
/ Pt / Au is vapor-deposited by 7000 Å normal to form a metal layer 25, and a photoresist 26 is applied on the metal layer 25 to open a window (FIG. 2 (e)). After that, plating is performed using the photoresist 26 as a mask, a metal portion 27 is formed in the opening portion, and the photoresist 26 is removed (FIG. 2 (f)). Then, the metal portion 27 and the Ti / Pt / Au metal layer 25 are etched from above by using an ion milling method to form a gate electrode 28 (second).
(Figure (g)).

(Problems to be solved by the invention) In the FET formed as described above, a gate electrode having an extremely thin line width of about 1500 Å is formed by normal vapor deposition using a thick SiN film 24 having a thickness of about 6000 Å as a mask. Therefore, as shown in FIG. 3, there is a drawback that the metal layer 25 is cut during vapor deposition.

In addition, the shape of the gate electrode was T-shaped in order to reduce the gate resistance, but the mechanical strength is insufficient because a huge electrode part is placed on the unstable base that is short horizontally and has a high height. However, there is a drawback that the gate electrode falls down without waiting for the final step.

An object of the present invention is to solve the conventional drawbacks and to provide a method for manufacturing an FET having a stable gate electrode that does not break during the formation of the gate electrode and is hard to collapse during the process.

(Means for Solving the Problem) A method for manufacturing a FET of the present invention is a process of forming a first film having a first recess not reaching the conductive layer on a semiconductor conductive layer, and a first recess. Forming a second film in the recessed portion of the second recess and forming a second recess smaller than the first recess, and depositing a third film in multiple layers to cover the first film and the second recess. And the step of etching the third film to form the first opening on the second recess, and etching the second film and the first film using the third film as a mask to make the conductive film A step of forming a second opening on the layer, a step of removing the third film and the second film, a step of etching the conductive layer with the first film as a mask to form a recess, The method includes a step of forming a gate electrode on the recess using the first film as a mask.

(Operation) According to the present invention, since the first film, which serves as a mask for forming the gate electrode, is etched in the vicinity of the second opening with the above-described structure, it is thinner than the thickness normally formed. It is formed. Therefore, for example, in the case of forming the gate electrode by vapor deposition or the like, even if the line width of the gate electrode becomes thin, there is no fear of cutting and the product yield is improved. In addition, the gate electrode formed in this way has a lower portion with a lower height than the conventional one, even if it has a shape such as a T-shaped gate or mushroom gate in which the upper portion of the electrode is significantly larger than the lower portion. Is low and it is difficult to break.

(Example) An example of the present invention will be described with reference to FIG. First
The drawings are cross-sectional views showing a method for manufacturing a gate portion of a FET of the present invention. In the figure, a SiN film 2 of 5000 Å is formed on the n-conductivity type GaAs layer 1, and the SiN film is etched by about 4500 Å using a photoresist 3 having a window opened to a length of 7000 Å as a mask.
At this time, since the etching is stopped before reaching the n-conductivity type GaAs layer 1, the conductive layer 1 is formed on the n-conductivity type GaAs layer 1.
The SiN film 2 having the concave portion 4 which does not reach the height is left (FIG. 1 (a)). Next, after removing the photoresist 3,
A 1500 Å thick SiO ₂ film 5 is formed on the SiN film 2, and the SiN film 2
The upper surface and the recess 4 are covered along the shape. Then, the recesses 7 formed on the recesses 4 are flattened using the resist 6 (FIG. 1 (b)). Next, the RIE method is used to etch the SiO ₂ film 5 from above, and the resist 6 used for planarization is used.
The SiO ₂ film 5 is removed, leaving the covered portion (FIG. 1 (c)). Next, the resist 6 is removed, and the SiN film 8 is multiply deposited (FIG. 1 (d)). Then, the RIE method is used to etch the SiN film 8 from above to form an opening 9 smaller than the recess 7 on the recess 7 (FIG. 1 (e)).
Further, the SiO ₂ film 5 and the SiN film 2 are etched using the opening 9 as a mask to form the opening 10 on the conductive layer 1 (first).
(F)). Then, the SiN film 8 and the SiO ₂ film 5 are removed by wet etching (FIG. 1 (g)). after that,
The conductive layer 1 is etched by wet etching using the SiN film 2 as a mask to form a recess 11. Then, Ti / Pt / Au is vapor-deposited by normal deposition to form a metal layer 12, and is flattened with a resist 13 (FIG. 1 (h)). Finally, RIE is used to etch Ti / Pt / Au to form the gate electrode 14 (FIG. 1 (i)).
According to the FET of this embodiment configured as described above, the SiN film 2 serving as a mask for forming the gate electrode has the opening 1
Since it is thinly formed in the vicinity of 0, cutting is less likely to occur during vapor deposition of the metal layer 12. Also, since the shape of the gate electrode is a T-shaped gate having a large cross-sectional area in the upper part, the gate resistance is small, but the lower part of the electrode is formed lower than in the past, so it is stable and can be broken during the process. It will not fall down.

(Effect of the Invention) According to the present invention, an FET having an extremely short gate length can be formed with a high yield and low resistance by using the multiple deposition method, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a gate portion of an FET in one embodiment of the present invention, FIG. 2 is a process sectional view of a method for manufacturing a gate portion of a conventional FET, and FIG. FIG. 6 is a cross-sectional view of the FET during the process when it is opened. 1 ... n conductivity type GaAs layer, 2,8 ... SiN film, 3 ... photoresist, 4,7 ... recess, 5 ... SiO ₂ film, 6,13 ... resist, 9,10 ... opening Part, 11 ... recess, 12 ... metal layer, 14
...... Gate electrode.

Claims (1)

[Claims] 1. A step of forming, on a semiconductor conductive layer, a first film having a first recess which does not reach the conductive layer, and a second film being formed in a recessed portion of the first recess, Forming a second recess smaller than the first recess, multiply depositing the first film and a third film so as to cover the second recess, and the third film Etching,
A step of forming a first opening on the second recess, and etching the second film and the first film using the third film as a mask to form a second film on the conductive layer. A step of forming an opening, a step of removing the third film and the second film, a step of etching the conductive layer using the first film as a mask to form a recess, and A method of manufacturing a field effect transistor, comprising the step of forming a gate electrode on the recess using the first film as a mask.