JPH08314803A - Disk cache controller - Google Patents

Abstract

PURPOSE: To prevent the hit rate from being lowered by unnecessary prefetch. CONSTITUTION: This device is provided with a DAM controller 110 for controlling a disk device 300, tag memory 120 for storing address tags, data memory 130 for storing block data, register A140 for storing the access address of the latest line, register B150 for storing the access address preceding to the latest one, adder 160 for adding '1' to the access address, register C170 for storing the access address of the line to be prefetched when the compared result shows coincidence with each other, prefetch control means 190 for monitoring the executing state of a cache access command when the compared result shows coincidence with each other and for instructing to perform cache hit judgement after the end of execution, and prefetch requesting means 210 for instructing a cache controller 200 to perform the cache hit judgement and for performing a prefetch request when the hit judgement result shows an error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk cache controller, and more particularly to cache prefetch control.

[0002]

2. Description of the Related Art In prefetch control in a conventional disk cache control device, in the case of a read instruction for a disk, an operation mode indicating whether prefetching is always performed or whether prefetching is performed by software is performed, and further prefetching is performed. The data that has been staged is a line next to the cache miss line at the time of the cache miss or a plurality of consecutive lines from the line next to the cache miss.

[0003]

The conventional disk cache control device often interferes with a regular function when always performing prefetching, and when the data to be prefetched is staging a plurality of consecutive lines. Prefetches a lot of unnecessary data into the valid data entry on the cache,
There are drawbacks such as a decrease in disk cache access performance and a decrease in cache hit rate.

Further, since the operation mode of whether or not to perform prefetch is instructed by the software, there is a problem that the load on the software increases and the efficiency of the software processing becomes inefficient.

[0005]

DISCLOSURE OF THE INVENTION A disk cache control device of the present invention includes an instruction of an access address from software to a disk device, an instruction of an access address requested for prefetch, and an instruction of a cache access command such as a cache hit determination process. A processor for controlling a disk access instruction, a cache hit determination result, and monitoring of a prefetch request, a DMA controller for controlling an access to the disk device according to an instruction from the processor, and a tag memory of a cache memory for storing an address tag. A data memory of a cache memory that stores block data transferred from the disk device, and a first register that stores an access address of the latest line for which the processor has instructed a cache hit determination. Data and a second for storing an access address before one than the latest is the access address stored in said first register to it when storing the access address of the newly line to said first register
Register, an adder for adding "1" to each of the access addresses stored in the first and second registers, an access address stored in the first register and a second register in the adder. Comparing means for comparing whether the access address obtained by adding "1" to the access address of the register is equal to the access address of the register for prefetching obtained by adding "1" to the access address of the first register. A third register that stores the access address when the comparison result by the comparison unit matches, and a cache hit determination for the access address of the line that monitors and prefetches the execution state of the cache access command based on the comparison result by the comparison unit. And a prefetch control means for instructing The cache memory addresses of the tag memory and the data memory are generated from the access address designated by the register No. 3, and the tag memory and the data memory are generated by a cache access command for cache hit determination from the processor or the prefetch control means. Access control to the cache controller, cache hit determination processing, and notification of the cache hit determination result;
The prefetch requesting means for instructing the cache hit determination of the access address of the prefetched line of the register and making a prefetch request to the processor when the hit determination result is missed.

The prefetch control means monitors the execution state of the cache access command of the processor when the comparison result by the comparison means matches.
After the execution is completed, a cache hit determination is instructed for the access address of the line to be prefetched stored in the third register.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a disk cache control device of the present invention.

The disk cache control device of the present invention is
As shown in FIG. 1, a processor 100 for controlling monitoring of a target access address instruction, a cache access command instruction, a disk access instruction, a cache hit determination result, and a prefetch request, a disk device 300 for storing data, A DMA (Direct Memory Access) controller 110 that controls access to the disk device 300, a tag memory 120 that stores an address tag, and a data memory 1 that stores block data.
30 and the access address of the latest line output by the processor 100 instructing the cache hit determination (hereinafter,
"1" is added to each of the register A140 that stores the access address of the line), the register B150 that stores the access address one time before the latest, and the access addresses of the register A140 and the register B150. An adder 160 and a register C1 for storing a prefetch access address which is the result of adding 1 to the access address of the register A140.
70, a comparison unit 180 for comparing the access address from the register A 140 and the access address obtained by adding “1” to the access address of the register B 150, and the cache access command of the processor 100 when the comparison result by the comparison unit 180 matches. The prefetch control means 190 for instructing the cache hit determination for the prefetch access address of the register C160 after the execution of the above, the cache controller 200 for generating the cache memory address and performing the cache memory access control and the cache hit determination processing, Prefetch request means 210 for issuing a prefetch request to the processor 100 when the cache hit determination is instructed and the hit determination result is missed, and the disk device 3 Configured to include a 0.

From these constituent elements, an access address 101 and a cache access command 102 are given.
Disk access command 103, disk interface signal 111, and address tag data 121
"1" is added to the block data 131, the latest (last accessed) access address 141, the access address 151 that is accessed once before the latest (second from the last), and the access address 141. Access address 161, an access address 162 obtained by adding “1” to the access address 151, a prefetch access address, a comparison result 171 of the access address 181 and the access address, and a cache hit determination command 191.
Cache memory address signal 201, cache hit determination result 202, and tag memory control signal 203
Then, a signal including the data memory control signal 204 and the prefetch request instruction 211 is exchanged.

Next, the operation of this embodiment thus constructed will be described. (1) When Access Addresses Consecutive First, when the read command is issued from the software to the access address “n + 1” while the access address “n” is stored in the register A 140, the processor 100 causes the access address 101 to change to the access address 101. "N + 1" is output and the cache access command 102 issues a cache hit determination command.

The cache controller 200 sends the generated memory address to the cache memory address signal 20.
1 and outputs the tag data 12 from the tag memory 120.
1 is read to perform a hit determination, and the result is shown in a cache hit determination result 202. The processor 100 is
If a cache hit occurs, the data at the target access address "n + 1" is read from the data memory 130, and if a cache miss occurs, the data at the target access address "n + 1" is read from the disk device 300.

The cache hit determination processing and disk device 30 for the above access address "n + 1"
When the processor 100 issues a cache hit determination command in parallel with the read process from 0, the register A
140 stores “n + 1” from access address 101, and register B150 stores access address 1
41 to “n” are stored. And register A140
When the data of the register B150 is determined, the adder 160 adds "1" to the updated data of the access address 141 and the access address 151, respectively.

Next, the comparison means 180 compares the data "n + 1" of the access address 141 with the data "n + 1" of the access address 162 output from the adder 160, and the comparison result 181 indicates that the results match. Shown in.
Then, when the comparison result 181 indicates a match, the register C170 outputs the access address 1 output from the adder 160.
The “n + 2” of 61 is stored. Prefetch control means 1
90 indicates that if the comparison result 181 matches, the processor 1
00 waits for the execution of the cache access command 102 to end, and issues the cache hit determination command 191 for the prefetch access address 171 stored in the register C170.

When the cache hit determination command 191 is issued, the register C170 outputs "n + 2" to the prefetch access address 171. The cache controller 200 generates a memory address from the prefetch access address 171, and determines the cache hit of the prefetch access address “n + 2” as in the case of the access address “n + 1”.

Assuming that the cache hit determination result is a cache miss, the prefetch request means 210 issues to the processor 100 because the cache hit determination command 191 is issued and the prefetch access address 171 has a cache miss. The prefetch request instruction 211 is notified. Then, the processor 100 fetches the access address “n + 2” indicated by the prefetch access address 171, and when there is no disk access according to the instruction from the software, the access address “n + 2” of the disk device 300.
Issue a disk command 103 to read to the DMA controller 110.

Further, the processor 100 outputs "n + 2" to the access address 101 and issues a command from the cache access command 102 to the cache controller 200 to instruct staging of block data transferred from the disk device 300. To do.

The cache controller 200 generates the cache memory address 201 and the tag data 121 from the prefetch access address 171, and instructs the memory write with the tag memory control signal 203. further,
When the target block data is transferred to the disk interface 111, the cache controller 200 instructs the memory write from the data memory control signal 204 to transfer the block data 131 to the data memory 130.
It is prefetched by staging to.

The prefetch access address 17
1 assumes that the cache hit determination result of “n + 2” is a cache hit, the prefetch request means 2
No. 10 does not notify the processor 100 of the prefetch request instruction 211 because the prefetch request condition that the cache hit determination command 191 is issued and the prefetch access address 171 has a cache miss is not satisfied.

Therefore, the processor 100 fetches the access address "n + 2" indicated by the prefetch access address 171, and accesses the access address "n + 2".
Issue disk command 103 to read
The cache access command 102 for instructing staging of block data is not issued.

As described above, the prefetch is executed only when the access addresses are consecutive with "n" and "n + 1" and only when the data of the next consecutive access address "n + 2" has a cache miss. (2) When access addresses are not continuous First, when the read address is issued from the software to the access address “m” (where m ≠ n + 1) while the access address “n” is stored in the register A140, the processor 100 performs the cache hit determination processing as in the case where the access address is "n + 1". As a result, if there is a cache hit, the data memory 130 is used; if there is a cache miss, the disk device 30 is used.
The data of the target access address "m" is read from 0.

When the processor 100 issues a cache hit determination command in parallel with the above cache hit determination processing and read processing from the disk 300,
The register A 140 stores “m” from the access address 101, and the register B 150 stores the access address 141.
To "n" are stored. And register A1
When the data of 40 and the data of the register B150 are determined, the adder 160 adds "1" to the data of the updated access address 141 and access address 151, respectively.

The comparison means 180 uses the access address 14
The comparison result 181 shows that the data “m” of 1 and the data “n + 1” of the access address 162 are compared, and the result is inconsistent because m ≠ n + 1. Since the comparison result 181 does not match, the register C170 does not store "m + 1" of the access address 161. Also,
The prefetch control unit 190 does not issue the cache hit determination command 191 for the prefetch access address 171 stored in the register C170.

Therefore, the prefetch request means 210 is
The cache hit determination command 191 is issued, and the prefetch request condition that the prefetch access address 171 has a cache miss is not satisfied, and the processor 100 is not notified of the prefetch request instruction 211.

Further, since the processor 100 has no prefetch request, the prefetch access address 17
It does not issue the disk command 103 for fetching 1 or prefetching or the cache access command 102 for instructing staging of block data.

As described above, when the access addresses are not consecutive with "n" and then "m" (m ≠ n + 1), the prefetch process is not executed.

[0027]

As described above, in the disk cache control device of the present invention, the software does not require any processing for prefetching, so that the processing efficiency of the software is improved. Also, only when the access addresses are consecutive, only the data of the next consecutive access address is prefetched, so unnecessary data is prefetched to the existing valid data entry in the cache. It can reduce the cache hit rate.

Further, there is an effect that the normal function is not hindered by the prefetch process, and the system performance is improved in terms of both software and hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a disk cache control device of the present invention.

[Explanation of symbols]

100 Processor 101, 141, 151, 161, 162 Access Address 102 Cache Access Command 103 Disk Access Command 110 DMA Controller 111 Disk Interface Signal 120 Tag Memory 121 Tag Data 130 Data Memory 131 Block Data 140 Register A 150 Register B 160 Adder 170 Register C 171 Prefetch access address 180 Comparison means 181 Comparison result 190 Prefetch control means 191 Cache hit determination command 200 Cache controller 201 Cache memory address 202 Cache hit determination result 203 Tag memory control signal 204 Data memory control signal 210 Prefetch request means 211 Prefetch request Instruction 3 00 Disk device

Claims (2)

[Claims] 1. A software access address instruction for a disk device, a prefetch request access address instruction, a cache access command instruction such as cache hit determination processing, a disk access instruction, a cache hit determination result, and a prefetch request A processor that controls monitoring, a DMA controller that controls access to the disk device according to an instruction from the processor, a tag memory of a cache memory that stores an address tag, and block data that is transferred from the disk device. A data memory of the cache memory, a first register for storing the access address of the latest line for which the processor has instructed the cache hit determination, and a new line access address for the first register. A second register that stores an access address that is one time before the latest one, which is the access address that has been stored in the first register when storing the address, and the first register and the second register that are stored in the first and second registers. The access address stored in the first register and the access address obtained by adding "1" to the access address of the second register by the adder. And stores the access address of the prefetch line obtained by adding "1" to the access address of the first register by the adder when the comparison result by the comparison means matches. The third register that performs the cache access command execution monitoring and monitoring based on the comparison result by the comparison means. Prefetch control means for instructing a cache hit determination for an access address of a line to be prefetched, and a cache memory address for the tag memory and the data memory are generated from the access address instructed from the processor or the third register. A cache controller that performs access control to the tag memory and the data memory, cache hit determination processing, and notification of the cache hit determination result by a cache access command for cache hit determination from a processor or the prefetch control means, and the prefetch The control means causes the cache controller to perform the third
Disk cache control device, comprising: prefetch requesting means for instructing cache hit determination of an access address of a line to be prefetched of the register and making a prefetch request to the processor when the hit determination result is missed. 2. The prefetch control means monitors the execution state of a cache access command of the processor when the comparison result by the comparison means matches, and prefetches stored in the third register after the execution is completed. The disk cache control device according to claim 1, wherein a cache hit determination is instructed for an access address of a line.