JPH0830571A - Data transfer network - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a data transfer network with a wide range of applications and high performance. A data transfer network has a partial network that connects a plurality of grouped processors to each other in a group, and a plurality of exchange switches that correspond one-to-one to each processor. The destination address of the packet received from the network is
If the switching switch matches the processor to which it is connected, it forwards it to the processor and, in the case of other packets, forwards it to a subnetwork different from the subnetwork that received it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer network for transferring packet type data.

[0002]

2. Description of the Related Art Recent advances in LSI technology have made it possible to realize a high-performance parallel computer system by connecting a large number of high-speed and large-capacity processors for parallel processing. In such a system, it is necessary to transfer a large amount of data between processors, between processors and memories, and for example, a data transfer network for connecting the processors as shown in FIG. 3 is required. For a conventional configuration method of a data transfer network, see, for example, Kurokawa et al., Information Processing Vol. 27, (1986).
), No. 9, Special Feature “Parallel Processing Technology” 3, 1, Coupling Method, pp. 1005 to 1021.

As a data transfer network, one using a crossbar switch and one using a multistage switch are known. In this case, a packet in which a transfer destination address is added to data to be transferred is transmitted to the data transfer network. The packets are sent out, and buses are sequentially generated in the network for the packets.

[0004]

When the data transfer network is composed of crossbar switches, the hardware becomes huge and it is difficult to realize. Therefore, it is practical to use the multistage switch system. In the above packet, the data length is usually several tens of bits or more,
Further, the transfer destination address also requires more than ten bits when using several thousand or more processors. Needless to say, it is desirable to transfer all the bits of the packet in parallel for high-speed transfer of the packet, but if all bits of the packet can be sent in parallel, the number of signal lines and switches will be enormous. , The bit width d of the data transfer path
Must be relatively small (up to about 10 bits or less). Therefore, from a practical point of view, as shown in FIG. 2B, each packet is divided into a plurality of subpackets each having a plurality of bit numbers d, all pits are transferred in parallel in each subpacket, and different subpackets are sequentially transferred. A method of transferring is necessary. In this case, it is necessary to divide not only the data but also the transfer destination address into at least two partial addresses.

Each of the multi-stage switches forming the data transfer network determines the destination of the input packet from the transfer destination address in the packet, performs appropriate switching, and outputs the packet to an appropriate output end. Output. Even when the data and the transfer destination address are divided as described above, each switch can be made to perform this switching by waiting for the arrival of all the partial addresses. Once the switching is performed, the data subpackets sequentially sent after the transfer destination address can be pipelined to the next stage switch. However, if the switching of each switch is performed after waiting for the arrival of all the partial addresses, there is a problem that the switching start time is significantly delayed compared to the case where all the pits of the transfer destination address are transferred in parallel.

An object of the present invention is to provide a data transfer network in which the switching start time of each switch does not need to be delayed even when the transfer destination address is divided into a plurality of partial addresses.

[0007]

Therefore, in the present invention, a partial address required for a switch to determine the next-stage switch to which a packet is to be sent has a plurality of partial addresses each including the partial address supplied to that switch. If it is included in the first of the subpackets, the switch configured the switch to start switching when the first packet arrives. More preferably, if the first subpacket does not contain the partial address required for the switch in the next stage to switch, the previous switch selects the partial address so that the partial address is included in the first subpacket. The sub-packets can be exchanged.

[0008]

According to the present invention, by adopting the above-mentioned configuration, it is possible to reduce the waiting time required for the switches constituting the data transfer network to start switching and realize a high-speed data transfer network.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the embodiments of the present invention, FIG. 5 is a diagram of what the present inventor considered as an example of a data transfer network which uses divided addresses but does not attempt to accelerate switching according to the present invention. Explain.

FIG. 5 shows a data transfer network having a multi-stage switch configuration (hereinafter, also simply referred to as network),
Suppose we have 16 inputs / 16 outputs.

In FIG. 5, S00 to S37 are 2-input / 2-output switches that form a network, and the numbers in brackets [] attached to the upper part of each switch indicate the number.

0'-15 'are input ports of the network, and 0 "-15" are output ports of the network.
The output ports 0 ″ to 15 ″ represent their addresses in binary numbers (0000) to (1111), respectively. FIG. 6 shows an example of the configuration of the switch used in the network of FIG. 5 for dividing and transferring the transfer destination address in the above-mentioned multistage switch. In FIG. 6, 11 and 12 are input ports of the switch and 01 and 02. an output port, E1 is the output port selection circuit, Q _1, Q ₂ output queue, Q _3, Q ₄ output queues, L1, L2, L3, L4 is for storing partial address included in the sub-packet Register of S
Reference numerals 1 and S2 are selectors, MS1 is a memory that stores information / procedures necessary for the operation of the switch, and P1 is a switch controller that controls the operation of the switch.

Here, for the sake of simplicity, it is assumed that the packet given to the network has a transfer destination address of 4 pits and data of 4 pits, and the pit width of the data transfer path is 2 bits, as shown in FIG. The transfer destination address is divided into partial addresses A ₁ and A _2, and is divided into data D ₁ and D ₂ . Also, consider the case where this packet is transferred from the input port 1'to the output port 11 ", as indicated by the thick line in FIG. 5. The address of 11" is (101
1), A ₁ and A ₂ represent bit strings 10 and 11, respectively. The operation of the data transfer network of FIGS. 5 and 6 at this time will be described with reference to FIG. As shown in FIG.

It is assumed that the partial addresses A ₁ and A ₂ and the partial data D ₁ and D ₂ are sequentially input to the input port 12 of the switch S00 having the [00] coordinates. At this time, the switch S00, and stored in the first, second partial address A _1, A _2, respectively register L3, L4, also partial address A _1, A ₂
The partial data D ₁ and D ₂ are sequentially stored in the input queue. The outputs C3 and C4 of the registers L3 and L4 (equal to the partial addresses A ₁ and A ₂ in this case) are given to the switch controller P1 and the switch controller P1.
Indicates that partial addresses A ₁ and A ₂ are registers L1 and L ₂ , respectively.
When set to 2, the control information M1 and M2 of the selectors S1 and S2 in the output port selection circuit E1 are created in response to the contents of the in-switch memory MS1 and the outputs C3 and C4 of the registers L3 and L4. give. More specifically, in this case, the switch controller P1 is
The judgment bit position information J1 indicating that the first bit of the first subpacket is the judgment bit as shown in
From the 4-bit address consisting of the outputs C3 (= A1) and C4 (= A2) given from the above, the above decision bit is extracted. In this case, since this value is 1, control information M for generating a path from the input port 12 to the output port 02 for the selector S2 in E1 based on this value.
Give 2. Thus, the sub-packets are sequentially transmitted from the output port 02 to the switch S of the next stage through the output queue Q3.
14 is sent.

In FIG. 5, output port 0 in switch S00
2 is selected, the above packet is sent to the switch S14.
7, the judgment bit position information J1 that the judgment bit position is the second bit of the first sub-packet is given from the memory MS1 in the switch, as shown in FIG.
A path from the input port 11 of the switch S14 to the output port 01 of the determination pit (0 in this case) is generated, and the packet is sent to the switch S24. Hereinafter, switch S24
Is the decision bit (in this case), the switch S35 is the second pit of the second sub-packet, and the switch S3 is
5 is the second bit (1 in this case) of the second subpacket, and the packet is transferred to the output port 11 ″ of the network by the same process.

A timing chart of the above operation is shown in FIG. In FIG. 8, it is assumed that the above subpackets are sequentially applied to the input port every time T. Further, it is assumed that the switch controller P1, selectors S1, S2, etc. in each switch operate at a sufficiently high speed. As can be seen from FIG. 6, FIG.
In the data transfer network of FIG. 6, each switch has two
Switching is started by waiting for the arrival of one divided address. Therefore, in addition to the transfer time 4T of four subpackets, the waiting time 2T × 4 = 8T for the arrival of the two divided addresses at each switch is added, so that the transfer time required for the network is 12T.

Next, examples of the present invention will be described.

FIG. 9 shows a data transfer network consisting of multi-stage switches according to the present invention. In its configuration, the difference from FIG. 5 is that the switches S00 'to S37' wait for the arrival of all sub-packets including the transfer destination address. Without activating the first sub-packet, switching is performed, the output port connected to the switch in the next stage to which the packet is to be transmitted is determined, and the sub-packet is transmitted, and the switch in the second stage The points S10 'to S17' are configured to switch the divided addresses between the first subpacket and the second subpacket for a plurality of subpackets including the divided transfer destination addresses. In the example of the network described with reference to FIGS. 5 and 6, in the switches S00 to S07 of the first stage and the switches S10 to S17 of the second stage, each switch determines the next stage switch to which the packet is to be sent. The partial address required to do this is the first partial address A1 in the first sub-packet of the packet input to each, but the third stage, fourth stage
In the switches S20 to S37 of the stage, it is the second
It is the second partial address A2 in the subpacket. However, as shown in FIG. 9, the second-stage switches S10 'to S1 are
When the sub-packet string input to 7 'is output, the second partial address A2 to the first sub-packet, partial address A ₁ as the first partial address A ₁ is included in the second sub-packet, A ₂ Are replaced by the switches S10 'to S17' in the second stage, so that the first subpacket includes the partial address required for switching in the switch in the next stage.

FIG. 1 shows the second stage switch S10 'of FIG.
~ S17 'is an example of the configuration, in FIG.
Is different from the output port C1 of the registers L1 and L2 so that one of the partial addresses stored in the registers L1 and L2 or L3 and L4 for the input port 11 or 12 is to be transmitted first. , C2 for selecting the selector S3, and selectors S5 for selecting the outputs C3, C4 of the registers L3, L4, the partial address sequence output from the selector S3 or S5 is selected prior to the partial data stored in the input queue Q1 or Q2. In addition, the switching controller P2 has a selector S4 or S6 for supplying the output port selection circuit E1 to the output port selection circuit E1, and the switching controller P2 is parallel to this packet in synchronization with the arrival of the first subpacket of the packet at the input port 11 or 12. Is started in response to the packet start signal PSTR1 or PSTR2 given to the The end of the packet is terminated in response to the packet end signal PEND1 or PEND2 which is given in synchronization with the arrival at the input port 11 or 12, and the judgment bit position information J2 given from the memory MS2 is always the head. , Which points to any bit of the partial address in the subpacket.

The switches S00'-S0 of the first stage are also included.
7'and switches S20 'to S37' of the third and fourth stages.
As shown in FIG. 2, registers L1, L3 for storing the sub pads and selectors S3 to S6 are omitted from FIG. That is, these switches are mainly used in the second stage switch S in that subpackets are not replaced.
Although different from 10 'to S17', a packet start signal P
It is the same in that it responds to STR1, PSTR2, and packet end signal PEND2. As in the case of FIG.
To explain the operation of the above, the bit width of the data transfer path is 2 bits, and the transfer destination address is two partial addresses A ₁ and A _2.
The data consists of two partial data D ₁ and D ₂ , each of which is contained in a subpacket having a length of 2 bits. Consider the case where data is transferred from the input port 1'to the output port 11 'as shown by the thick line in FIG. The operation of the data transfer network of FIG. 9 at this time will be described with reference to FIG. As shown in FIG.

It is assumed that the partial addresses A ₁ and A ₂ and the partial data D ₁ and D ₂ similar to those in FIGS. 5 to 7 are sequentially input to the input port 12 of the switch S00 ′ having the coordinate [00]. Switches S00 'and S in FIG.
The operation of 24 'and S53 is performed by the switch S0 in FIG.
The operation is almost the same as 0, S24, and S35, except that each switch starts the operation when the first partial address arrives. That is, in the case of FIG. 9, since the determination bit position for determining the destination switch of the packet from each switch is within the partial address of the first subpacket as indicated by * in FIG. The difference is that the destination is decided and the transmission is started without waiting for the arrival of.

Next, an example of the operation of the switch S14 'in FIG. 9 will be described with reference to the time chart of FIG.
From 'switch S00 to' switch S14, partial address A _1, A _2, partial data D _1, D _2, input port 11
Will be sent in sequence. At this time, the packet start signal PSRT1 is given to the switch controller P2 in synchronization with the arrival of the head partial address and in parallel with the packet transfer. The switch controller P2 is a switch S00 '.
Starts the control operation as follows. The switch S14 ', the first partial address A ₁ at the first timing is stored in the register L2, and moves the first partial address AA ₁ in the register L1 at a second timing that follows,
And the second partial address A ₂ is stored in the register L2.
In addition, the partial data D at the third and fourth timings, respectively.
₁ and D ₂ are sequentially stored in the input queue Q ₁ . Here, the content C2 of the register L2 is given to the switch controller P2. In this case, when the first partial address A ₁ reaches the register L2, this partial address A ₁ is given to the switch controller P2 as C1. The switch controller P2 responds to the bit at the position indicated by the judgment bit position information J2 given from the memory MS2 among the outputs C2, and selects the selector S in the output port selection circuit E1.
The control information M1 and M2 for 1 and S2 are created and given to them to generate a bus from the input port 11 to the output port 01. Further, the switch controller P2 has the first partial address A ₁ stored in the register L1 and the register L
Of the second partial address A ₁ stored in 2, the above third
In the timing, the A _2, also supplies a control signal M3, such as selecting the A ₂ in the fourth timing selector S3, thereby interchanging the order of the partial address A ₁ and A _2. Further, the switch controller P2 is the third controller.
, The partial address A ₂ output from the selector S3 is selected, the partial address A ₁ output from the selector S3 is selected at the fourth timing, and the input queue Q1 is selected at the fifth and sixth timings. The partial data D ₁ and D ₂ stored in the selector are selected, and the control signal M4 to be supplied to the output port selection circuit E1 is supplied to the selector S4. The output of the selection circuit E1 is given to the queue Q3,
At the third, fourth, fifth, and sixth timings, A ₁ , A ₂ , D ₁ , and D ₂ are input / stored in the output queue Q3, respectively. As a result, the transfer destination address created by exchanging the partial addresses A ₁ and A ₂ as described above can be selectively applied to the output port selection circuit E1 prior to the data stored in the input queue Q1.

FIG. 11 shows the switches S00 'and S2 of FIG.
The waiting time for the address arrival in 4'and S35 'is half the time T in the case of FIG. Therefore, it can be seen that the transfer time required for the network is 9T, which is 25% faster than 12T in the case of FIG. 5 (FIG. 8).

The switch controller P2 can also perform the same processing on the packet given from the input port 12, and like the case of FIG. 6, determines the priority of the input data of the input ports 11 and 12. be able to. The switch controller P2 has an output port 01,
02, the output control signal OC1 is output from the switch controller P2 to the output queue Q when the output enable signal OE1 and OE2 of 02 is applied.
3, the partial addresses A ₁ , A ₂ , and the partial data D ₁ , D ₂ are sequentially sent from the output queue Q3 to the output port 01. Similarly, when the signal OE2 is in the output permission state, the output control signal OC2 changes to the switch controller P2.
To the output queue Q4. Output queue Q3, Q
When 4 is filled with data and new data cannot be stored, status signals SQ1 and SQ2 respectively connected to the switch controller P2 are given to the switch controller P2. Although the input permission signals IA1 and IA2 of the normal input terminals 11 and 12 are output from there, the input permission signals IA1 and IA2 are set to the input prohibited state by the status signals SQ1 and SQ2, and a new packet is input. Prohibit that. In the case of the configuration of FIG. 9, the input permission signal IA1 (or IA
2) to the switch at the front stage, and output permission signal OE1 (OE
By inputting as 2), it is possible to prevent packets from being lost due to overflow of the queue in the middle of the transfer route. In FIG. 1, registers L1, L2, output queues Q1, Q
The control of the data set timing to 3 is performed by the signals T11 and T.
12, T13, T14, and registers L3, L
4. Control of data set timing to the output queues Q2 and Q4 is performed by signals T21, T22, T23 and T24, and these signals are given from the switch controller P2. FIG. 13 shows the switch controller P2 of FIG.
2 is a schematic configuration diagram of FIG. In the figure, timing supply circuits 10A and 10B indicate packet star start signals PST.
Address decoder 16A in response to R1 or PSTR2
Or 16B is driven and the timing clock is given to the counter 12A or 12B, and the end of the packet is given in synchronization with the timing given to the input port 11 or 12 (FIG. 1). The counter 12A or 12B and the timing decoder 14A or 14B are reset in response to the packet end signal PEND1. In the address decoder 16A or 16B, the register L2 cuts out the pit indicated by the judgment pit position information J2 given from the memory MS2 among the outputs C2 and C4 of the L4, and sends the inputted packet to either of the output ports 01 and 02. This signal is sent to the conflict control 22. The timing decoders 14A and 14B are counters 12A and 1
In response to the count value of 2B, the control signal T11
.About.T13, M3, M4 and output queue control 18A or 18B and selector control 24 'are activated. The conflict control 22 checks whether there is a conflict between the outputs of the address data 16A and 16B, and if there is no conflict, sends it to the selector control 24. Therefore, selector control signals M1 and M2 are generated. In the conflict control, if there is a conflict between the two outputs, only one of them is sent to the selector control 24 in response. At the same time, an input control 20A or 20B signal provided corresponding to the other of the address decoders 16A and 16B is sent.
The input / control 20A, 20B sends the signal IA1 or IA2 for prohibiting the transmission of a new packet to the switch of the generation stage and the preceding stage.

The output queue control 18A, 18B generates a signal T14, OC for controlling the output queue Q3 or Q4, and also a packet start signal PSTR1 or PS.
T2, packet end signal PEND1 or PEND2,
It is generated in synchronization with the start of packet transmission and the end of packet transmission by the output queue Q3 or Q4, and these signals are sent to the switch in the next stage.

FIG. 12 shows the circuit of FIG. 1 using the circuit of FIGS.
The time chart when performing timing control different from 1 is shown. In this case, as in the case of FIG.
The partial address A ₁ , A ₂ , partial data D ₁ , D ₂ are sequentially sent to the input port 11 from the switch S00 'to the switch S14' of the circuit. Stores the first partial address A ₁ at the first timing in the switch S14 'in the register L2, then determines an output port to be sent the data. At the subsequent second timing, the first partial address is moved to the register L1 and the second partial address A ₂ is sent through the register L2 to the output queue Q3. FIG.
In the second embodiment, the partial address A ₁ that needs to be processed (interpreted) to determine the packet transfer destination in S14 ′ is included in the first subpacket, and the partial address A ₂ included in the second subpacket. Does not require processing (interpretation) in S14 '. Therefore, it is possible to pass through the register at the second timing as described above. At this time, the switch controller P2, selectors S1, S2, S3
The control of S4 can be realized by a method similar to the case of FIG.
Next, the partial data D ₁ and D ₂ are sequentially stored in the input queue Q1 at the third and fourth timings, respectively, and at the third timing, A ₁ , at the fourth timing, D ₁ , and at the fifth timing. Each D ₂ is sent to the output queue Q3. As a result, in FIG. 12, the waiting time for 1T in S14 ′ required in FIG. 11 is shortened. In FIG. 12, FIG.
The transfer time, which was 9T required, can be reduced to 8T, and the bi-line operation without waiting time can be realized.

In the above description, for the sake of simplicity, the partial addresses A ₁ and A ₂ and the partial data D ₁ and D ₂ are temporarily stored in the output queue Q3, but from the beginning the output enable signal OE1. Is in the output enable state, output queue Q
Bypass or through 3 directly, the third, fourth,
It is obvious that the configuration may be such that the data is sent to the output port 01 at the fifth and sixth timings. Further, output queues Q3 and Q4 for storing partial address strings and partial data strings
Obviously, it may be provided after the input port instead of before the output port, or both. The input queues Q1 and Q2 and the output queues Q3 and Q4
May be a FIFO memory, but may be a RAM or a register file. In FIG. 2, registers L3 and L4,
Although the registers L1 and L2 are connected in series, the first sub-packet may be stored in the register L1 (or L3) and the second sub-packet may be stored in the register L2 (or L4) via the selector. . Also in this case,
Registers L1 to L4 are RAMs (there is a sufficient data word length)
May be configured using a part of the register file.

As is clear from the above description, the effect of the present invention becomes larger as the network is large-scale and the number of switch stages increases. In the above description, the data width of the data transfer path is 2 bits, the transfer destination address is 4 bits, and the data is 4 bits. However, if the number of bits of the transfer destination address is larger than the data width of the data transfer path, it is arbitrary. It is clear that the present invention is effective in the case of the value of. Further, although the switch having two inputs and two outputs has been described, it is clear that the present invention is effective regardless of the switch configuration and the network configuration.

FIG. 14 is a diagram showing another embodiment of the present invention. PE11 to PE44 are processors, and the data transfer networks connecting the processors are switches EX11 to EX44 and X partial networks NX1 to N.
It consists of X4 and Y sub-networks. The packets transferred in the data transfer network are the same as those shown in FIG. However, the transfer destination partial addresses A ₁ , A ₂
Is the subscript i in the X direction and the subscript j in the Y direction of the processor PE _11.
Equal to. That is, the address of the processor PEij is represented by a set of X address i and Y address j.

In FIG. 14, processors PE having the same i
ij (j = 1 to 4, i = 1, 2, 3, 4) and a processor PEij (i = 1 to 4, j = 1, 2,
3, 4) belong to one cluster.

X partial network NXi (i = 1, 2,
3 and 4) mutually connect the processors PEij (j = 1 to 4) of the cluster having i in common (referred to as X cluster), and the Y partial network NYj (j = 1, 2, 3, 4).
Connects processors PEij (i = 1 to 4) belonging to a cluster having j in common (called a Y cluster) to each other. These partial networks NXi and NYj are networks composed of multistage switches as shown in FIG. As will be described later, it is not necessary to replace the partial addresses in each of the multistage switches used therein, and therefore, the switches shown in FIG. 2 can be used. The switch EXij (i = 1 to 4, i = 1 to 4) is a switch of 3 input / 3 output ports that connects the X partial network NXi and the Y partial network NYj and the processor PEij to each other.

For example, in the partial network NX1, the processors PE11, PE12, PE13, PE14 are respectively switches EX11, EX12, EX13, EX.
The processor PE1 is connected to NY1 via the processor PE1.
1, PE12, PE31, and PE41 are connected via reswitches EX11, EX21, EX31, and EX41, respectively.

As shown in FIG. 15, the switch EXij has an input port IPij with the processor PEij, an output port OPij, and an input port IX with the partial network NXi.
ij, an output port OXij, an input port IYij for the partial network NYj, and an output port OYij.

Since the switch EXij needs to exchange the partial addresses A ₁ and A ₂ as described later, for example, the switch shown in FIG. 16 in which the switch of FIG. 1 is changed to 3 inputs / 3 outputs is used. To use. The parts and signals in FIG. 16 are similar to the parts and signals in FIG. 1 that have the same alphabetic characters or symbols that begin with an English character string.

In this embodiment, the data transfer between the processor PEij and the processor PEk1 (1≤i, j, k, 1≤4) is PEij → EXi, as will be described later.
j → NXi → EXi1 → NY1 → EXk1 → PEk1 or PEij → EXij → NYi → EXkj → NXk
→ EXk1 → PEk1 can be performed via either of two routes.

The operation of the network shown in FIG. 14 will be described below with reference to FIG.
This will be described with reference to FIGS.

Switch EX from certain processor PEij
ij is the processor PEk1 via the input port IPij
It is assumed that the packet addressed to is received (step 130).

The first and second partial addresses A ₁ and A _{2 at} the head of this packet are the destination processor PEk1 in this case.
Is equal to the X-direction address k and the Y-direction address l.

(1) Now, the switch EXij is shown in FIG.
As shown in, the packet has the first condition A ₁ (= k).
= Determine whether or not it satisfies its own X-direction address (i) (step 132), and if this condition is satisfied (that is, if the destination processor PEk1 and the source processor PEij belong to the same X class), It is judged (step 134) whether this packet satisfies the second condition A ₂ = own X-direction address (j) (step 134), and if this condition is also satisfied (that is, the source processor PEij and the destination processor). If it is the same as PEk1, switch EXij sends this packet to processor PEij via its output port OPij (sweep 163). On the other hand, step 1
As a result of the determination of the second condition in 34, the second condition was not satisfied. If (that is, the destination processor PE
If k1 is another processor belonging to the same X cluster as the processor PEij), the partial addresses A ₁ and A ₂ are replaced (step 138), and this packet is sent to the X partial network NXi via the output end OXij (step 138). Step 140). By this address replacement, the Y-direction address l of the destination processor PEk1 is located at the beginning of this packet. As a result, the X partial network NXi
Each switch of (= NXk) can start switching as soon as the first subpacket of this packet arrives in response to the partial address A ₂ at the beginning of the packet. The partial network NXk sends this packet to the switch EXk.
1 through its input port IXk1. When this switch EXk1 receives this packet (step), as shown in FIG. 18, the partial address (in this case, A ₂ (=
1)) is equal to the Y-direction address l of the switch EXk1 (= EXi1) (step 164).
In this case, the switch EXk1 sends this packet to the processor PEk1 via its output port OPk1 since the condition that they are equal is satisfied (step 16).
5).

In this way, packet transmission is performed between the processors in the same X cluster.

(2) In step 132 of FIG. 17, if the result of the determination of the first condition is that the first condition is not satisfied (that is, the destination processor PEk1 and the source processor PEij do not belong to the same X cluster). In the case), it is determined whether or not the second condition A ₂ (= 1) = own Y-direction address (j) (step 142). As a result of this determination, if this condition is satisfied (that is, if the processors PEk1 and PEij do not belong to the same X cluster but belong to the same Y cluster, the switch EXij sends the packet to the Y partial network NYj and outputs it to the output port It is sent out via OYij (step 144).

The partial network NYj sends this pocket to the switch (Ekj) having an X address equal to the partial address A ₁ (= k) at the beginning of this packet.
The switch (Ekj) receives this packet from the input end IYkj as shown in FIG. 19 (step 1
52), it is determined whether or not this packet is equal to the second partial address A ₂ = own Y-direction address (step 15).
4). In this case, this condition is satisfied, so switch E
kj sends the packet to the processor (PEkj) connected to it through output port OPkj. In this way, packet transfer between two processors belonging to the same Y cluster can be performed.

(3) If the result of the determination in step 142 of FIG. 17 is negative, that is, the destination processor PEk1 and the source processor PEij do not belong to the same X cluster, or belong to the same Y cluster. If not, there are two paths connecting these two processors. That is, this is a route for first transferring a packet to the first route X partial network, and specifically, PEij
→ EXij → NXi → EXi1 → NY1 → EXk1 → P
It is Ek1. In this route, the Y address is determined first, so this route will be referred to as the Y priority route hereinafter. The second route is a route for transferring the bucket to the Y partial network first, and specifically, PEij → EXij → NYj.
→ EXkj → NXk → EXk1 → PEk1. In this route, the X address is determined first, and henceforth this is referred to as the priority route.

At step 146, one of these two routes is selected.

This selection is made in advance for each switch EXij.
It may be set for each. In this case, step 146
Is omitted. Further, the amount (load) of packets passing through each partial network of the network may be measured, and the above selection may be dynamically changed so that the load becomes as uniform as possible.

When the X priority route is selected in step 146, the stitch EXij outputs the packet to the output port OYi.
It is sent to the partial network NYj via j (step 144). Upon receiving this packet, this partial network NYj has a switch Ekj having an X address equal to the partial address A ₁ (= k) at the beginning of the packet.
Is transmitted through the input port IYkj. As shown in FIG. 19, when this switch receives this (step 152), it receives the second partial address A ₂ (=
1) = It is determined whether or not the own Y address (= j) is satisfied (step 154). In this case, since it is assumed that j ≠ l, the result of this determination is negative. This switch Ekj puts in the partial addresses A ₁ and A ₂ of this packet or moves the partial address A ₂ to the beginning (step 15).
8). After that, this packet is transmitted to the X partial network NX.
to k through the output port OXjk.

Each switch in this partial network NXk can respond to the partial address A _{2 at} the beginning of this packet as soon as it arrives. The sub-network then sends this packet to the switch Ek1 with a Y-direction address equal to the sub-address A ₂ (= 1).

This switch Ek1 has an input port IXk.
Receive this packet via 1 (step 162,
In FIG. 18, it is determined whether the first partial address A _{1 of} this packet is equal to its own X-direction address (= k). In this case, this determination result is affirmative, so the switch Ek1 sends this packet to the processor PEk1. Thus, packet transfer between two processors that do not belong to the same cluster is performed by the X priority route.

When the Y priority route is selected in step 146 (FIG. 17), the switch EXij replaces the partial addresses A ₁ and A ₂ in the packet and moves A ₂ to the beginning (step 138). Then, this packet is sent to the X partial network NXi (step 140). This partial network NXi sends this packet to the switch EXi1 having a Y address equal to this partial address A ₁ (= 1).

As shown in FIG. 18, this switch EXil receives A ₁ after receiving this bucket (step 162).
(= K) = determines whether it is equal to its own X-direction address (= i) (step 164). In this case, the result of this judgment is negative, and this switch uses partial addresses A ₂ , A ₁
, And move A ₁ to the beginning of the packet (step 1
68), the packet is again transmitted to the Y partial network NY1.
(Step 170). Due to this partial network NY1, this packet forwards this packet to the switch Ekl with an X-direction address equal to the first partial address A ₁ (= k) of this packet. With this switch Ekl, steps 152, 154 and 156 of FIG.
Processor PE connected to this packet by
send to kl. Thus, 2 which do not belong to the same cluster
Packets are routed between the two processors by the Y priority route.

The advantage of the network as in this embodiment is that
The smaller the size of each partial network, the easier the implementation. Since the processors are clustered as described above, the partial network NY
In j, the first partial address A _{1 of} the transfer destination addresses
Only the second partial address A ₂ is required in NXi. In this embodiment, A ₁ , A ₂ are included in the switch EXij.
Each sub-network NX has a replacement means
Since the required partial address in i, NXj is always present in the first subpacket, each switch in the partial network does not have to wait for all the partial addresses to arrive, and high-speed data transfer is possible.

During operation of the network of FIG. 14, the speed can be further increased by changing as follows.

That is, in FIG. 18, determination 16 is performed when each switch (EXmn) receives a packet from the X partial network NXm, where m and n are integers.
4 must wait for the arrival of the partial address A ₁ from the network NXm. However, as already mentioned, in the network NXn the packet has the partial address A ₂ at its head. Therefore, the above determination 164
Is not possible until the second subpacket from the subnetwork NXm arrives at the switch EXmn. The same problem occurs for decision 154 in FIG.
These problems are improved by changing the sub-networks NXm, NYn, etc. as follows.

That is, the partial network NXm or N
Yn and the like are respectively applied to step 180A in FIGS.
As indicated by 180B, when the packets are output to a switch EXmn from each of them, a switch in the partial network closest to the switch is configured to replace the partial addresses A ₁ and A ₂ in the packet. This can be realized similarly to the method described in FIG.

These results X from the partial network NX
The operation of the switch EXnm received in the packet is
As shown in FIG. In the figure, the same reference numerals as those in FIG. 18 indicate the same processes. As can be seen from this figure, in this improved operation, the switch EXmn performs the determination processing 144 for the partial address A ₁ as in the case of FIG. Since the partial address A ₁ is included at the head of the packet to be sent, the determination processing 144 can be started as soon as the partial address A ₁ arrives. Also,
As a result of the addresses being exchanged at the time of packet output by the X partial network NXm, the addresses are not required to be exchanged in FIG. 18 and not required in FIG. 22 Similarly, the operation of the switch EXm when receiving a packet from the Y partial network NYm is become that way. In the figure, the same reference numerals in FIG. 19 denote the same. Also in this case, the comparison between FIG. 22 and FIG. 18 still applies.

In the above description, A ₁ and A ₂ are 2 bits,
Although d is 2 bits, the effect of the present invention does not change even if the number of bits is arbitrary. Also, the transfer destination address is divided into three, a partial network in the Z direction is provided in addition to the X and Y directions, and EXij has 4 input ports / 4 output ports like EXijk. It is also clear that the number of divisions of can be increased.

FIG. 24 shows an embodiment of such a data transfer network. In the figure, NX ₁₁ , NX ₁₂ , NX
₁₄ , ₁₄ , N _{44 and the} like represent the partial transfer network 7.1 in the X direction, and NY ₁₁ , NY ₁₂ , NY ₁₄ , NY _{44 and the} like represent the partial transfer network in the Y direction, which are the same as in FIG. 11A. In this embodiment, the partial network N in the Z direction
Z ₁₁ , NZ ₂₁ , NZ ₄₁ , NZ _14, ... NZ _{44 and the} like are provided.

Switches EX ₁₁₁ , E ₁₄₁ , EX ₄₁₁ , EX _444, etc. and processors PE ₁₁₁ , PE ₁₄₁ , PE ₄₁₁ , PE ₄₄₄ are provided at the intersections of these three partial networks.

In the figure, for simplification, each sub-network is represented by a straight line, and the switches and processors are only partially represented, and the switches and processors are only partially represented.

[0058] Switch EX ₁₁₁ is connected at the input and output ports for each of the X-direction partial network NX _11, Y-direction partial network NY _11, Z-direction partial network NZ ₁₁ and processor PEl _11.

The same applies to the other processors.

When a packet is transferred from one processor to another processor, the transfer destination address in the packet is A
_{It is} composed of ₁ , A ₂ , and A ₃ . When the processor of the packet transmission destination is Pijk, each is equal to the respective coordinates i, j, k in the X, Y, Z directions.

Now, for example, processors PE ₁₁₂ to PE
_When sending a packet to _444, there are several packet transfer routes. For example, PE ₁₁₁ → EX ₁₁₁ → NX ₁₂ →
EX ₄₁₁ → NY ₁₄ → EX ₄₄₁ → NZ ₄₄ → EX ₄₄₄ → PE ₄₄₄
Is one of them.

The operation for transferring a packet according to this route is as follows.

When the switch EX ₁₁₁ sends this packet to the partial network NX ₁₁ , the switch EX ₁₁₁ transfers the partial addresses A ₁ , A ₂ and A ₃ without replacing them, as in the case of FIG. Partial network NX
₁₁ sends this packet to the switch EX ₄₁₁ having the X coordinate equal to the address A ₁ . The switch EX ₄₁₁ determines that the partial address A ₃ , A ₂ , A ₁ in this packet A ₂ is different from its own Y coordinate, and therefore the partial network NY in the Y direction NY is used.
Send to ₁₄ . At that time, the address in the packet is A ₂ ,
Replace A ₃ and A ₁ in that order. This network sends a packet to a switch EX ₄₄₁ with a Y coordinate equal to address A _2.
Send to.

The switch EX ₄₄₁ sends this packet to the Z direction partial network NZ ₄₄ because the partial address A ₂ therein is different from its own Z coordinate. At that time, the addresses are replaced in the order of A ₃ , A ₁ , and A ₂ . The network sends this packet to EX ₄₄ with the Z coordinate equal to address A ₂ . Switch EX ₄₄₄ which received this
_Sends this packet to the processor PE ₄₄₄ .

As described above, in the present embodiment, when there are more processors than in the case of FIG. 14, data transfer between them can be performed. Moreover, since the switches EX perform the address replacement as described above, the partial network can switch in response to the partial address at the head of the arrived packet.

As shown in FIG. 22 and FIG. 23, instead of replacing the addresses in EX ₄₁₁ and EX ₄₄₁ when switching, the partial networks NX ₁₁ , NY ₁₁ and NZ ₄₄ replace 3 addresses when outputting a packet. The faster operation can be processed.

FIG. 25 shows an embodiment of the present invention. PE is a processor, and EX is a switch. As shown in the drawing, one switch similar to the switch EX100 is provided for each of a plurality of processors similar to the processor PE100, and each switch EX has four switches. An input port and an output port are connected to nearby switches to form a mesh-shaped data transfer network. Also, FIG.
As shown in FIG. 6, the switch EX100 is a processor PE.
Input / output boat IP100 / OP10 between 100
0, 4 Input / output ports to and from neighboring switches, I
N100 / ON100, IW100 / OW100, IS
It has 100 / OS100 and IE100 / OE100. Also in this embodiment, as described above, the packet transferred between the processors is transmitted and received as a packet including an example of subpackets divided by the bit width d of the data transfer path as shown in FIG. This embodiment differs from the other embodiments in that the transfer destination address in the packet is d.
It is divided into two so that the number of bits is -1 bit or less, and the upper part of the divided transfer destination address is used as a global address A _G , and the lower part is used as a local address A _L , and A _G , A _L Is stored in each of the above subpackets, and the head subpacket is provided with a flag bit L indicating whether the divided address stored therein is A _G or A _L. For simplicity, d = 4 and A _G and A _L each have 3 bits. As shown in FIG. 27, 64 processors represented by 6 bits in total of A _G and A _L are connected by a switch as shown in FIG. 26, and the processors have the same global address as shown in FIG. It is clustered by 8 each. In the present embodiment, each switch has a configuration of 5 input ports / output ports, for example, a switch similar to that shown in FIGS. 9 and 16.
The configuration shown in FIG. 30 can be used. The operation of each unit in FIG. 30 and the meaning of the reference numerals are the same as those of each unit having a reference numeral starting with the same alphabetic character (column) in FIG. The configuration of FIG. 30 differs from the configuration of FIG. 9 in that the divided address storage register L
That is, the setting circuit X21 for the flag bit L is provided between 12, L22 and the selector S31. X21 is a set signal XC21 from the switch controller P21.
Sets the flag bit L. The operation of the switch will be described below. Note that in FIG. 20, R22 to R25
The part indicated by is the same structure as the part indicated by R21 and is omitted for simplicity. In each processor, when transmitting data for the first time, A _G is put in the head subpacket and the L bit is set to 0. The processing procedure in each switch is shown in FIG. In the present embodiment, since the L bit is provided, it is not necessary for each switch to refer to the local address A _L while L = 0, and therefore, all the addresses including the transfer destination address divided as described above are included. The next-stage switch to which the packet should be sent can be determined without waiting for the arrival of the sub-packet. When packets are transferred one after another and enter a switch in the cluster having the same global address as the target processor, the switch waits for the arrival of a sub-packet including the local address A _L, and then, as in the case of FIG. _{The L} and A _G are exchanged so that the local address is included in the first subpacket, and L = 1 is sent to the next stage. Subsequent switches can determine the next-stage switch to which the packet should be sent, without waiting for the arrival of the second subpacket including the global address.

[0068] Each processor in FIG. 27, when having an address, such as shown, A ₀ = 000, from A _L = 110 processor NS _{of, A 0 = 110, A L} = 110 processor NR of
Consider the case of sending a bucket to. Here, each switch stores the local address of the adjacent processor and the global address of the adjacent cluster together with its own address. While L = 0, the global address A ₀ and its own global address are compared. If they are different, the transfer direction and the output port are determined by comparing A ₀ with the global address of the adjacent cluster. The simplest way is to send in the direction in which the difference in global addresses is the smallest. Following this algorithm, the packet is
, And the position indicated by NX (A ₀ = 11
0, A _L = 000) switch. Here, in the NX switch, A _L and A ₀ are interchanged as in the case of the switch of FIG. 9, and L = 1 is sent to the next stage. After that, the local address is compared with the local address of the adjacent processor, and the transfer direction and the output port can be determined by the same algorithm as above. In this embodiment, it is only the NX switch that needs to wait for the arrival of two subpackets including A ₀ and A _L among the switches at each stage, and the other switches wait for the arrival of the transfer destination address. The time is less than half of the time when the present invention is not used, and the effect is very large especially when the number of processors is large.

In the above description, A ₀ and A _L are each 3 bits, but the effect of the present invention does not change even if the number of bits is arbitrary.

Although the transfer destination address is divided into two,
Even if the number of divisions is increased and the number of bits L is set to a plurality of bits accordingly, the effect of the present invention remains unchanged.
Further, although the switch of the data transfer network is connected to four neighbors, the effect of the present invention does not change even if the switch is connected to any number of sides.

In the above description of the embodiments, the destination of the data packet is supposed to be indicated by the transfer destination address included in the first two or more subpackets, but in order to indicate the transfer destination address equivalent to this. It is obvious that the tag information of may be used. As such tag information, for example, information obtained by taking the Exclusive Or of the address of the calling processor and the transfer destination address can be used.

[0072]

As described above, according to the present invention, it is not necessary to wait for the arrival of all of the plurality of subpackets including the transfer destination address at each stage of the plurality of switches configured in multiple stages of the data transfer network. High-speed data transfer is possible.

[Brief description of drawings]

FIG. 1 is a second stage switch (S14 ′ etc.) of the apparatus of FIG.
FIG.

FIG. 2 is a schematic configuration diagram of switches (S00 ′, S24 ′ or S35 ′) of the first, third or fourth stages of the apparatus of FIG.

FIG. 3 is a diagram showing blocks of a parallel computer system to which a data transfer network according to the present invention is applied.

FIG. 4 is a diagram showing a packet structure of the present invention.

FIG. 5 is a schematic configuration diagram of a low-speed data transfer network for comparison with the present invention.

6 is a schematic configuration diagram of a switch (Sij) of the network of FIG.

FIG. 7 is a diagram for explaining the operation of switches in the network of FIG.

8 is a time chart of the operation of the network of FIG.

FIG. 9 is a schematic configuration diagram of a data transfer network according to the present invention.

FIG. 10 is a diagram for explaining the operation of switches of the apparatus of FIG.

11 is a time chart of an example of the operation of the apparatus of FIG.

12 is a time chart of another example of the operation of the apparatus in FIG.

13 is a schematic configuration diagram of a switch controller (P2) used in the switch of FIG.

FIG. 14 shows another embodiment of a data transfer network according to the present invention using a partial network.

FIG. 15 shows another embodiment of the data transfer network according to the present invention using a partial network.

FIG. 16 is a switch (E) used in the apparatus of FIGS.
Xij) schematic configuration diagram.

FIG. 17 is a flowchart of operations performed when the switch (EXij) in FIG. 16 receives a packet from the processor.

18 is a switch (EXij) used in the apparatus of FIG.
Is a flowchart of the operation when the packet is received from the partial network NY.

19 is a switch (EXij) used in the apparatus of FIG.
Is a flowchart of the operation when the packet is received from the partial network NX.

FIG. 20 is an X-direction partial network (N
Xj) improved operation flow chart.

FIG. 21 shows a partial network (N direction) of the device of FIG.
Yi) improved operation flow chart.

22 is a flowchart of the improved operation when the switch (EXij) of the apparatus of FIG. 16 receives a packet from the Y direction partial network (NYi).

23 is a flowchart of the improved operation when the switch (EXij) of the apparatus of FIG. 16 receives a packet from the X-direction partial network (NXj).

FIG. 24 is an example of a three-dimensional data transfer network using partial networks.

FIG. 25 is another embodiment of the present invention using a lattice-coupled network.

26 is a diagram showing input / output ports of the switch (EX100) of FIG.

27 is a diagram showing a data transfer route in the apparatus of FIG. 25.

FIG. 28 is a diagram showing a packet used in the device of FIG. 25.

29 is a flowchart of the operation of the switch (EX) of the apparatus shown in FIG.

30 is a schematic configuration diagram of a switch (EX) of the apparatus of FIG. 25.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Hamanaka 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeo Nagashima 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory

Claims (8)

[Claims] In a data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors includes an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 2 or more) composed of a plurality of bits. , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. A data transfer network, which forwards the packet to the processor if it matches the processor, and forwards it to a partial network different from the partial network which received the packet in the case of other packets. 2. In a data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors includes an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 2 or more) composed of a plurality of bits. , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to each other, Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches the processor, it forwards it to the processor, and if it is another packet, it forwards it to a subnetwork different from the subnetwork that received it, and the subnetwork is a predetermined one of the subaddresses. Or a transfer destination determining means for decoding a plurality of bits to determine a transfer destination of the packet, and the exchange switch has a transfer order changing means for changing a transfer order of the plurality of received partial addresses. And the above packet is forwarded from one subnetwork to another subnetwork. The Rutoki, data transfer network, characterized in that said transfer destination determining means for transferring partial addresses required to determine the transfer destination, the first among all the partial address received. 3. A data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors comprises an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 2 or more) composed of a plurality of bits. , A set of partial addresses of the D set is grouped by the same partial address, and the data transfer network includes a partial network connected to each other in the grouped plurality of processor groups and each of the processors. It has a plurality of exchange switches corresponding to one-to-one, Thus, each processor is connected to the D partial networks corresponding respectively to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches the specified processor, it transfers it to the processor, and if it is another packet, transfers it to a partial network different from the partial network that received it. The data contained in the packet consists of multiple bits. The partial network has a plurality of partial data, and the plurality of switches are connected in multiple stages in the partial network, and each switch that constitutes the partial network and the exchange switch is connected to a switch in a front stage and a switch in a rear stage, respectively. , A means for receiving the packet, wherein the receiving means is The individual partial addresses of the partial addresses of the above receive all the bits in parallel, the individual partial data of the above multiple partial data receive all of the bits in parallel, and the multiple partial addresses of the multiple partial addresses Data is sequentially received, and each switch has a route selecting unit connected between the receiving unit and a plurality of switches in the next stage, and the route selecting unit is provided with a plurality of received partial addresses. Each partial address or all bits of the partial data are transferred in parallel, and each partial data of a plurality of partial data transfers all of its bits in parallel, and a plurality of partial addresses,
A plurality of partial data are sequentially transferred, each switch has a control means connected to the receiving means and the route selecting means, and the control means is a predetermined one of the partial addresses. The routing means is controlled in response to a plurality of bits, and the control means included in at least some of the switches is responsive to the arrival of the first partial address of the packet and at least one of the remaining ones or more. A data transfer network, characterized in that, before a partial address arrives, it decodes one or more predetermined bits in the first partial address to control the route selecting means. 4. In a data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors comprises an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 2 or more) composed of a plurality of bits. , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to each other, Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches the processor, it is forwarded to the processor, and if it is another packet, it is forwarded to a subnetwork different from the subnetwork that received it. The data contained in the packet is composed of multiple bits. In the partial network, a plurality of switches are connected in multiple stages, and each switch constituting the partial network and the exchange switch is connected to a front stage switch and a rear stage switch, respectively. And a means for receiving the packet, wherein the receiving means is Each partial address of the plurality of partial addresses receives all its bits in parallel, each partial data of the above plurality of partial data receives all its bits in parallel, and The partial data are sequentially received, and each switch has a route selecting unit connected between the receiving unit and a plurality of switches in the next stage, and the route selecting unit is provided with a plurality of received partial addresses. Individual partial addresses of all of the bits are transferred in parallel, all bits of individual partial data of multiple partial data are transferred in parallel, and multiple partial addresses and multiple partial data are serially transferred. Each switch has a control means connected to the receiving means and the route selecting means, the control means being a predetermined one of the partial addresses or In response to the number of bits to control said routing means, at least the exchange switch of said switch,
A transfer order changing means for changing the transfer order of the plurality of received partial addresses, and when the packet is transferred from one partial network to another partial network, the packet is included in the other partial network. A data transfer network characterized in that the control means of the switch first transfers, among all the received partial addresses, the partial addresses required for controlling the path selecting means. 5. A data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors comprises an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 3 or more) composed of a plurality of bits, and the plurality of processors are A partial address of a set of the D sets is divided into groups having the same partial address, and the data transfer network includes a partial network that connects a plurality of grouped processors to each other in the group and each of the processors. It has a plurality of exchange switches corresponding to one-to-one, Thus, each processor is connected to the D partial networks corresponding respectively to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. Forwarded to the processor, and in the case of other packets, the partial address corresponding to that partial network in a partial network different from the one that received it A data transfer network characterized in that the data is transferred to a partial network different from the connected processor. 6. In a data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors comprises an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 3 or more) composed of a plurality of bits, and the plurality of processors are , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to each other, Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches with the processor, the packet is forwarded to the processor, and in the case of another packet, the partial address corresponding to the partial network in the partial network different from the partial network receiving the packet Transferring to a partial network different from the connected processor, said partial network having means for decoding one or more predetermined bits of said partial address to determine the transfer destination of said packet; The switch transfers the received multiple partial addresses. All that have means for changing the order, and when the packet is transferred from one partial network to another partial network, the transfer destination determining means has received the partial addresses necessary for determining the transfer destination. A data transfer network characterized by being transferred first among the partial addresses of. 7. In a data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors includes an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 3 or more) composed of a plurality of bits, and the plurality of processors are , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to each other, Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches the processor, the packet is forwarded to the processor, and in the case of another packet, the partial address corresponding to the partial network in the partial network different from the partial network which received the packet Transferred to a partial network different from the connected processor, the data included in the packet has a plurality of partial data composed of a plurality of bits, and the partial network has a plurality of switches connected in multiple stages, Each switch that makes up the network and switching switches , Each of which is connected to each of the front-stage switch and the rear-stage switch and which receives the packet from the front-stage switch, and the receiving unit receives all the bits of each partial address of the plurality of partial addresses in parallel. However, each partial data of the plurality of partial data receives all the bits in parallel, and sequentially receives a plurality of partial addresses and a plurality of partial data. There is a route selecting means connected between the plurality of switches in the next stage, the route selecting means transferring all the bits of each of the received partial addresses of the partial addresses in parallel, and All the bits of the individual partial data of the partial data of are transferred in parallel, and a plurality of partial addresses and a plurality of partial data are sequentially transferred, and each switch is The control means is connected to the receiving means and the route selecting means, and the controlling means controls the route selecting means in response to one or more predetermined bits of the partial address. The control means included in at least some of the switches of the switch are responsive to the arrival of the first partial address of the packet before the remaining at least one or more partial addresses arrive in the first partial address. A data transfer network characterized by decoding one or more predetermined bits to control the path selecting means. 8. A data transfer network for connecting a plurality of processors and transferring data between them, the data transfer between the processors comprises an address of a destination processor or a tag indicating the address and data to be delivered. And a tag indicating the address of the destination processor is composed of a partial address of D sets (D is an integer of 3 or more) composed of a plurality of bits, and the plurality of processors are , A group of partial addresses of the D group having the same partial address, and the data transfer network includes a partial network for connecting a plurality of grouped processors to each other in the group, and each of the processors. Has a plurality of exchange switches corresponding to each other, Therefore, each processor is connected to D partial networks respectively corresponding to the D sets of partial addresses, and the switching switch is connected to the destination address of the packet received from a partial network. If it matches with the processor, the packet is forwarded to the processor, and in the case of another packet, the partial address corresponding to the partial network in the partial network different from the partial network receiving the packet Transferred to a partial network different from the connected processor, the data included in the packet has a plurality of partial data composed of a plurality of bits, and the partial network has a plurality of switches connected in multiple stages, Each switch that makes up the network and switching switches Has means for receiving the packet from the switch at the front stage and the switch at the rear stage, respectively, and the receiving unit is arranged so that each partial address of the plurality of partial addresses has all its bits in parallel. Each of the individual partial data of the plurality of partial data is received in parallel, and a plurality of partial addresses and a plurality of partial data are sequentially received. And a plurality of switches in the next stage, the route selecting means transfers all the bits of each partial address of the plurality of received partial addresses in parallel, and All bits of individual partial data of plural partial data are transferred in parallel, and plural partial addresses and plural partial data are sequentially transferred. And a control means connected to the reception means and the route selection means, the control means controlling the route selection means in response to one or more predetermined bits of the partial address, At least the replacement switch of the switches is
A transfer order changing means for changing the transfer order of the plurality of received partial addresses, and when the packet is transferred from one partial network to another partial network, the packet is included in the other partial network. A data transfer network characterized in that the control means of the switch first transfers, among all the received partial addresses, the partial addresses required for controlling the path selecting means.