JPH0830567A - Mutual access method between processors of parallel computer - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To enable the processes of each processor of a parallel computer on which multiple parallel programs operate to mutually access the virtual space of processes on other processors. [Configuration] A parallel computer assigns an identifier of a parallel program as a common identifier to all shared areas of each process in which the parallel program is operating, and each processor processes each process in its own processor in correspondence with the shared area identifier. Area designation tables 106 and 2 for holding information of shared areas of
06, the requesting processor 101 sets the identifier in the area designation register 104 and the partner processor number in the PE number register, specifies the virtual address of the data to be accessed, and specifies the identifier, the partner processor number and the virtual address. Is transmitted to the reply side processor 201 by the TLB, and the reply side converts the offset into the corresponding real address in its own processor based on the contents and the identifier of the area designation table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mutual access method between processors in a parallel computer, and more particularly, in a parallel computer in which a plurality of parallel programs operate, a process operating on each processor is a process operating on another processor. The present invention relates to a mutual access method between processors that enables access to a virtual space.

[0002]

2. Description of the Related Art A parallel computer in which a plurality of processors are connected to perform parallel processing is an important technique because it can increase the speed of calculation according to the number of processors.
When the number of processors is relatively small (up to several tens), a shared memory parallel computer has been put into practical use. On the other hand, when the number of processors is large (several hundreds or more), a distributed memory parallel computer has been developed in order to avoid concentration of access to the shared memory.

Conventionally, in a distributed memory type parallel computer, when data in a memory on another processor is required, a message passing method has been used in which a partner processor transfers a block of data to a memory on its own processor. On the other hand, in order to realize the ease of use of the shared memory parallel computer with the distributed memory parallel computer,
A research on a distributed shared memory type parallel computer which can directly access a memory on another processor has been actively conducted. In a distributed shared memory type parallel computer, it is necessary to realize a global address space in order to make all the memories in the parallel computer accessible.

Conventionally, in a parallel computer configured by using a plurality of clusters each having a local memory and capable of operating independently, the virtual space of another processor can access the virtual space of another processor. As a method, a method has been adopted in which access is performed by designating a logical processor number, a logical page number and an offset within a page. For example, the system discussed in JP-A-5-89056 and JP-A-5-181751 corresponds to this. When a parallel computer realizes a multi-process environment, a plurality of parallel programs operate across a plurality of clusters, and each processor needs to execute a plurality of processes. Since there is no way to specify the destination process when accessing, it is called gang scheduling in which the same process runs on all processors and all processes switch processes to processes that make up the same parallel program when switching processes. Uses a process switching method.

[0005]

In the above prior art, in gang scheduling, a process switching request is sent to all processors at the time of process switching, and after confirming that all accesses issued by all processors have been completed, Since it is necessary to send a process switching instruction to all processors, a large overhead occurs when switching processes. Further, since different processes cannot be executed by each processor, even if some of the processes that make up the parallel program are in the execution suspended state, it is not possible to switch only these processes. It is an object of the present invention that, in a parallel computer in which a plurality of parallel programs operate, a process which is in charge of each processor of the parallel program can mutually access the virtual space of the process even if task switching is freely performed in each processor. Is to provide a method.

[0006]

To achieve the above object, the present invention provides a plurality of clusters each including one or more processors and a main memory used by the one or more processors, and the plurality of clusters. And a network for connecting at least one process to which virtual space is allocated in each processor and configured by a set of a plurality of processes operating on each processor on one or more clusters in the system. In a parallel computer in which at least one parallel program operates, the process, which is a processor responsible portion of the parallel program operating in each processor in the cluster, configures the same parallel program on a processor in another cluster. Can access the real memory area corresponding to the shared area in the virtual space In the method of mutual access between processors, the parallel computer assigns an identifier of the parallel program as an identifier common to all shared areas of each process in which the parallel program is operating, and each processor assigns the shared area identifier to the shared area identifier. Correspondingly, an area designation table for holding information on the shared area of each process in the own processor is provided, and the requesting processor has the shared area identifier,
Specify the destination processor number that holds the shared area to be accessed and the virtual address of the data to be accessed,
The identifier of the destination, the processor number of the other party, and the offset of the real address obtained by converting the virtual address are sent to the responding processor for access, and the responding processor accesses the contents of the area designation table and the shared area. Based on the identifier, the offset is converted into a corresponding real address in its own processor. Further, the parallel computer allocates one shared area identifier corresponding to the entire shared area of each process in which the parallel program is operating. Further, the requesting processor specifies the shared area identifier and a virtual address including a partner processor number holding a shared area to be accessed as a virtual address of data to be accessed, and the identifier,
The destination processor number obtained by converting the virtual address including the destination processor number and the offset of the real address are sent to the responding processor for access. Further, the shared area is continuously secured on the real memory, each entry of the area designation table has a shared area identifier and a base address and size of the real memory area corresponding to the shared area, and the network interface circuit The area specification table is accessed by the shared area identifier from the side processor, and the real address is obtained by adding the offset from the requesting processor to the base address of the obtained entry. Further, the area designation table is provided for each cluster, and the shared area is continuously secured on the real memory. Each entry of the area designation table is a processor number in the cluster, a shared area identifier, and a real memory area corresponding to the shared area. The network interface circuit has a base address and a size, and the network interface circuit accesses the area designation table by the processor number and the shared area identifier from the requesting processor, and the base address of the obtained entry is offset from the requesting processor. The real address is obtained by adding. Also, the destination processor number sent by the requesting processor is used as a logical processor number, the shared area is continuously secured in the real memory, and each entry of the area designation table is a shared area identifier, a logical processor number, and a shared area. Having the base address and size of the corresponding real memory area, the responding processor accesses the area designation table with the shared area identifier and logical processor number from the requesting processor, and uses the base address of the obtained entry The actual address is obtained by adding the offset from the requesting processor. Further, each entry of the area designation table is further incremented at the time of issuing an access in correspondence with the shared area identifier,
The count value is decremented when the access is completed. Each entry of the area designation table further has an area valid flag, a read flag, and a write flag corresponding to the shared area identifier. Further, a processor number conversion means for converting the partner processor number designated by the requesting processor into a logical processor number and converting the partner processor number from the logical processor number to the physical processor number is provided, and the logical processor number is converted by the means. It is converted to a number and sent to the responding processor. Also,
The area designation table is arranged in the main storage device, an area designation table cache is provided, and entries of the area designation table are cached in the area designation table cache.

[0007]

According to the present invention, the shared area of the processes on each processor forming the parallel program is represented by a common identifier, and the shared area identifier of the own process is added when the shared area of another processor is accessed. Therefore, regardless of which process is running on the other processor, the shared area of the other processor corresponding to the own process can be accessed.

[0008]

EXAMPLES Example 1 Hereinafter, a first example of the present invention will be described. FIG. 1 shows a parallel computer according to the present invention. In this embodiment, a plurality of clusters 100 and 200 are connected by a network 300. In FIG. 1, 101,
Reference numeral 201 denotes a processor, which may have the same configuration as a conventional microprocessor. In FIG. 1, one processor is provided for each cluster for simplification, but each cluster 100, 200 has a tightly coupled multiprocessor configuration including one or more processors. Each cluster 10
Reference numerals 0 and 200 include processor units 10 and 20, one network interface circuit 12 and 22, and main storage devices 107 and 207. When the cluster 100 is provided with a plurality of processors, a plurality of processors similar to the processor unit 10 are connected. Even when the cluster 200 is provided with a plurality of processors, a plurality of processors similar to the processor unit 20 are connected.

The main storage devices 107 and 207 are accessed by using the address line and the data line by using the conventional technique. For the main memory, for example, 0x0 for a 32-bit processor
0000000 to 0x7FFFFFFF (0x is 16
Range is implemented, and the address space in which the most significant bit is 1 has no corresponding real memory in its own processor. A network 300 connects a plurality of clusters 100 and 200, and when a destination processor address is designated by a certain processor, it is controlled by a network interface circuit and transmits data or the like to a partner processor corresponding to the address. 111, 211
Is a request message transmitting circuit for transmitting a memory access request to another processor, 112 and 212 are request message receiving circuits for receiving a memory access request from another processor, and 113 and 213 are requesting a memory access request from another processor. The message receiving circuit 112,
Response message transmission circuits 114, 214 for obtaining access from the main memory devices 107, 207 and transmitting a response message for the memory access by receiving the response message from the partner processor for the access request from the own processor. It is a reply message receiving circuit for returning access to the processor, and exists in the network interface circuits 12 and 22, respectively.

In this embodiment, a plurality of clusters 100, 2
A parallel program executed over a plurality of processors (101, 201, etc.) on 00 is composed of processes operating on each processor, and each process corresponds to a shared area of the process and main storage devices 107, 207. It has a real memory area on top, and the identifier of the parallel program is given as an identifier of the shared area as an identifier common to all processes constituting the parallel program. Each processor 101,
201 has area designation tables 106 and 206 having table entries which are identifiers of shared areas corresponding to all processes executed by the processor. Further, the area designation registers 104 and 204 hold the identifiers of the parallel programs of the processes currently being executed.

In this embodiment, the shared area is secured as a continuous area in the real address space, and the identifier of the parallel program common to each process forming the same parallel program is given as the shared area identifier. Avoid management in page units by managing by the base address and size of the area, and when accessing the shared area of other process, the offset in the address consisting of the processor number (PE number) and the offset is translated by TLB. , The address of the shared area of the process on the access side is added to the address of the converted offset, and this is sent to the cluster on which the processor of the PE number, which is the access side, is present. Access is made by accessing the shared area that is uniquely determined. Is characterized in that access a shared area of a process corresponding irrespective processes running that side.

The structure of the virtual space of each process is shown in FIG. In the figure, process A, process B, and process C exist on the processor (PE) 101. Each process is a virtual private area (virtual P area) 403, 4 that is accessed only by the process on the processor 101.
13, 423, and the entity of the shared area is the processor 10
1 and virtual local areas (virtual L areas) 402, 412, 422 accessed by processes on the processor 101 and other processors, and virtual windows which are windows for accessing the virtual local areas on other processors from the processor 101. Global area (virtual G area)
It consists of 401, 411 and 421. Where process A
“0” attached to each of the areas 401, 402, and 403 is an area identifier, and a parallel program number is used as the area identifier. Here, the parallel program number is “0”. In addition, each area 411, 412, 41 of the process B
The area identifier of 3 is the parallel program number “1”,
The area identifier of each area 421, 422, 423 of the process C is the parallel program number “2”.

Virtual private areas 403, 413, 4
Reference numeral 23 denotes an arbitrary real private area (real P area) 4 on the main memory 107 in the processor 101 in page units by address translation by the TLB in the processor 101.
32, 434, 436, 438. At this time, the most significant bit of the address output from the TLB is 0, and the address determination circuit 102 determines this,
The address is sent to the main storage device 107. As a result, the virtual private areas 403, 41
When accessing 3, 423, the address in the corresponding real private area is referred to.

Virtual local areas 402, 412, 422
Is a continuous real local area (real L area) 433, 43 on the main memory 107 in the processor 101 due to the address translation by the TLB in the processor 101.
5, 437. At this time, the most significant bit of the address output from the TLB is 0, the address determination circuit 102 determines this, and the address is sent to the main storage device 107. As a result, when each process accesses the virtual local area 402, 412, 422, the address in the corresponding real local area 433, 435, 437 is referred to.

Virtual global areas 401, 411, 42
All 1's are converted into one continuous real global area (real G area) 431 by address conversion by the TLB in the processor 101. The real global area obtained as a result of the conversion is an area in which the most significant bit of the real address is 1, and there is no corresponding area in the main storage device 107, and the address judgment circuit 102 judges this and the conversion is performed. The output address is sent to the request message sending circuit 111.

On the other processor 201, the real local areas 445, 447, 443 are continuous areas starting from arbitrary addresses, and do not have to have the same addresses as the corresponding areas on the processor 101. Real local area 445
The area identifier of is the parallel program number "0", the area identifier of the real local area 447 is the parallel program number "1", and the area identifier of the real local area 443 is the parallel program number "2".

Information (region base address, region size, etc.) on each of the above real local regions is registered in the region designation table 106 or the region designation table 206 of FIG. As shown in FIG. 3, the contents of the area designation tables 106 and 206 include an area identifier, an area valid flag, an area base address, an area size, an access counter, a read flag, and a write flag. The area identifier is a common identifier given to each process forming the parallel program, and is designated by the number of the parallel program. The area valid flag is a flag that indicates whether each real local area is valid or invalid, and when the invalid real local area is accessed by the other processor 101, the error determination circuit 205 determines that and accesses the processor 201. Add complexity. The area base address indicates the start address of each area in the real address space, and the area size indicates the number of bytes in each area.

The access counter exists to guarantee the completion of access to the shared area on another processor for each shared area. The access counter is set to 0 when the shared area is created. When the processor 101 issues an access to the processor 201 on another cluster, the area designation table 106 is searched for an entry having the same area identifier as the value held in the area designation register 104 when the access is issued, and the access counter of this entry is searched. Is incremented. Processor 20 on another cluster
When the access issued to 1 returns to the reply message receiving circuit 114, the access counter of the entry of the area designation table 106 corresponding to the area identifier in the message is decremented. Thus, when an access is issued to a shared area of a processor on another cluster, the access counter of the corresponding area in the area designation table 106 is incremented, and when the issued access returns, the access counter of the corresponding area in the area designation table 106 is returned. The access counter is decremented. Therefore, the access counter represents the number of incomplete accesses among all the accesses issued to the shared area on the other cluster. When performing synchronization with a parallel program, guarantee the completion of all access before synchronization. At this time, by waiting until the access counter reaches 0, it is possible to guarantee the completion of all accesses before the synchronization.

The read flag is a flag for designating permission or non-permission of read access to the shared area from another processor, and the write flag is a flag for designating permission or non-permission of write access to the shared area from another processor. Is. Some parallel programs allow reading of the shared area of other processors, but do not write to the shared area of other processors. When such a parallel program is executed, erroneous writing is prevented by disabling write access to the shared area of another processor with the write flag. Also, when performing exclusive processing during execution of a parallel program,
Temporarily prohibit reading and writing to the shared area from other processors. This can be realized by setting the read flag and the write flag in the non-permission state.

When accessing a local area of a process on another processor 201 from a process on the processor 101, a global area on the processor 101 is used. In this embodiment, the process A is executed on the processor 101.
The case where is being executed will be described. (Step 1) When process A (area identifier is parallel program number 0) accesses local area 462 of process D (area identifier is parallel program number 0) on another processor 201 of the same parallel program,
The parallel program number 0 is set in the area designation register 104 as the area identifier, the processor number of the processor 201 in the address is set in the PE number register 103, and the virtual global area 401 is accessed. The type of access is a read request or a write request and is determined by the control line of the processor. (Step 2) To access the virtual global area 401, the offset within the address is set to the processor 101.
The address is converted to the real global area 431 by the TLB in the inside and is output to the address line 120a of the processor. (Step 3) The address determination circuit 102 determines that the real global area 4 is set because the most significant bit of the address is 1.
It is determined that the access is to 31 and the most significant bit is set to 0 to obtain the offset in the real local area of the partner processor 201, and this is transferred to the request message circuit 111 through the signal line 170o. Also, the value of the access counter of the area designation table 106 corresponding to the value of the area designation register is incremented.

(Step 4) Request message transmission circuit 1
11 receives the offset in the area, the value of the PE number register 103 and the value of the area designation register 104 are sent to the signal line 1
Obtain through 50p, 160r. If the access is write, the write value is set to the data line 132d.
Get through. (Step 5) The request message transmission circuit 111 generates a request message for the partner processor 201 based on the information obtained in step 4, and sends it to the network 300. As shown in FIG. 4, the request message is composed of a packet header and transfer data, and the packet header includes a receiving side processor number, a transmitting side processor number, a transfer data length, a packet type, an area identifier, and an area offset. The processor number on the receiving side is the value of the PE number register 103, and the processor number on the transmitting side is the own processor 10.
1 processor number, transfer data length is transfer data size, packet type is request message type and read request or write request, area identifier is value of area designation register, area offset is offset generated by address determination circuit 102. Is.

(Step 6) The request message is received by the request message receiving circuit 212 of the processor 200. (Step 7) The request message receiving circuit 212 gives the area identifier of the request message to the area designation table 206 through the signal line 261r, and reads the attribute of the corresponding real local area. At this time, if the real local area 445 does not exist in the area designation table 206 or if the area valid flag of the real local area 445 indicates invalid, an error occurs and the processor 200 is interrupted. (Step 8) When a valid real local area 445 corresponding to the area identifier of the request message exists, the area offset of the request message and the area size of the corresponding entry of the area designation table 206 are compared by the error determination circuit 205, and the area If the offset is equal to or larger than the area size, an error occurs and the processor 201 using the signal line 284e.
Interrupt. Also, if the read flag of the corresponding valid real local area in the read request access indicates disapproval, an error occurs if the write flag of the corresponding valid real local area in the write request access indicates disapproval. Interrupt the processor 201.

(Step 9) When the access is made normally, the above error is not established and the area designation table 206
The area base address 280b is read from the address area 280b, the area offset is added by the adder 208, and the address 223a of the data in the corresponding real local area is calculated and given to the reply message transmission circuit 213. Further, each information such as the sender processor number, the transfer data length, and the packet type on the header of the request message is also given to the reply message sending circuit 213. (Step 10) The reply message sending circuit 213 accesses the main memory device 207 using the address line 222a and the data line 238d, assembles the result into a reply message, and sends it to the network 300. (Step 11) The reply message receiving circuit 114 receives the reply message and returns the result to the processor 100. Through the above operation, the real local area 445 of the process D forming the same parallel program on the other processor 201 can be accessed from the virtual global area of the process A, and as a result, the virtual local area 402 of the process D is accessed.

Next, a case where the process A in the processor 101 suspends execution and the process B of another parallel program number 1 is in execution will be described. When the process B is being executed due to the process switching, the area identifier 1 is written in the area designation register 104. When the process B accesses the other processor 201 during execution, the PE number register 10 is used as in the case described above.
The processor number of the processor 201 is written in 3, and the virtual global area 411 is accessed. Then, the virtual global area 411 is converted into the real global area 431, and the request message transmission circuit causes the other processor 201
Access to is issued. In the processor 201, since 1 is designated as the area identifier, the processor 2
It is recognized that the access is to the real local area 447 of 01, and the access is performed correctly. As described above, since the area identifier is specified by the accessing processor regardless of the process running on the accessed processor, the storage device can be accessed even when each processor is executing a different parallel program process. It works without problems. The above is the first embodiment.

<Modification of First Embodiment> In the embodiments described above, the identifier of the parallel program is used as the identifier of the shared area. However, a unique identifier is provided in the shared area itself, and the parallel program is used as the area identifier. This may be used instead of the identifier of the identifier. In this case, each process on each processor can hold a plurality of virtual local areas and the corresponding real local areas.

In step 1 above, the other processor is specified by writing the PE number in the PE number register 103. However, the TLB is configured to give the PE number and offset to the address determination circuit 102, and the address determination circuit is provided. It is also possible to specify and specify by the upper bits of the area offset line 170o output by 102.
In this case, the PE number register 103 becomes unnecessary. In this case, the output data width of TLB becomes large.

Further, in step 1 above, the area in the destination processor is specified by writing the area identifier in the area number register 104. However, the TLB is configured so as to give the area identifier to the address judging circuit, and the address is determined. It may be specified by a plurality of upper bits of the area offset line 170o output from the determination circuit 102. In this case, the area designation register 104 becomes unnecessary. In this case, the output data width of TLB becomes large.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIG. Since this embodiment is a modification of the first embodiment,
Only the differences will be described. In this embodiment, the area designation tables 106-2 and 206-2 are set to the clusters 100 and 20.
One is set to 0, and the area designation table 106 is correspondingly set.
-2, 206-2 is different in that the structure is changed. The structure of the area designation tables 106-2 and 206-2 is shown in FIG. The contents of the area designation table 106-2 in this embodiment adds a processor number to the area designation table of the first embodiment, and accesses the area designation table 106-2 with a set of a processor number and a shared area identifier.

In the present embodiment, a process in the cluster 200 when a request message from the processor 101 to the processor 201 arrives at the request message receiving circuit 212 will be described along with the steps of the first embodiment. (Step 7) The request message is received by the request message receiving circuit 212 of the cluster 200. The request message circuit 212 gives the processor number and the area identifier of the request message to the area designation table 106-2, and reads the attribute of the corresponding real local area. If the real local area 445 does not exist in the area designation table 206, or if the area valid flag of the real local area 445 indicates invalid, an error occurs and the processor 20
Interrupt one. According to the present embodiment, by preparing the area designation table in units of clusters, the area designation tables can be collectively controlled in units of clusters.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIG. Since this embodiment is a modification of the first embodiment,
Only the differences will be described. The present embodiment is different only in that the PE number registers 103 and 203 are designated by logical processor numbers instead of real processor numbers. The conversion from the real processor number to the logical processor number is performed by the circuit shown in FIG. 7 in the processor 201 on the access issue side. Reference numeral 203-2 in FIG. 7 denotes a PE number conversion circuit, 203-3
Is a PE number conversion table. The PE number conversion table 203-3 is a table which is accessed by the PE number conversion circuit 203-2 with a combination of an area identifier and a logical processor number and which returns an actual processor number.

In this embodiment, the processor 201 writes the logical processor number in the PE number register 203. P
The E number conversion circuit 203-2 is a PE number register 203 of the processor and an area designation register 20 representing a processor group.
The PE number conversion table 203-3 is accessed with a set of 4 values, the logical processor number of the PE number register 203 is converted into the real processor number, and the result is transferred to the request message transmission circuit. (Step 4) Upon receiving the offset within the area, the request message transmission circuit 111 obtains the destination processor number and the value of the area designation register 104 through the signal lines 150p and 160r. When the access is writing, the value to be written is obtained through the data line 132d.

According to this embodiment, each parallel program can be executed by a processor group formed by a combination of arbitrary processors in a parallel computer, and a plurality of processes can be executed on each processor.

<Fourth Embodiment> A fourth embodiment of the present invention will be described. Since this embodiment is a modification of the third embodiment, only different points will be described. This embodiment differs from the third embodiment in that a logical processor number is added to a request message and the area designation table 106 is accessed by a combination of the logical processor number and the shared area identifier in the partner processor.

Area designation table 106-3 in this embodiment
The structure of is shown in FIG. Area designation table 1 in this embodiment
06-3 is added with a logical processor number and is accessed by a set of a logical processor number and a shared area identifier. The structure of the request message of this embodiment is shown in FIG.
Shown in The request message is added with the logical processor number of the receiving side in addition to the receiving side processor number required for transferring the message to the responding processor or cluster by the interconnection network 300.

The structure of the virtual space of each process in this embodiment is shown in FIG. In the figure, a parallel program I is operating, and a logical processor 0 and a logical processor 1 are arranged on a processor (PE) 101, and a logical processor 2 and a logical processor 3 are arranged on a processor 201. Logical processors 0, 1, 2, 3 process A,
Perform B, D, and E. 501, 511, 521, 56
1, 571 and 581 are virtual global areas of respective processes, 502, 512, 522, 562, 572 and 582.
Is a virtual local area of each process, 503, 513, 5
23, 563, 573, 583 are virtual private areas of the respective processes, 531, 541 are processors 101, 2
01 real global area, 532, 534, 536, 5
38, 542, 544, 546, 548 is the processor 1
Real private areas 01 and 201, 533 are processors 10 corresponding to the virtual local area 502 of process A
1 is a real local area of the processor 101 corresponding to the virtual local area 512 of the process B, 537 is a real local area of the processor 101 corresponding to the virtual local area 522 of the process C, and 545 is a virtual local area of the process D. The real local area of the processor 201 corresponding to the local area 562, 547 is the real local area of the processor 201 corresponding to the virtual local area 572 of the process E, and 543 is the real local area of the processor 201 corresponding to the virtual local area 582 of the process F. Is. The shared areas of the parallel program I are virtual local areas 502, 512, 562, 572, and are accessed using the common shared area identifier 0.

The present embodiment differs from the third embodiment in the case where the process A running on the logical processor 0 uses the virtual global area of the process A to access the virtual local area of the process D on the logical processor 2. I will explain mainly. (Step 1) The processor 101 sets the area number 0 in the area designation register 104 according to the program of the process A, sets the processor number of the logical processor 2 in the PE number register 103, and sets the virtual global area 501.
Access to. The type of access is a read request or a write request. (Step 2) The access to the virtual global area is translated into the real global area 531 by the TLB in the processor 101 and output to the address line 120a of the processor. (Step 3) Same as the first embodiment. (Step 4) In addition to step 4 of the third embodiment, the request message transmission circuit 111 obtains the logical processor number from the PE number register 103. (Step 5) Same as Step 5 of the first embodiment,
The request message has the structure shown in FIG. (Step 6) Same as the first embodiment. (Step 7) The request message receiving circuit 212 gives the area identifier and logical processor number of the request message to the area designation table 206 through the signal line 261r, and reads the attribute of the corresponding real local area 545. This time,
If the real local area 545 does not exist in the area designation table 206, or if the area valid flag of the real local area 545 indicates invalid, an error occurs and the processor 201 is interrupted. (Step 8) Same as the first embodiment. (Step 9) Same as the first embodiment. (Step 10) Same as the first embodiment. (Step 11) Same as the first embodiment. By the above operation, the real local area 545 of the process D constituting the same parallel program on the other logical processor 1 can be accessed from the virtual global area 402 of the process A being executed by the logical processor 0, and as a result, the virtual local area of the process D is local. The area 562 has been accessed. According to this embodiment, it is possible to execute a plurality of processes forming a parallel program on one real processor, and the number of processors can be virtualized.

<Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to FIG. Since this embodiment is a modification of the first embodiment, only different points will be described. In this embodiment, the area designation tables 106 and 206 are stored in the main storage devices 107 and 207.
It is different in that it is held above and only necessary portions are cached in the area table caches 106C and 206C. Area designation table cache 106C, 20
6C has the same structure as the area designation table except that an entry valid bit is added to each element of the area designation table shown in FIG.

In this embodiment, the processing in the cluster 200 when a request message from the processor 101 to the processor 201 arrives at the request message receiving circuit 212 will be described along with the steps of the first embodiment.

(Step 7) The request message is received by the request message receiving circuit 212 of the cluster 200. The request message circuit 212 gives the area identifier of the request message to the area designation table cache 206C through the signal line 261r, and reads the attribute of the corresponding real local area. At this time, if the attribute of the corresponding real local area does not exist in the area designation table cache 206C, or if the entry valid bit of the attribute of the corresponding real local area indicates invalid, the area designation in the main storage device 207 The attribute of the corresponding real local area of the table 206 is accessed, and the area designation table cache 206 is accessed.
C is cached. Caching is a conventional technique and will not be described. If the real local area 445 does not exist in the area designation table 206, or if the area valid flag of the real local area 445 indicates invalid, an error occurs and the processor 200 is interrupted. When changing the area designation table 206, the processor invalidates the entry valid bits of all entries in the area designation table cache 206. According to this embodiment, the area designation table can be stored in the main storage device, the amount of hardware can be reduced as compared with the first embodiment, or the maximum number of areas can be increased.

[0040]

According to the present invention, each processor constituting a parallel computer can access the shared area corresponding to the process on its own processor regardless of the process running on the partner processor. Therefore, a plurality of parallel programs can be operated on the parallel computer.

[Brief description of drawings]

FIG. 1A is a diagram showing a part of a configuration of a parallel computer according to a first embodiment.

FIG. 1B is a diagram showing another part of the configuration of the parallel computer according to the first embodiment.

FIG. 2 is a diagram showing a relationship between a virtual address space and a real address space according to the first embodiment.

FIG. 3 is a diagram showing a configuration of an area designation table according to the first embodiment.

FIG. 4 is a diagram showing a packet configuration according to the first embodiment.

FIG. 5A is a diagram showing a part of a configuration of a parallel computer according to a second embodiment.

FIG. 5B is a diagram showing another part of the configuration of the parallel computer according to the second embodiment.

FIG. 6 is a diagram showing a configuration of an area designation table according to the second embodiment.

FIG. 7 is a diagram illustrating a configuration of a processor number conversion circuit according to a third embodiment.

FIG. 8 is a diagram showing a configuration of an area designation table according to the fourth embodiment.

FIG. 9 is a diagram showing the structure of a packet according to the fourth embodiment.

FIG. 10 is a diagram showing a relationship between a virtual address space and a real address space according to the fourth embodiment.

FIG. 11A is a diagram showing a part of a configuration of a parallel computer according to a fifth embodiment of the present invention.

FIG. 11B is a diagram illustrating another part of the configuration of the parallel computer according to the fifth embodiment.

[Explanation of symbols]

100, 200 clusters 10, 20, 10-2, 20-2, 10-3, 20-3
Processor unit 12, 22, 12-2, 22-2, 12-3, 22-3
Network interface circuit 101, 201 Processor 102, 202 Address determination circuit 103, 203 Processor number register 104, 204 Area designation register 203-2 Processor number conversion circuit 203-3 Processor number conversion table 105, 205 Error determination circuit 106, 206 Area designation Table 106C, 206C Area designation table cache 107, 207 Main memory 108, 208 Address adder 111, 211 Request message transmitting circuit 112, 212 Request message receiving circuit 113, 213 Reply message transmitting circuit 114, 214 Reply message receiving circuit 300 Mutual Coupling network 120a, 220a Processor address bus 121a-123a, 221a-223a Main memory access address line 130 d-139d, 230d-239d Data line 140m-143m, 240m-243m Message line 150p, 250p Processor number line 160r, 161r, 260r, 261r Area number line 170o, 171o, 270o, 271o Area offset line 180b, 280b Area base address Line 182s, 282s Area size line 184e, 284e Error signal line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naonobu Sukegawa 1-280, Higashikoigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] 1. A plurality of clusters comprising one or more processors and a main storage device used by the one or more processors, and a network connecting the plurality of clusters, wherein a virtual space is provided in each processor. A parallel computer in which at least one allocated process operates and at least one parallel program configured by a set of a plurality of the processes operating on each processor on one or more clusters in the system operates, The process, which is the processor in charge of the parallel program running on each processor in the cluster, accesses the real memory area corresponding to the shared area in the virtual space of the process forming the same parallel program on the processor in another cluster. A mutual access method between processors, which enables: The column computer allocates an identifier of the parallel program as a common identifier to all shared areas of each process in which the parallel program is operating, and each processor shares each process in its own processor in correspondence with the shared area identifier. An area specification table holding area information is provided, and the requesting processor specifies the shared area identifier, the partner processor number holding the shared area to be accessed, and the virtual address of the data to be accessed. The partner processor number and the offset of the real address obtained by converting the virtual address are sent to the responding processor for access, and the responding processor is based on the contents of the area designation table and the shared area identifier. The offset is converted into a corresponding real address in its own processor. Method for mutual access between processors of parallel computer. 2. A plurality of clusters each comprising one or more processors and a main storage device used by the one or more processors, and a network connecting the plurality of clusters, wherein a virtual space is provided in each processor. A parallel computer in which at least one allocated process operates and at least one parallel program configured by a set of a plurality of the processes operating on each processor on one or more clusters in the system operates, The process, which is the processor in charge of the parallel program running on each processor in the cluster, accesses the real memory area corresponding to the shared area in the virtual space of the process forming the same parallel program on the processor in another cluster. A mutual access method between processors, which enables: The column computer allocates one shared area identifier corresponding to the entire shared area of each process in which the parallel program is operating, and each processor corresponds to the shared area identifier of the shared area of each process in its own processor. The requesting processor has an area designation table for holding information, and the requesting processor designates the shared area identifier, the partner processor number for holding the shared area to be accessed, and the virtual address of the data to be accessed. The offset of the destination processor number and the real address obtained by converting the virtual address is sent to the responding processor for access, and the responding processor uses the offset based on the contents of the area designation table and the shared area identifier. Of a parallel computer, which is characterized by translating the corresponding real address in its own processor. Mutual access method between sessa. 3. The interprocessor mutual access method for a parallel computer according to claim 1, wherein the requesting processor holds the shared area identifier and a shared area to be accessed as a virtual address of data to be accessed. The virtual address including the partner processor number is designated, and the identifier, the partner processor number and the offset of the real address obtained by converting the virtual address including the partner processor number are sent to the responding processor. A mutual access method between processors of a parallel computer characterized by performing access. 4. A method of mutual access between processors of a parallel computer according to any one of claims 1 to 3, wherein a shared area is continuously secured in a real memory, and each entry of the area designation table is It has a shared area identifier and a base address and size of an actual memory area corresponding to the shared area, and the response side processor accesses the area designation table by the shared area identifier from the request side processor,
A mutual access method between processors of a parallel computer, characterized in that an actual address is obtained by adding an offset from the requesting processor to the base address of the obtained entry. 5. The inter-processor mutual access method for a parallel computer according to claim 1, wherein the area designation table is provided for each cluster, and the shared area is continuously secured in the real memory. However, each entry of the area designation table has the intra-cluster processor number, the shared area identifier, and the base address and size of the real memory area corresponding to the shared area, and the response side processor is the processor number from the request side processor. A method of mutual access between processors of a parallel computer, characterized in that the real address is obtained by accessing the area designation table with a shared area identifier and adding an offset from the requesting processor to the base address of the obtained entry. . 6. The method of mutual access between processors of a parallel computer according to claim 1, wherein the destination processor number sent by the requesting processor is a logical processor number, and the shared area is It is secured continuously in the real memory, and each entry of the area designation table has a shared area identifier, a logical processor number, and a base address and size of the real memory area corresponding to the shared area. A parallel characterized in that the real address is obtained by accessing the area designation table by the shared area identifier and the logical processor number from the processor and adding the offset from the requesting processor to the base address of the obtained entry. Mutual access method between processors of computer. 7. The inter-processor mutual access method for a parallel computer according to any one of claims 4 to 6, wherein each entry of the area designation table further corresponds to a shared area identifier. A mutual access method between processors of a parallel computer having a count value which is incremented at the time of issue and decremented at the completion of access. 8. The inter-processor mutual access method for a parallel computer according to claim 4, wherein each entry of the area designation table further has an area valid corresponding to a shared area identifier. Flag, read flag,
A mutual access method between processors of a parallel computer characterized by having a write flag. 9. The inter-processor mutual access method for a parallel computer according to claim 1, wherein the partner processor number designated by the requesting processor is a logical processor number, and the partner processor A processor number conversion means for converting a number from a logical processor number to a physical processor number is provided, and the logical processor number is converted to a physical processor number by the means and is sent to a response side processor. how to access. 10. The method of mutual access between processors of a parallel computer according to claim 1, wherein the area designation table is arranged in a main storage device, and an area designation table cache is provided. A method of mutual access between processors of a parallel computer, characterized in that an entry of the area designation table is cached in the area designation table cache.