JPH08293852A - Sync protection system - Google Patents

Abstract

(57) [Summary] [Objective] To provide a synchronization protection system capable of improving synchronization performance. [Configuration] The present invention includes a first synchronization protection circuit 29 and a second synchronization protection circuit 31. The first synchronization protection circuit 29 protects the synchronization at the first synchronization timing, and the second synchronization protection circuit 31 protects the synchronization at the second synchronization timing different from the first synchronization timing. When the correlation of the correlation output signal C synchronized at the second synchronization timing is larger than the correlation of the correlation output signal C synchronized at the first synchronization timing, the second synchronization protection circuit 31 is The second false lock pulse FS is output to the synchronization protection circuit 29, and the first false lock pulse FS is output.
The synchronization protection circuit 29 is returned to the initial state. By competing the first synchronization protection circuit 29 and the second synchronization protection circuit 31, the synchronization performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization protection system in a spread spectrum communication system, and more particularly to a synchronization protection system having a large degree of freedom in design and capable of improving synchronization performance.

[0002]

2. Description of the Related Art In conventional data communication, communication using a narrow band modulation method is generally used. These can realize demodulation in a receiver with a relatively small circuit, but have a drawback that they are weak in an environment with multipath or narrow band colored noise such as indoors (office or factory).

On the other hand, a spread spectrum communication system spreads the spectrum of data by a spread code,
Since it transmits in a wide band, it has an advantage that the drawbacks can be eliminated as described above. In addition, as a feature of the spread spectrum communication system, CDMA (code division multiple access system)
Therefore, many users can communicate using the same frequency.

FIG. 34 is a schematic block diagram showing a configuration of a portion related to synchronization of a receiver of a general spread spectrum communication system as described above.

In FIG. 34, the receiver of the spread spectrum communication system includes a distributor 43, multipliers 45 and 47, correlators 49 and 51, a local signal generator 53, and a square sum circuit 5.
5, including a synchronization protection circuit 57.

In the receiver of a general spread spectrum communication system, the distributor 43 distributes the IF signal into two signals. The multiplier 45 multiplies one distribution signal from the distributor 43 by the cos component from the local signal generator 53, and outputs a baseband in-phase signal (I signal).
The I signal is input to a correlator 49 that can correlate with the spreading code used during transmission.

The multiplier 47 multiplies the other distribution signal from the distributor 43 by the sin component from the local signal generator 53, and outputs a baseband quadrature signal (Q signal). The Q signal is input to a correlator 51 that can correlate with a spreading code used in a transmitter (not shown). Square sum circuit 55
Is the sum of squares of the correlated I correlation signal from the correlator 49 and the correlated Q correlation signal from the correlator 51,
Obtain the absolute value output C of the correlated signal. The synchronization protection circuit 57 synchronizes with the desired wave using the correlation output signal C, which is the absolute value output of the correlated signal from the sum of squares circuit 55, and outputs it as a synchronization pulse.

The synchronization protection circuit 57 of the spread spectrum communication system as described above uses the correlation output signal C from the sum of squares circuit 55 to capture and hold synchronization. in this case,
A synchronization protection circuit similar to the frame synchronization system of a general digital wireless communication system is used. A synchronization protection circuit in a general frame synchronization system is disclosed, for example, in Kimio Tanaka's "Digital Communication Technology" (published by Tokai University Press).

FIG. 35 is a schematic block diagram showing a synchronization protection circuit in a receiver of a conventional spread spectrum communication system, which is similar to the above-described frame synchronization type synchronization protection circuit.

In FIG. 35, the conventional synchronization protection circuit is
Discriminator 1, initial synchronization circuit 3, cycle counter 32, AND
The circuit 33, the false lock counter 35, the logic gate 37, the positive lock counter 39, and the flip-flop circuit 19.

In the conventional synchronization protection circuit shown in FIG. 35, the discriminator 1 compares the correlation output signal C from the sum of squares circuit 55 shown in FIG. 34 with a predetermined threshold value, and the correlation output signal C has a predetermined value. When the threshold value is exceeded, it is considered that the correlation is obtained, and the correlation detection pulse SP is generated. The initial synchronization circuit 3 confirms that the initial synchronization is established by the correlation detection pulse SP, and activates the cycle counter 32.

The AND circuit 33 ANDs the output of the cycle counter 32 and the correlation detection pulse SP from the discriminator 1.
Calculation is performed. When the same chip phase of the spreading code is confirmed, the chip phase synchronization correlation detection pulse CP is output. That is, when both the correlation detection pulse SP and the output from the cycle counter 32 are at "H" level, the AND circuit 33 outputs a "H" level signal. Therefore, when the correlation output signal C exceeds the predetermined threshold value in the discriminator 1, the AND circuit 33 outputs the chip phase synchronization correlation detection pulse CP. The chip phase synchronization correlation detection pulse CP clears the count value of the false lock counter 35 by one count and increments the count value of the positive lock counter 39 by one count.

The logic gate 37 performs an AND operation on the logically inverted correlation detection pulse SP and the output from the cycle counter 32. That is, when the correlation output signal C exceeds the predetermined threshold value in the discriminator 1, the logic gate 37 does not output a signal. When the correlation output signal C does not exceed the predetermined threshold value in the discriminator 1 (when the correlation detection pulse SP is not output from the discriminator 1), the logic gate 37 outputs the chip phase synchronization non-detection pulse. Output NP.

The chip phase synchronization non-detection pulse NP counts up the counter value of the false lock counter 35 one by one and clears the counter value of the positive lock counter 39 one by one. The positive lock counter 39 and the false lock counter 35 overflow when the count number reaches a predetermined target value.

When the false lock counter 35 overflows before the positive lock counter 39, the flip-flop circuit 19 judges that the synchronization is not correct, and outputs the out-of-synchronization signal N. The out-of-sync signal N is the initial synchronization circuit 3,
The false lock counter 35 and the correct lock counter 39 are returned to the initial state.

When the positive lock counter 39 overflows earlier than the false lock counter 35, the flip-flop circuit 19 determines that the synchronization is correct and outputs the synchronization normal signal S. When the positive lock counter 39 continuously overflows earlier than the false lock counter 35, the positive lock counter 39 outputs the synchronization pulse P.

As described above, the conventional synchronization protection circuit protects the synchronization of the correlation output signal C.

Here, the synchronization protection circuit is designed to improve the synchronization performance as described below.

(1) The synchronization time is short, (2) the retention characteristic is good (the synchronization should not be lost at the correct position),
(3) Do not synchronize at the wrong position (disconnect immediately after synchronizing at the wrong position), and (4) immediately return to the synchronized state when the synchronization is removed.

[0020]

The synchronization performance of the conventional synchronization protection circuit of FIG. 35 will be described.

FIG. 36 is a diagram showing an example of the waveform of the correlation output signal C input to the discriminator 1 of FIG.

In FIG. 36, the signal represented by the broken line is
It is an ideal signal, and the signal represented by the solid line is a signal whose level has fluctuated due to noise. The arrow TH indicates the level of a predetermined threshold value in the discriminator 1 in FIG.

FIG. 37 shows the count number and time of the positive lock counter 39 when the ideal correlation output signal and the correlation output signal whose level fluctuates due to noise are input to the synchronization protection circuit of FIG. It is a figure which shows the relationship with. The vertical axis represents the number of counts and the horizontal axis represents time.

The line indicated by the arrow a indicates the number of counts in the positive lock counter 39, assuming that the ideal correlation output signal C shown by the broken line in FIG. 36 is input to the synchronization protection circuit in FIG. . The polygonal line indicated by arrow b is shown in FIG.
36 shows the number of counts in the positive lock counter 39 when the actual correlation output signal C indicated by the solid line 6 is input to the synchronization protection circuit of FIG. That is, since only the signal of B in FIG. 36 exceeds the threshold value TH, the count is incremented and becomes 1 only when the signal of B is input.

As described above, in the conventional synchronization protection circuit of FIG. 35, as shown in FIG. 37, it is assumed that the ideal correlation output signal C is input and the actual correlation output signal C is input. In some cases, the relationship between the count number and time was different from that in the case of being performed. Here, the line indicated by the arrow a is
It is called an ideal count number line, and the polygonal line indicated by b is called an actual count number line.

As described above, in the conventional synchronization protection circuit of FIG. 35, the ideal count number line (a) and the actual count number line (b) are different (threshold value as shown in FIG. 36). Since the signals A, D, and E that do not exceed TH may not be taken into consideration in determining whether or not synchronization is normal), it is necessary to lower the threshold value of the discriminator 1, but when the threshold value is too low. In the case of synchronization at the wrong synchronization position, or when synchronization is made at the wrong position, the synchronization cannot be lost. On the other hand, if the threshold value of the discriminator 1 of the synchronization protection circuit in FIG. 35 is raised too much, the synchronization may be lost even when the synchronization is performed at the correct position.

Therefore, in the conventional synchronization protection circuit, there is a problem that it is not easy to design a synchronization protection circuit which improves the synchronization performance.

Further, when the C / N of the wireless line is poor, the output may decrease even when the correlation output signal C is in the correct phase. Therefore, in the discriminator 1 of the synchronization protection circuit of FIG. 35, the threshold value must be lowered so that the probability that the threshold value will not be exceeded often occurs.
If it is lowered too much, it becomes difficult to lose the synchronization when the synchronization is achieved at the wrong correlation position.

Therefore, in the actual synchronization protection, depending on the C / N used, the optimum value of the threshold value of the discriminator 1 in FIG.
The optimum number of counter stages (predetermined target value for overflow) is determined, but the degree of freedom in setting these is small (actual count line (b) and ideal count line (a) as shown in FIG. 37. ) Is different), and when operation is required over a wide C / N range,
There is a problem that sufficient protection characteristics cannot be obtained.

Further, in the spread spectrum communication system, there is a unique correlation output called autocorrelation, and when it is used for CDMA, due to the cross-correlation with other stations,
Receive constant interference. Therefore, unlike a general frame synchronization circuit, a correlation output of a certain size is constantly generated at the same time timing. As a result, when the synchronization protection circuit of FIG. 35 is used in the spread spectrum communication system, depending on the size of the threshold value of the discriminator 1, the synchronization may not be lost while keeping the synchronization at the wrong position. was there.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a synchronization protection system which has a large degree of freedom in design and can improve synchronization performance.

Another object of the present invention is to provide a synchronization protection system capable of preventing synchronization at an incorrect position with a signal based on autocorrelation or cross-correlation.

[0033]

According to a first aspect of the present invention, there is provided a synchronization protection system which protects synchronization at a first synchronization timing by using a correlation output signal based on a signal from a correlator that correlates a spread code. Using the first synchronization protection means that returns to the initial state in response to the signal and the correlation output signal, the synchronization is protected at the second synchronization timing different from the first synchronization timing,
When the correlation of the correlation output signal synchronized at the second synchronization timing is larger than the correlation of the correlation output signal synchronized at the first synchronization timing in the first synchronization protection means, the first synchronization protection means And a second synchronization protection means for outputting a predetermined signal for returning the signal to the initial state.

According to a second aspect of the present invention, there is provided a synchronization protection system, wherein first synchronization protection means protects synchronization at a first synchronization timing by using a correlation output signal based on a signal from a correlator that correlates with a spread code. Using the correlation output signal, the correlation between the second synchronization protection unit that protects the synchronization at the second synchronization timing different from the first synchronization timing and the correlation between the correlation output signal synchronized at the second synchronization timing is And a timing transition unit for setting the synchronization timing of the first synchronization protection unit to the second synchronization timing when the correlation output signal synchronized with the first synchronization timing is larger than the correlation of the correlation output signal.

According to a third aspect of the present invention, in the synchronization protection system, the correlation output signal based on the signal from the correlator that correlates the spread code is used to protect the synchronization at the first synchronization timing.
Second synchronization protection means for protecting the synchronization at the second synchronization timing different from the first synchronization timing by using the synchronization protection means and the correlation output signal, and the correlation output synchronized at the second synchronization timing. When the correlation of the signals is greater than the correlation of the correlation output signals synchronized at the first synchronization timing in the first synchronization protection means, the first synchronization protection means is returned to the initial state, or the first synchronization And a means for changing the first synchronization timing of the protection means to the second synchronization timing, wherein the first synchronization protection means is such that the correlation of the correlation output signals synchronized at the first synchronization timing is the second synchronization timing. When the protection means is greater than the correlation of the correlation output signals synchronized at the second synchronization timing, it outputs a reset signal for returning the second synchronization protection means to the initial state, and the second synchronization protection means outputs the reset signal. It returns to the initial state by.

In the synchronization protection system according to claim 4, in the synchronization protection system according to any one of claims 1 to 3, the first synchronization protection means uses a correlation output signal satisfying a predetermined condition. , Synchronization acquisition means for performing synchronization acquisition,
The difference between the predetermined reference value and the correlation output signal is obtained, the difference signal output means for outputting the difference signal, and the difference having the first target value and matched with the first synchronization timing captured by the synchronization capturing means. First addition means for sequentially adding signals, and second addition means for sequentially adding correlation output signals having a second target value and having a second target value, and addition values of the first addition means Alternatively, it includes a determining unit that determines whether or not the synchronization is normal depending on whether the first target value or the second target value of any of the added values of the second adding unit is reached earlier.

According to a fifth aspect of the present invention, there is provided the synchronization protection system according to any one of the first to third aspects, wherein the first synchronization protection means uses a correlation output signal satisfying a predetermined condition. Synchronization acquisition means for performing synchronization acquisition,
Addition means for sequentially adding only correlation output signals having a predetermined target value and matched with the first synchronization timing captured by the synchronization acquisition means, and a predetermined target number are provided for the first synchronization timing. The counting means for counting the correlation output signals satisfying the predetermined condition, and the synchronization is normal depending on which of the added value of the adding means and the counted value of the counting means reaches a predetermined target value or a predetermined target number earlier. And a determination means for determining whether or not

According to a sixth aspect of the present invention, there is provided the synchronization protection system according to any one of the first to third aspects, wherein the first synchronization protection means uses a correlation output signal satisfying a predetermined condition. Synchronization acquisition means for performing synchronization acquisition,
A difference signal output means for obtaining a difference between a predetermined reference value and the correlation output signal and outputting the difference signal, and a difference signal having a predetermined target value and matched with the first synchronization timing captured by the synchronization capturing means. And a predetermined target number,
Counting means for counting correlation output signals satisfying a predetermined condition matching the first synchronization timing, and either the added value of the adding means or the counted value of the counting means reaches a predetermined target value or a predetermined target number earlier. And a determining means for determining whether or not the synchronization is normal depending on the arrival.

In the synchronization protection system according to claim 7, in the synchronization protection system according to any one of claims 1 to 3, the second synchronization protection means uses a correlation output signal satisfying a predetermined condition. A synchronization acquisition means for performing synchronization acquisition, a difference signal output means for obtaining a difference between a predetermined reference value and a correlation output signal, and outputting a difference signal, and a first target value,
First addition means for sequentially adding the difference signals matched with the second synchronization timing captured by the synchronization acquisition means, and correlation output signals having a second target value and matched with the second synchronization timing, Whether the synchronization is normal or not depends on the second addition means to be added and whether the addition value of the first addition means or the addition value of the second addition means reaches the first target value or the second target value earlier. And a determination means for determining whether or not.

The synchronization protection system of claim 8 is the synchronization protection system of claim 1.
In the synchronization protection system according to any one of 1 to 3, the second synchronization protection means has a synchronization acquisition means for performing synchronization acquisition using a correlation output signal satisfying a predetermined condition and a predetermined target value. Then, it has an adding means for sequentially adding the correlation output signals matched with the second synchronization timing captured by the synchronization capturing means, and a predetermined target number, and satisfies a predetermined condition suitable for the second synchronization timing. Whether the synchronization is normal or not is determined by the counting means for counting the correlation output signal and whether the addition value of the addition means or the count value of the counting means reaches a predetermined target value or a predetermined target number earlier. And a determining means for performing.

According to a ninth aspect of the present invention, there is provided the synchronization protection system according to any one of the first to third aspects, wherein the second synchronization protection means uses a correlation output signal satisfying a predetermined condition. Synchronization acquisition means for performing synchronization acquisition,
A difference signal output means for obtaining a difference between a predetermined reference value and the correlation output signal, and a difference signal output means for outputting the difference signal, and a difference signal having a predetermined target value and matched with the second synchronization timing captured by the synchronization capturing means. Are sequentially added, counting means for counting correlation output signals having a predetermined target number and satisfying a predetermined condition matching the second synchronization timing, and an addition value of the addition means or And a judgment means for judging whether or not the synchronization is normal, depending on whether a predetermined target value or a predetermined target number of the count values of the counting means is reached earlier.

A synchronization protection system according to a tenth aspect is the synchronization protection system according to the third aspect, wherein the second synchronization protection means uses a correlation output signal satisfying a predetermined condition to perform synchronization acquisition. Means, an adding means for sequentially adding the correlation output signals captured by the synchronization capturing means in accordance with the second synchronization timing, and a determining means for determining whether or not the synchronization is normal from the added value of the adding means. Including.

According to an eleventh aspect of the synchronization protection system of the fourth aspect, the first synchronization protection means sets an arbitrary time width, and outputs the difference signal and the correlation output signal of the set time width. Each further includes time width setting means for outputting to the first adding means and the second adding means.

According to a twelfth aspect of the synchronization protection system of the fifth aspect, there is further provided a time width setting means for setting an arbitrary time width and outputting a correlation output signal having the set time width to the adding means. Prepare

In the synchronization protection system of claim 13, in the synchronization protection system of claim 6, the first synchronization protection means sets an arbitrary time width and outputs a difference signal of the set time width to the addition means. It further comprises a time width setting means.

In the synchronization protection system of claim 14, in the synchronization protection system of claim 7, the second synchronization protection means sets an arbitrary time width and the difference signal and the correlation output signal are set at the set time width. Each further comprises time width setting means for outputting to the first adding means and the second adding means.

According to a fifteenth aspect of the synchronization protection system of the eighth or tenth aspect, the second synchronization protection means sets an arbitrary time width, and the correlation output signal is set at the set time width. And a time width setting means for outputting to the addition means.

According to a sixteenth aspect of the synchronization protection system of the ninth aspect, in the ninth aspect, the second synchronization protection means sets an arbitrary time width and outputs the difference signal to the addition means in the set time width. It further comprises a time width setting means.

In the synchronization protection system according to claim 17, in addition to the configuration of the synchronization protection system according to any one of claims 11 to 13, the time width setting means is a first of the arbitrary time widths. The later time width is made wider than the previous time width with respect to the peak timing of the correlation output signal that matches the synchronization timing.

In the synchronization protection system according to claim 18, in the synchronization protection system according to any one of claims 11 to 13, the first synchronization protection means integrates the correlation output signal in an arbitrary time width. It further comprises adjusting means for adjusting the time width setting means so as to maximize.

According to a nineteenth aspect of the synchronization protection system of the present invention, in addition to the configuration of the synchronization protection system according to any one of the fourteenth to sixteenth aspects, the time width setting means has a second time period among the predetermined time widths. The later time width is made wider than the previous time width with respect to the peak timing of the correlation output signal that matches the synchronization timing.

The synchronization protection system of claim 20 is the synchronization protection system according to any one of claims 14 to 16, wherein the second synchronization protection means integrates the correlation output signal in an arbitrary time width. It further comprises adjusting means for adjusting the time width setting means so as to maximize the time width setting means.

[0053]

In the synchronization protection system of claim 1, the second
When the correlation of the correlation output signal synchronized at the second synchronization timing is larger than the correlation of the correlation output signal synchronized at the first synchronization timing in the first synchronization protection means, , The first synchronization protection means returns to the initial state and resynchronizes.

In the synchronization protection system of claim 2,
In the second synchronization protection means, the correlation of the correlation output signal synchronized at the second synchronization timing is larger than the correlation of the correlation output signal synchronized at the first synchronization timing in the first synchronization protection means. In this case, since the first synchronization timing in the first synchronization protection means is set to the second synchronization timing, the time required for the initial synchronization in the first synchronization protection means can be shortened.

In the synchronization protection system of claim 3,
In the second synchronization protection means, the correlation of the correlation output signal synchronized at the second synchronization timing is larger than the correlation of the correlation output signal synchronized at the first synchronization timing in the first synchronization protection means. In this case, the first synchronization protection means returns to the initial state and resynchronizes. Alternatively, claim 3
In the synchronization protection system, the correlation of the correlation output signal synchronized at the second synchronization timing in the second synchronization protection means is synchronized at the first synchronization timing in the first synchronization protection means. When the correlation is larger than the correlation of the correlation output signal, the first synchronization timing in the first synchronization protection means is set to the second synchronization timing, so that the time required for initial synchronization in the first synchronization protection means can be shortened. . Further, in the synchronization protection system according to claim 3, the correlation of the correlation output signals synchronized at the first synchronization timing in the first synchronization protection means is the second synchronization timing in the second synchronization protection means. Since the second synchronization protection means returns to the initial state when the correlation is larger than the correlation of the correlation output signals synchronized with each other, it is not necessary to provide the second synchronization protection means with a means for removing synchronization.

In the synchronization protection system of claim 4,
The first synchronization protection means sequentially adds the difference signal and the correlation output signal, which are the difference between the predetermined reference value and the correlation output signal, which match the first synchronization timing captured by the synchronization capturing means. However, when the added value of the difference signal reaches the first target value in the first addition means earlier than the added value of the correlation output signal, it is determined that the synchronization is lost, and the added value of the correlation output signal When the second target value in the second adding means is reached earlier, it is determined that the synchronization is normal, and therefore the first
The actual added value in the adding means and the second adding means is
It is an approximation of the added value when the ideal difference signal having no level fluctuation due to noise and the correlation output signal are input.

In the synchronization protection system of claim 5,
The first synchronization protection means sequentially adds the correlation output signals that match the first synchronization timing captured by the synchronization capturing means, and simultaneously counts the correlation output signals that match the first synchronization timing. When the predetermined target value in the adding means is reached earlier than the count value, it is determined that the synchronization is normal, and when the count value reaches the predetermined target number in the counting means earlier, it is determined that the synchronization is lost. Therefore, the actual added value in the adding means is approximate to the ideal added value when a correlation output signal having no level fluctuation due to noise is input.

In the synchronization protection system of claim 6,
The first synchronization protection means sequentially adds a difference signal, which is a difference between a predetermined reference value and a correlation output signal, which is matched with the first synchronization timing captured by the synchronization capturing means, and at the same time, is correlated with the synchronization timing. The output signals are counted, and when the added value of the difference signal reaches the predetermined target value in the adding means earlier than the count value, it is determined that the synchronization is lost, and the count value is early and the predetermined target number in the counting means is reached. When it reaches, it is determined that the synchronization is normal, and therefore the actual addition value in the adding means is approximated to the ideal addition value when the correlation output signal without level fluctuation due to noise is input. Become.

In the synchronization protection system of claim 7,
The second synchronization protection unit sequentially adds the difference signal and the correlation output signal, which are the difference between the predetermined reference value and the correlation output signal, which are in synchronization with the synchronization timing captured by the synchronization capturing unit, to obtain the difference. When the added value of the signal is faster than the added value of the correlation output signal and reaches the first target value in the first adding means, it is determined that the synchronization is lost, and the added value of the correlation output signal is faster. When the second target value in the second adding means is reached, it is determined that the synchronization is normal. Therefore, the actual added value in the first adding means and the second adding means is an ideal level fluctuation due to noise. It is an approximation of the added value when the difference signal without correlation and the correlation output signal are input.

In the synchronization protection system of claim 8,
The second synchronization protection means sequentially adds the correlation output signals that match the second synchronization timing captured by the synchronization capturing means, and simultaneously counts the correlation output signals that match the second synchronization timing. When the predetermined target value in the adding means is reached earlier than the count value, it is determined that the synchronization is normal, and when the count value reaches the predetermined target number in the counting means earlier, it is determined that the synchronization is lost. Therefore, the actual added value in the adding means is approximate to the ideal added value when a correlation output signal having no level fluctuation due to noise is input.

In the synchronization protection system of claim 9,
The second synchronization protection means sequentially adds the difference signals, which are the difference between the predetermined reference value and the correlation output signal, that match the second synchronization timing captured by the synchronization capturing means, and at the same time, the second synchronization protection means
When the added value of the difference signal is faster than the count value and reaches the predetermined target value in the adding means, it is determined that the synchronization is out of sync, and the count value is fast. When the predetermined target number in the counting means is reached, it is determined that the synchronization is normal, and therefore the actual added value in the adding means is an ideal added value of the difference signal in which the level does not change due to the noise level. It will be an approximation.

In the synchronization protection system of the tenth aspect, the second synchronization protection means sequentially adds the correlation output signals that match the second synchronization timing captured by the synchronization capture means, and the added value is When the predetermined target value in the adding means is reached, it is determined that the synchronization is out of sync. Therefore, the actual added value in the adding means is an ideal correlation output signal without level fluctuation due to noise level. It is similar to the added value in the case.

In the synchronization protection system of the eleventh aspect, since the first synchronization protection means adds the difference signal and the correlation output signal with arbitrary time widths, the addition can be made strong against multipath.

In the synchronization protection system of the twelfth aspect, since the first synchronization protection means adds the correlation output signals with an arbitrary time width, the multipath can be strengthened.

In the synchronization protection system of the thirteenth aspect, since the first synchronization protection means adds the difference signal with an arbitrary time width, it is possible to strengthen multipath.

In the synchronization protection system of the fourteenth aspect, since the second synchronization protection means adds the difference signal and the correlation output signal with arbitrary time widths, it is possible to strengthen the multipath.

In the synchronization protection system of the fifteenth aspect, since the second synchronization protection means adds the correlation output signals with an arbitrary time width, the multipath can be strengthened.

In the synchronization protection system of the sixteenth aspect, since the second synchronization protection means adds the difference signal with an arbitrary time width, it is possible to strengthen the multipath.

According to another aspect of the synchronization protection system of the present invention, in the first synchronization protection means, an arbitrary time width of the difference signal and the correlation output signal is compared with a peak timing of the correlation output signal, and a later time width is compared with the peak timing of the correlation output signal. Since the width is wider than the time width, even when the correlation output signal spreads backward in time, synchronization can be achieved at the maximum received power.

In the synchronization protection system of the eighteenth aspect, the first synchronization protection means adjusts the time width setting means so that the integral of the correlation output signal is maximized, so that the effect of PDI can be improved. .

In the synchronization protection system of claim 19, in the second synchronization protection means, an arbitrary time width of the correlation output signal is set to a peak timing of the correlation output signal, and a later time width is set to be shorter than the previous time width. Even if the correlation output signal spreads backward in time for widening, synchronization can be achieved at the maximum received power.

In the synchronization protection system of the twentieth aspect, the second synchronization protection means adjusts the time width setting means so that the integral of the correlation output signal is maximized, so that the effect of PDI can be improved. .

[0073]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sync protection circuit and a sync protection system according to the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic block diagram showing a synchronization protection circuit according to the first embodiment of the present invention.

In FIG. 1, the sync protection circuit according to the first embodiment comprises a discriminator 1, an initial sync circuit 3, a sync counter 5, a difference signal output circuit 7, a first gate 9 and a first adder 1.
1, a second gate 13, a second adder 15, an OR circuit 17, and a flip-flop circuit 19.

The synchronization protection circuit according to the first embodiment can also be used in the receiver of the general spread spectrum communication system of FIG. 34 described in the section of the prior art. Therefore, a case where the synchronization protection circuit according to the first embodiment is used as the synchronization protection circuit 57 of the receiver of the spread spectrum communication system of FIG. 34 will be described.

The correlation output signal C is input from the square sum circuit 55 of the receiver of the general spread spectrum communication system of FIG. 34 to the synchronization protection circuit according to the first embodiment. The correlation output signal C is sent at a constant cycle, but a noise component signal may occur.

Here, the synchronization protection means that when demodulating the received spread spectrum signal, the correlation is detected in order to correctly demodulate the data with respect to the peak position (correct chip phase) of the correlation output signal C of the receiver. It refers to protecting timing synchronization.

FIG. 2 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection circuit of FIG.

In FIG. 2, the correlation output signal C includes the maximum correlation signal a (the signal to be synchronized) having the maximum correlation and the noise component signal b. The maximum correlation signal a is transmitted in the cycle t.

The correlation output signal C is input to the discriminator 1 of the synchronization protection circuit of FIG. 1 in order to prevent erroneous synchronization due to the noise component signal b. That is, the discriminator 1 of FIG. 1 inputs only the signal in which the output level of the correlation output signal C exceeds the threshold value TH to the initial synchronizing circuit 3 of FIG.
Therefore, only the maximum correlation signal a is input to the initial synchronizing circuit 3.

Here, the threshold value TH is the correlation output signal C
Since the level is set to such an extent that it can be discriminated whether or not it is the maximum correlation signal a, the maximum number of the maximum correlation signal a is input to the initial synchronizing circuit 3.

When a fixed number (for example, three) of the maximum correlation signals a are continuously input to the initial synchronizing circuit 3 and it is confirmed that the synchronization is achieved, the synchronizing counter 5 is started. After that, the synchronization counter 5 automatically outputs a signal (hereinafter, referred to as "synchronization counter output signal SC") which is synchronized with the synchronization timing of the maximum correlation signal a.

The threshold value TH in the discriminator 1 is set according to the desired synchronization performance (the synchronization performance described in the section of the prior art). The synchronization counter output signal SC output from the synchronization counter 5 is supplied to the first gate 9 and the second gate 9.
Although input to the gate 13, the first gate 9 and the second gate 13 open when the synchronous counter output signal SC is input. That is, the first gate 9 and the second gate 13 are opened at the same timing as the synchronization timing of the signal (the maximum correlation signal a in FIG. 2) that exceeds the threshold value TH. That is, if the initial synchronization is performed at the correct position, the first gate 9 and the second gate 1 in FIG.
3 is turned on every spreading code period.

FIG. 3 is a diagram showing the timing at which the first gate 9 and the second gate 13 of FIG. 1 are turned on / off for each spreading code period.

In FIG. 3, t represents a spread code period. As shown in FIG. 3, upon initial synchronization, the first gate 9
And, the second gate 13 is repeatedly turned on and off every spreading code period t. When the correlation output signals C exceeding the threshold value TH are not continuously input, it is measured that a fixed number of correlation output signals C are continuously input again.

The difference signal D from the difference signal output circuit 7 is input to the first gate 9 of FIG. Second gate 13 of FIG.
The correlation output signal C is input to. Where the difference signal D
Is a difference between a predetermined reference value and the amplitude length of the correlation output signal C, which is obtained by the difference signal output circuit 7.

FIG. 4 is a diagram showing the waveforms of the correlation output signal C and the difference signal D. FIG. 4A shows a correlation output signal C
(B) shows the difference signal D. The difference signal D shown in (b) is the difference between the amplitude length of the correlation output signal C shown in (a) and the predetermined reference value B.

FIG. 5 is a diagram for explaining the predetermined reference value B of FIG. The amplitude length of the correlation output signal C fluctuates due to noise components, but the predetermined reference value B in FIG. 3 is set to a value exceeding the upper limit of the fluctuation range (indicated by f) of the amplitude length of the correlation output signal C. To be done. Here, the predetermined reference value B is
Set to obtain optimum synchronization performance, C / N, required BE
Select by R.

The required BER means an error rate for obtaining a target communication quality. For example, at least 10 ^-3 is required for voice, and 10 ^-5 is required for data. The required BER depends on the system.

Now, returning to FIG. 1, description will be made. It is assumed that the correlation output signal C shown in FIG. 2 is input. First, when synchronizing at the correct position, that is, the correlation maximum signal a in the correlation output signal C as shown in FIG.
The case of inputting in 3 will be described.

The difference signal D from the difference signal output circuit 7 is input to the first adder 11 by the first gate 9 only at the synchronization timing. On the other hand, the correlation output signal C is the second gate 13
Therefore, it is input to the second adder 15 only at the synchronization timing. Therefore, the first adder 11 and the second adder 15
2 does not receive the noise component signal b included in the correlation output signal C as shown in FIG.

In the second adder 15, the correlation output signal C (correlation maximum signal a) exceeding the threshold TH as shown in FIG.
Are sequentially added, the addition amount reaches a predetermined target value and the second adder 15 immediately overflows. And the second
The adder 15 outputs a set signal to the flip-flop circuit 19, the flip-flop circuit 19 determines that the synchronization is normal, and outputs the synchronization normal signal S. At this time, the set signal is input to the OR circuit 17, and the OR circuit 17
The first adder 11 and the second adder 15 are reset.

If the synchronization is normal continuously, the second
The synchronizing pulse P is output from the adder 15.
That is, when the second adder 15 outputs the set signal, the “H” level signal is output, and when the second adder 15 is reset by the OR circuit 17, the “L” level signal is output. If the synchronization is normal, it becomes a pulse signal.

On the other hand, in the first adder 11, the difference signal D components are sequentially added, and the difference signal D is the difference component signal between the maximum correlation signal a as shown in FIG. 2 and the predetermined reference value. In this case, the first adder 11 does not overflow before the second adder 15 and does not output the reset signal to the flip-flop circuit 19. First adder 11
Overflows when the addition amount reaches a predetermined target value.

The predetermined reference value B as shown in FIG. 4 for obtaining the difference signal is, for example, the difference (difference signal D) from the correlation maximum signal a as shown in FIG. Set so that it is smaller than the amplitude length. Generally speaking,
The predetermined reference value B is set so that the difference signal D is smaller than the signal to be synchronized (the signal having the maximum correlation) in the correlation output signal C. FIG. 6 is a diagram showing the relationship between the signals input to each of the first adder 11 and the second adder 15 of FIG. 1 and the amount of addition thereof.

FIG. 6 (a) shows the waveform of the correlation output signal C input to the second gate 13 of FIG. FIG.6 (b) is
The waveform of the difference signal input to the first gate 9 is conceptually shown. FIG. 6C shows the sync counter output signal CS from the sync counter 5 of FIG. FIG. 6D is the correlation output signal C shown in FIG. 6A that has passed through the second gate 13. FIG. 6E shows the difference signal D shown in FIG. 6B that has passed through the first gate 9. FIG. 6F shows the addition amount of the signal shown in (d) in the second adder 15. FIG. 6G shows the amount of addition of the signal shown in (e) in the first adder 11.

As shown in FIG. 6, when the correlation output signal C is larger than the difference signal D (a) and (b), the second adder 15
Is larger than the addition amount of the first adder 11.
Therefore, if they are synchronized in the correct position, the second
The adder 15 will overflow earlier than the first adder 11.

Next, description will be given of the case where the synchronization is made at an incorrect position, that is, the case where the noise component signal b as shown in FIG. 2 is input to the second gate 13. That is, the synchronous counter output signal SC from the synchronous counter 5
2 and the timing of the correlation maximum signal a (signal to be synchronized) as shown in FIG. 2 are deviated.

Difference signals larger than the noise component signal are sequentially input to the first adder 11. On the other hand, a noise component signal smaller than the difference signal is input to the second adder 15 many times. At this time, the first adder 11 overflows earlier than the second adder 15 and outputs a reset signal, the flip-flop circuit 19 judges that the synchronization is not normal, and outputs the out-of-synchronization signal N. When the reset signal from the first adder 11 is input to the NOR circuit 17, the NOR circuit 17 resets the first adder 11 and the second adder 15. The out-of-sync signal N is
Initial synchronization circuit 3, first adder 11 and second adder 15
Reset.

Here, although the synchronization is in a normal state, when the correlation output signal C including the error signal is input to the synchronization protection circuit, a large difference signal based on the error signal generated at the synchronization timing is generated by the first gate 9. May be input to the first adder 11. At this time, the first adder 11 adds a large difference signal component.

However, in such an accidental malfunction,
Since it is rare that a large difference signal component is continuously input to the first adder 11, the first adder 11 overflows before the second adder 15 to output the reset signal, and the flip-flop circuit 19 Does not output the out-of-sync signal N.

In an actual communication device, the normal synchronization signal S, the out-of-synchronization signal N and the synchronization pulse P are used for monitoring during demodulation. For example, when the synchronization normal signal S is output, the standard is that the data is correct. On the contrary, when the out-of-sync signal N is output, it means that some demodulated data is erroneous. In this way, transmission / reception is controlled using the normal synchronization signal S and the out-of-synchronization signal N. In terms of appearance, the reception indicator can be turned on by connecting it to an LED or the like. The synchronizing pulse P is also used for such a purpose, but since it has a pulse shape, it becomes easy to control other circuits such as a data demodulating circuit. Generally, a signal that is always at "H" level
The pulsed form is easier to use as a signal.

Now, the relationship between the addition amount of the correlation output signal C added by the second adder 15 and time will be described.

FIG. 7 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection circuit of FIG.

In FIG. 7, only the signal having the maximum correlation (the signal to be synchronized) among the correlation output signals C is shown, and the noise component signal is not shown. The signal shown by the broken line shows an ideal signal without level fluctuation due to noise, and the signal shown by the solid line is a signal whose level changes due to noise. That is, a signal whose level fluctuates due to noise as shown by the solid line is input to the actual synchronization protection circuit. Since synchronization is achieved at the correct position, the second gate 13 of FIG. 1 is opened at the position indicated by arrow G, and the second adder 15 sequentially adds the values of the correlation output signal C at the gate position G. To do.

FIG. 8 shows the second adder 15 when the correlation output signal C shown in FIG. 5 is input to the second gate 13 of FIG.
It is a figure which shows the relationship between the addition amount and time in. The vertical axis represents the amount of addition and the horizontal axis represents time.

In FIG. 8, the addition amount shown by the arrow a indicates the case where the ideal correlation output signal C as shown by the broken line in FIG. 7 is input to the second gate 13. The addition amount shown by the arrow b indicates the case where the correlation output signal C having a level fluctuation due to noise as shown by the solid line in FIG. 5 is input to the second gate 13.

Since the correlation output signal C actually input to the synchronization protection circuit of FIG. 1 varies in level due to noise,
The amount of addition is a polygonal line as shown by arrow b. However, the average is close to a line representing an ideal addition amount of the correlation output signal C without the level fluctuation due to noise shown by the arrow a. Here, if the line representing the addition amount shown by the arrow a is called an ideal addition amount line and the line representing the addition amount shown by the arrow b is called an actual addition amount line, the actual addition amount line b is It can be said that they converge to the ideal addition amount line a. this is,
Generally, this is because the correlated output signal from the correlator of the synchronization protection system has a constant value when viewed statistically for a long time. The integrated noise converges to zero. The same applies to the case where the difference signal D is input to the first gate 9 in FIG.

On the other hand, in the conventional synchronization protection circuit of FIG.
When the correlation output signal C shown in FIG. 36 is input,
The relationship between the count number of the positive lock counter 39 and time is as shown in FIG. That is, the ideal count number line a (when the correlation output signal C shown by the broken line in FIG. 36 is input) and the actual count number line b (FIG. 36).
When the correlation output signal C whose level is changed due to noise is input).

Using these results, the reason why the synchronization protection circuit according to the first embodiment can improve the synchronization performance described in the prior art will be described in detail. In the conventional synchronization protection circuit of FIG. 35, the initial synchronization circuit 3, AN
The D circuit 33 and the logic gate 37 share the discriminator 1. Therefore, since the correlation output signal C exceeding the same threshold value is input to the initial synchronization circuit 3, the AND circuit 33, and the logic gate 37, the threshold value cannot be increased in the discriminator 1. That is, as shown in FIG. 37, since the ideal count number line is deviated from the actual count number line, the threshold value is set with a margin, that is, the discriminator 1 in FIG. It is necessary to set a small value.

Correlation output signal C as shown by the solid line in FIG.
Is input to the synchronization protection circuit of FIG. 35, if the threshold value TH of the discriminator 1 is increased, the signal A of FIG.
This is because D and E are not input to the AND circuit 33 and the logic gate 37, and only the signal B is input.
That is, in the conventional synchronization protection circuit shown in FIG. 35, it is determined whether synchronization is normal or not depending on whether the correlation output signal C exceeds the threshold value TH of the discriminator 1 (discriminator 1).
The number of correlation output signals C that exceed the threshold value TH at is determined whether or not the synchronization is normal).

Since the threshold value is set small, in the conventional synchronization protection circuit as shown in FIG. 35, it is probabilistically more likely to hold the synchronization at the wrong position. That is,
Sync time (the time from starting sync capture to syncing at the wrong position, then unsyncing, then starting sync capture to syncing at the correct position) starts sync capture Immediately (without having to keep sync in the wrong position) it will take longer than the sync time to sync in the correct position.

However, in the synchronization protection circuit according to the first embodiment, as shown in FIG. 8, since the ideal addition amount line a and the actual addition amount line b are close to each other, the conventional Instead of determining whether the synchronization is normal by checking whether the correlation output signal C exceeds the threshold value,
Whether the synchronization is correct is determined based on the addition amounts of the difference signal D and the correlation output signal C in the first adder 11 and the second adder 15. In addition, like a conventional synchronization protection circuit,
The signals A, D, and E that do not exceed the threshold value TH shown in FIG. 36 are not considered in the determination as to whether the synchronization is normal.

As a result, in the first embodiment, the discriminator 1 of FIG. 1 can be used only for pulling in the synchronization, and its threshold value can be increased, so that the synchronization can be performed at the wrong position. Less. Further, in the first embodiment, FIG.
As shown in, the ideal addition amount line a and the actual addition amount line b
The time taken to lose synchronization is shortened due to the fact that is close to.

From the above, the threshold value for the correlation output signal C input to the initial synchronization circuit 3 and the correlation input to the AND circuit 33 and the logic gate 37 in the conventional synchronization protection circuit of FIG. The synchronization time can also be shortened by changing the threshold value for the output signal C. That is, the synchronization time can also be shortened by increasing the threshold value for the initial synchronization circuit 3 and decreasing the threshold values for the AND circuit 33 and the logic gate 37.

Further, as described above, in the conventional synchronization protection circuit of FIG. 35, if the threshold value is set with a margin, that is, the threshold value is set to be small, synchronization or erroneous position may occur. If you synchronize at the correct position, you cannot cancel the synchronization, so you cannot decrease the threshold too much. I will end up. That is, in the conventional synchronization protection circuit shown in FIG. 36, if the threshold value is increased, the synchronization holding characteristic deteriorates.

However, in the synchronization protection circuit of the first embodiment, whether the synchronization is normal or not depends on the addition amount of the difference signal D and the correlation output signal C in the first adder 11 and the second adder 15 of FIG. Since the ideal addition amount line a and the actual addition amount line b are approximate to each other as shown in FIG. 8, such a problem does not occur and the retention characteristic is not deteriorated. Does not happen.

Further, in the conventional synchronization protection circuit shown in FIG. 35, if the threshold value is set with a margin, that is, if the threshold value is made small, the synchronization cannot be removed when the synchronization is made at the wrong position. That is, synchronization is maintained at the wrong position. However, in the synchronization protection circuit according to the first embodiment, it is determined whether synchronization is normal by the addition amount of the difference signal D and the correlation output signal C in the first adder 11 and the second adder 15 of FIG. As shown in FIG. 8, since the ideal addition amount line a and the actual addition amount line b are close to each other,
The first adder 11 and the second adder in the synchronization protection circuit of FIG.
A predetermined target value at which the adder 15 overflows can be set in small increments, and even if synchronization is made at an incorrect position, the synchronization can be immediately released.

For the same reason as above, the synchronization recovery time can be shortened in the first embodiment.

Generally, in the conventional synchronization protection circuit, if the threshold value is increased, the synchronization time is delayed, or even if the synchronization is performed at the correct position, the synchronization is lost. On the other hand, if the threshold value is made small, there is a drawback that it becomes difficult for the synchronization to be lost when the synchronization is made at the wrong position.

Therefore, with this trade-off, the threshold value and the false lock counter 35 of the conventional synchronization protection circuit of FIG.
And a predetermined target value at which the positive lock counter 39 overflows is determined.

However, in the conventional synchronization protection circuit, as shown in FIG. 8, when the difference between the ideal count number line and the actual count number line is large, the defect and the threshold value when the threshold value is increased It is difficult to set a small threshold value that can overcome the drawbacks in the case of reducing the value of, and to set a predetermined target value at which the false lock counter 35 and the positive lock counter 39 overflow.

On the other hand, in the synchronization protection circuit of the first embodiment of the present invention, as shown in FIG.
And the actual addition amount line b are close to each other, a threshold value of the discriminator 1 of FIG. 1, a predetermined target value at which the first adder 11 overflows, and a predetermined target value at which the second adder 15 overflows. You can set the value in small increments. That is, the degree of freedom in designing the synchronization protection circuit increases.

As a result, in the synchronization protection circuit of the first embodiment of the present invention, the synchronization performance can be improved and the optimum design according to the product used can be realized. Furthermore, in the synchronization protection circuit of the first embodiment,
Wide C / N due to increased design freedom
The synchronization protection performance is improved even under the conditions, and the stable operation is performed under various circumstances. Next, a modification of the synchronization protection circuit according to the first embodiment shown in FIG. 1 will be described.

In an actual communication path, the correlation output can be observed by spreading over several chips in time due to the change in the path and the multipath.

FIG. 9 is a diagram showing the waveform of a multipath signal. As shown in FIG. 9, the reason why a multipath signal that spreads over several chips in time is generated is that the receiver receives a reflected wave due to the multipath, but in the spread spectrum technology, a technology called PDI or rake is used. Then, these reflected waves can be used for demodulation. Therefore, it is effective to operate the synchronization protection circuit shown in FIG. 1 with the opening widths of the first gate 9 and the second gate 13 widened by several chips in consideration of these points.

When PDI or the like is performed, the effect of PDI varies depending on whether the time width for integration (hereinafter referred to as "window") is set to any of A, B, and C in FIG.

FIG. 10 is a schematic block diagram showing a modification of the synchronization protection circuit according to the first embodiment shown in FIG. 1 which can effectively deal with multipath signals.

The synchronization protection circuit according to the modification of the first embodiment shown in FIG. 10 includes a gate width determination circuit 26 and a gate width control circuit 27 in the configuration of the synchronization protection circuit according to the first embodiment shown in FIG. It was added. The gate width determination circuit 26 is connected to the demodulation circuit 28.

The PDI and rake in the demodulation circuit 28 are
The window is determined based on the synchronization timing of the synchronization protection circuit. This window is determined so that the integral at PDI or rake is maximized. Further, the peak timing of the correlation output signal C can be expanded by several chips before and after the same width.

When there are multipaths, the direct wave has the highest amplitude level and the reflected wave has the smallest amplitude level.
It becomes a signal that spreads backward with respect to the peak timing of the correlation output signal C (multipath signal). Therefore, the window in the demodulation circuit 28 is also the correlation output signal C.
The number of chips behind the peak timing can be set larger than the number of previous chips.

As described above, the gate width determination circuit 26 determines the gate width (opening width) of the first gate 9 and the second gate 13 based on the window information determined by the demodulation circuit 28. It outputs a gate width determination signal to the gate width control circuit 27. Gate width control circuit 27
Controls the gate widths of the first gate 9 and the second gate 13 based on this gate width determination signal. That is, the first
The gate widths of the gate 9 and the second gate 13 are controlled so that the PDI and rake integration of the demodulation circuit 28 becomes maximum.

Further, a certain width is provided before and after the peak timing of the correlation output signal C by several chips, or the number of chips behind the peak timing of the correlation output signal C is made larger than the number of previous chips. You can also

From the above, in the synchronization protection circuit according to the modification of the first embodiment, the gate width of the first gate 9 and the second gate 13 of FIG. 10 can be controlled. Therefore, the modification of the first embodiment can improve the effects of PDI and rake in the synchronization protection circuit.

Further, in the synchronization protection circuit according to the modification of the first embodiment, it is possible to quickly respond to a sudden change at the time of passing, and it is possible to stably perform the synchronization protection. Further, in the synchronization protection circuit according to the modification of the first embodiment, it is possible to achieve synchronization at the point where the reception power of the multipath signal becomes maximum, and it is possible to make it suitable for the synchronization protection system.

(Second Embodiment) FIG. 11 shows a second embodiment of the present invention.
3 is a schematic block diagram showing a synchronization protection circuit according to the embodiment of FIG.

The synchronization protection circuit according to the second embodiment can also be used in the receiver of the general spread spectrum communication system of FIG. 34 described in the section of the prior art. Therefore, a case where the synchronization protection circuit according to the second embodiment is used as the synchronization protection circuit 57 of the receiver of the spread spectrum communication system of FIG. 34 will be described.

In FIG. 11, the synchronization protection circuit according to the second embodiment of the present invention comprises a discriminator 1, an initial synchronization circuit 3, a synchronization counter 5, a protection counter 21, a gate 23, and an adder 2.
5, an OR circuit 17 and a flip-flop circuit 19.

Here, the operations of the discriminator 1, the initial synchronization circuit 3, the synchronization counter 5, the OR circuit 17, and the flip-flop circuit 19 are the same as those of the discriminator 1 of the synchronization protection circuit according to the first embodiment shown in FIG. Initial synchronization circuit 3, synchronization counter 5,
The operation is the same as that of the OR circuit 17 and the flip-flop circuit 19. The operation of the gate 23 and the adder 25 of the synchronization protection circuit according to the second embodiment is the same as that of the second gate 13 of the synchronization protection circuit according to the first embodiment shown in FIG.
The operation is the same as that of the second adder 15. Therefore, the operation of the other parts, focusing on the operation of the protection counter 21, will be briefly described.

In the discriminator 1, when a fixed number of correlation output signals C exceeding a predetermined threshold value TH are continuously input,
The initial synchronization circuit 3 operates, and the synchronization counter 5 outputs a signal (hereinafter, referred to as “synchronization counter output signal SC”) synchronized with the synchronization timing of the correlation output signal C exceeding the threshold value. Sync counter output signal SC from sync counter 5
As a result, the gate 23 opens at the synchronization timing.

Then, the correlation output signal C matching the synchronization timing is input to the adder 25 and added sequentially. On the other hand, the protection counter 21 counts the sync counter output signal SC from the sync counter 5. That is, each time the gate 23 is opened once, the protection counter 21 counts up by one.

Here, when the addition amount of the adder 25 reaches a predetermined target value and overflows before the count number (count amount) in the protection counter 21 reaches the predetermined target number and overflows, 25 outputs a set signal, and the flip-flop circuit 19 judges that they are synchronized at the correct position and outputs a synchronization control signal S. The set signal is input to the OR circuit 17, and the OR circuit 17
The adder 25 and the protection counter 21 are reset.

On the other hand, when the count number of the protection counter 21 reaches the predetermined target number and overflows before the addition amount of the adder 25 reaches the predetermined target value and overflows, the protection counter 21 outputs a reset signal. Then, the flip-flop circuit 19 determines that it is not synchronized at the correct position, and outputs the out-of-synchronization signal N.

The reset signal also resets the adder 25 and the protection counter 21 like the set signal. The out-of-sync signal N resets the initial synchronization circuit 3, the adder 25, and the protection counter 21. The operations of the adder 25 and the protection counter 21 will be described in detail below.

First, the case where the correlation output signal C is synchronized at the correct position will be described. FIG. 12 is a diagram showing a relationship between the addition amount of the adder 25 and the count number of the protection counter 21 of FIG. 11 when the correlation output signal C is synchronized at the correct position. The vertical axis represents the addition amount, and the horizontal axis represents the count number. The horizontal axis can be considered as the time axis.

The relationship between the addition amount and time in the adder 25 of the synchronization protection circuit according to the second embodiment of FIG. 11 is the relationship between the addition amount and time of the synchronization protection circuit according to the first embodiment as shown in FIG. Is the same as. In FIG. 8, the actual addition amount line b is similar to the ideal addition amount line a. However, in the synchronization protection circuit according to the second embodiment, although not shown, the actual addition amount line b The ideal addition amount line is approximate. From this, the relationship between the addition amount and the count number (time) as shown in FIG. 12 can be derived.

Here, AA is a predetermined target value when the addition amount overflows in the adder 25 of FIG. m is a target number when the count number overflows in the protection counter 21 of FIG. When synchronizing at the correct position, the protection counter 2 in FIG.
Before the count number of 1 reaches the target number m, the addition amount of the adder 25 of FIG. 11 reaches the target value AA, and the adder 2
No. 5 overflows first, and synchronization is never lost.

A predetermined target value at which the addition amount in the adder 25 in FIG. 11 overflows and a predetermined target number at which the count number of the protection counter 21 overflows are set so as to have such a relationship. The adder 25
It is also possible to set the predetermined target value in 1 to BB larger than AA and set the predetermined target number in the protection counter 21 to n larger than m. In this case, since the integration is increased, errors are reduced, but synchronization protection takes time.

Next, the case where synchronization is performed at an incorrect position will be described. FIG. 13 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection circuit according to the second embodiment of FIG.

Consider a case where the synchronization protection circuit shown in FIG. 11 is synchronized at the position indicated by arrow G in FIG. 13, that is, a case where the synchronization protection circuit is synchronized at an incorrect position.

FIG. 14 is a diagram showing the relationship between the addition amount of the adder 25 of FIG. 11 and the count number of the protection counter 21 when synchronizing at an incorrect position as shown in FIG. The line indicated by arrow N shows the relationship between the addition amount and the count number when synchronized at the correct position. The line indicated by arrow A shows the relationship between the addition amount and the count number when synchronized at an incorrect position.

The signal added by the adder 25 shown in FIG. 11 is the signal indicated by the arrow G in FIG. 13, and it is considered that noise is superimposed on the autocorrelation value of the spread code.
In this case, the addition amount converges on the autocorrelation value. This is because the spread spectrum correlation output signal C has a constant value when viewed statistically for a long time. Typically,
The autocorrelation value is about 0.3 to 0.4 at maximum when the value of the correctly correlated value is normalized to be 1. From this,
The slope of the line A showing the relationship between the addition amount and the count number when synchronized at an incorrect position is smaller than the slope of the line N showing the relationship between the addition amount and the count number when synchronized at the correct position. Has become.

Here, AA is a predetermined target value when the addition amount in the adder 25 in FIG. 11 overflows. m is a predetermined target number when the count number in the protection counter 21 in FIG. 11 overflows.

Here, when synchronizing at an incorrect position (line indicated by arrow A), the count number of the protection counter 21 reaches the target number m before the addition amount of the adder 25 reaches AA. Therefore, the protection counter 21 overflows first, and it is determined that the synchronization is incorrect, and the synchronization is removed. On the other hand, when synchronizing at the correct position (line indicated by arrow N), when the count number of the protection counter 21 reaches k (smaller than m at which the protection counter 21 overflows), the addition amount of the adder 25 is AA is reached and overflows and the correct sync position is maintained.

As described above, in the synchronization protection circuit according to the second embodiment of the present invention, since the addition is made as an analog value or multi-bit data so as not to impair the amplitude level of the correlation output signal C, the addition amount The relationship of the number of counts (time) is as shown in FIGS. 12 and 14, and the predetermined target value AA and the protection of FIG. 11 where the adder 25 of FIG. 11 overflows due to the required C / N and the required pull-in time. A predetermined target number m at which the count number of the counter 21 overflows can be set in small steps, and the degree of freedom in designing increases. Therefore, the synchronization protection circuit according to the second embodiment can be optimally designed according to the product used.

For the same reason, the synchronization performance can be improved in the synchronization protection circuit according to the second embodiment.

Further, for the same reason, in the synchronization protection circuit according to the second embodiment, sufficient protection characteristics can be obtained over a wide C / N range.

Further, in the synchronization protection circuit according to the second embodiment, since the protection counter 21 is provided as a circuit for removing the synchronization in FIG. 11, the first protection circuit shown in FIG.
The number of circuits is smaller than that in the case where the first gate 9 and the first adder 19 are provided as a circuit for removing the synchronization like the synchronization protection circuit according to the embodiment. Further, the protection counter 21 of FIG. 11 has a smaller circuit scale than the first adder 19 of FIG. From this, in the synchronization protection circuit according to the second embodiment, the circuit scale can be made smaller than that of the synchronization protection circuit according to the first embodiment.

However, the degree of freedom in design is slightly reduced as compared with the synchronization protection circuit according to the first embodiment.

Next, a modification of the synchronization protection circuit according to the second embodiment will be described. FIG. 15 is a schematic block diagram showing a synchronization protection circuit in a modified example of the second embodiment which can effectively cope with the case where a multipath signal is input.

The synchronous protection circuit in the modification of the second embodiment shown in FIG. 15 is obtained by providing a gate width determining circuit 26 and a gate width control circuit 27 in the structure of the synchronous protection circuit according to the first embodiment shown in FIG. Is. The gate width determination circuit 26 is connected to the demodulation circuit 28.

The operations of the gate width determination circuit 26 and the gate width control circuit 27 are shown in FIG. 10, and the gate width determination circuit 26 of the synchronization protection circuit in the modification of the first embodiment is shown.
The operation is the same as that of the gate width control circuit 27.

Therefore, in the synchronization protection circuit according to the modification of the second embodiment, the same effects as those of the synchronization protection circuit according to the second embodiment of FIG. 11 are obtained, and the synchronization protection circuit of the first embodiment shown in FIG. The same effects as the effects unique to the synchronization protection circuit in the modified example are achieved.

(Third Embodiment) FIG. 16 is a schematic block diagram showing a synchronization protection circuit according to the third embodiment.

The synchronization protection circuit according to the third embodiment can also be used in the receiver of the general spread spectrum communication system of FIG. 34 described in the section of the prior art. Therefore, a case where the synchronization protection circuit according to the third embodiment is used as the synchronization protection circuit 57 of the receiver of the spread spectrum communication system of FIG. 34 will be described.

In FIG. 16, the synchronization protection circuit according to the third embodiment includes a discriminator 1, an initial synchronization circuit 3, a synchronization counter 5, a protection counter 21, a difference signal output circuit 7, and a gate 2.
3, an adder 25, an OR circuit 17, and a flip-flop circuit 19.

In FIG. 16, the difference signal output circuit 7, the gate 23, the adder 25, the OR circuit 17, and the flip-flop 19 are respectively the difference signal output signal 7 of the synchronization protection circuit according to the first embodiment shown in FIG. First gate 9, first adder 11, OR circuit 17, and flip-flop circuit 1
This is similar to the operation of 9.

In FIG. 16, the operations of the discriminator 1, the initial synchronization circuit 3, the synchronization counter 5, and the protection counter 21 are as follows.
The operations of the discriminator 1, the initial synchronization circuit 3, the synchronization counter 5, and the protection counter 21 of the synchronization protection circuit according to the second embodiment shown in FIG. However, the second shown in FIG.
The protection counter 21 of the synchronization protection circuit according to the embodiment of FIG. 9 is used to remove the synchronization, but the protection counter 21 of the synchronization protection circuit according to the third embodiment shown in FIG. 16 is used to maintain the synchronization. .

That is, when the count number of the protection counter 21 reaches the predetermined target number before the addition amount of the adder 25 reaches the predetermined target value, the protection counter 21 overflows and the set signal is flip-flopped. It is output to the circuit 19 and the OR circuit 17. At this time,
The flip-flop circuit 19 determines that the synchronization is normal and outputs the synchronization normal signal S.

Upon receiving this set signal, the OR circuit 17 resets the adder 25 and the protection counter 21. If the synchronization is normal continuously, the protection counter 21 outputs the synchronization pulse P. That is,
When the protection counter 21 outputs a set signal, an "H" level signal is output, and when the protection counter 21 is reset, an "L" level signal is output.
This is repeated.

On the other hand, when the amount of addition in the adder 25 reaches a predetermined target value for overflow before the protection counter 21 overflows, the adder 25 outputs a reset signal to the flip-flop 19 and the OR circuit 17.
Output to. At this time, the flip-flop circuit 19 determines that the synchronization is not normal and outputs the out-of-synchronization signal N. The out-of-sync signal N resets the initial synchronization circuit 3, the adder 25, and the protection counter 21. The OR circuit 17 determines whether the adder 25 and the protection counter 21 are based on the reset signal.
Reset. The above will be described in detail.

FIG. 17 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection circuit of the third embodiment of FIG.

From the difference signal output circuit 7 of FIG.
The difference signal D having a magnitude of 4 is output to the gate 23. Further, at the position of the arrow G, the gate 23 of FIG. 16 opens. The signal waveform represented by the solid line is a signal when there is level fluctuation due to noise, and is the correlation output signal C actually input to the synchronization protection circuit. The signal waveform shown by the broken line shows an ideal signal with no level fluctuation due to noise.

FIG. 18 is a diagram showing the relationship between the addition amount of the adder 25 and the count number of the counter 21 in the synchronization protection circuit of FIG.

The vertical axis shows the amount of addition, and the horizontal axis shows the number of counts. The horizontal axis can be considered as the time axis. The line indicated by the arrow N represents the relationship between the addition amount and the count number when synchronization is made at the correct position as shown in FIG. The line indicated by the arrow A shows the relationship between the addition amount and the count number when synchronized at an incorrect position. AA is a predetermined target value at which the addition amount in the adder 25 in FIG. 16 overflows. m is a predetermined target number at which the count number of the protection counter 21 in FIG. 16 overflows.

Since the adder 25 of FIG. 16 adds the difference signal D, the line N when synchronizing at the correct position is used.
Is smaller than the slope of the line A when synchronizing at an incorrect position. That is, the difference signal becomes small when synchronizing at the correct position, and becomes large when synchronizing at the incorrect position.

Here, in FIG. 18, the relationship between the addition amount obtained by adding the difference signals and the count number (time) is linear because the actual addition amount line b and the ideal addition amount line b in FIG. This is because the relationship that the addition amount line a is approximate can be similarly applied to the relationship between the addition amount obtained by adding the difference signals and the time (count number).

When synchronizing at the correct position (arrow N
16), the addition amount of the adder 25 in FIG. 16 reaches the target number m before the target value AA, and the overflow occurs because the count number of the protection counter 21 reaches the target number m and it is determined that the synchronization is normal. On the other hand, when synchronizing at an incorrect position (indicated by arrow A), the addition amount of the adder 25 in FIG. 16 is before the count number of the protection counter 21 reaches m (the target number of protection counter 21 overflow). Then, the target value AA is reached and overflow occurs, and it is determined that the synchronization is not correct.

That is, the adder 25 overflows when the count number of the protection counter 21 of FIG. 16 becomes k. Here, in the synchronization protection circuit according to the second embodiment, as shown in FIG. 14, the synchronization cannot be released until the count number of the protection counter 21 reaches m, but the synchronization protection according to the third embodiment is performed. The circuit includes a protection counter 21
The synchronization can be released at the stage of k before the count number of reaches m.

As described above, in the synchronization protection circuit according to the third embodiment of the present invention, since the adder 25 is used as the circuit for canceling the synchronization (the protection counter 21 is used as the circuit for maintaining the synchronization). Since it is used), the time for losing synchronization can be shortened and the synchronization recovery performance can be improved.
Further, in the synchronization protection circuit according to the third embodiment of the present invention, as shown in FIG. 18, the relationship between the addition amount and the time is linear and the synchronization according to the first embodiment of FIG. Since the protection counter 21 of FIG. 16 is used without using the second gate 13 and the second adder 15 as a circuit for maintaining the synchronization like the protection circuit, similar to the synchronization protection circuit according to the second embodiment. The number of circuits is also small. Therefore, in the synchronization protection circuit according to the third embodiment, the second
The effect similar to that of the synchronization protection circuit of FIG. Next, a modification of the synchronizing circuit according to the third embodiment will be described.

FIG. 19 is a schematic block diagram showing a synchronization protection circuit according to a modification of the third embodiment, which can effectively deal with the case where a multipath signal is input.

In FIG. 19, a synchronization protection circuit according to a modification of the third embodiment has a gate width determination circuit 26 and a gate width control circuit 27 added to the configuration of the synchronization protection circuit according to the third embodiment of FIG. It is a thing. The gate width determination circuit 26 is connected to the demodulation circuit 28.

The operations of the gate width determination circuit 26 and the gate width control circuit 27 are the same as the operations of the gate width determination circuit 26 and the gate width control circuit 27 of the synchronization protection circuit of the modification of the first embodiment shown in FIG. Is. The operation of the other part of the synchronization protection circuit of the modification of the third embodiment of FIG. 19 is similar to the operation of the synchronization protection circuit of the third embodiment shown in FIG.

Therefore, in the synchronization protection circuit of the modification of the third embodiment of the present invention, in addition to the effect of the synchronization protection circuit of the third embodiment shown in FIG. 16, the first embodiment shown in FIG. It also has an effect peculiar to the synchronization protection circuit of the modified example.

(Fourth Embodiment) In a spread spectrum communication system, there is a unique correlation output called autocorrelation, and when it is used in CDMA (code division multiple access system), due to the cross correlation of other stations, Receive constant interference. Therefore, unlike a general frame synchronization circuit, a correlation output of a certain size is constantly generated at the same time timing.

As a result, depending on the condition of synchronization pull-in,
There is a risk that synchronization may be lost at the wrong position. Therefore, the synchronization protection system of the spread spectrum communication system according to the fourth exemplary embodiment of the present invention includes two synchronization protection circuits to solve such a problem.

The synchronization protection circuit according to the fourth embodiment can also be used in the receiver of the general synchronization protection system of FIG. 35 described in the section of the prior art. Therefore, a case where the synchronization protection circuit according to the fourth embodiment is used as the synchronization protection circuit 57 of the receiver of the synchronization protection system of FIG. 35 will be described.

FIG. 20 is a schematic block diagram showing a synchronization protection system according to the fourth embodiment of the present invention.

The synchronization protection system according to the fourth embodiment can also be used in the receiver of the general spread spectrum communication system of FIG. 34 described in the section of the prior art. Therefore, a case where the synchronization protection system according to the fourth embodiment is used as the synchronization protection circuit 57 of the receiver of the spread spectrum communication system of FIG. 34 will be described.

In FIG. 20, the synchronization protection system according to the fourth embodiment of the present invention comprises a first synchronization protection circuit 29 and a second synchronization protection circuit 31.

Next, the operation will be described. In FIG. 20, the correlation output signal C is input to the first synchronization protection circuit 29 and the second synchronization protection circuit 31. Then, the first synchronization protection circuit 29 enters the synchronization process at a timing satisfying a predetermined condition for pulling in the synchronization. Hereinafter, the synchronization timing in the first synchronization protection circuit 29 will be referred to as the first synchronization timing.

On the other hand, the second synchronization protection circuit 31 starts its operation by the synchronization signal S indicating that the first synchronization protection circuit 29 is synchronized, and sees the synchronization timing signal SS to check the first synchronization protection circuit 31. At a timing different from the first synchronization timing in the circuit 29, a synchronization point is searched for under a predetermined condition for synchronization pull-in. If initial synchronization is performed, the second synchronization protection circuit 31 also enters the synchronization process. Hereinafter, the synchronization timing in the second synchronization protection circuit 31 will be referred to as the second synchronization timing.

When the first synchronization protection circuit 29 is synchronized at the correct position, the first synchronization protection circuit 29 generates the synchronization pulse P and returns the second synchronization protection circuit 31 to the initial state. (Reset). In addition, the second synchronization protection circuit 3
When 1 is synchronized at the correct position, the second synchronization protection circuit 31 generates the second false lock pulse FS and resets (resets) the first synchronization protection circuit 29 to the initial state.
When the first synchronization protection circuit 29 itself determines that its own first synchronization timing is incorrect, the first synchronization protection circuit 29 outputs the first false lock pulse FP.

As described above, in the synchronization protection system according to the fourth embodiment, the first synchronization protection circuit 29 and the second synchronization protection circuit 31 compete with each other so that the first synchronization protection circuit 29 can operate. The second synchronization protection circuit 31 returns the first synchronization protection circuit 29 to the initial state until synchronization is made at the correct position. Further, when the first synchronization protection circuit 29 is synchronized at the correct position, even if the second synchronization protection circuit 31 is operating, the second synchronization protection circuit 31 is repeatedly returned to the initial state. The synchronization of the first synchronization protection circuit 29 is maintained. Hereinafter, detailed description will be made using specific circuits for the first synchronization protection circuit 29 and the second synchronization protection circuit 31.

FIG. 21 shows the first synchronization protection circuit 2 of FIG.
9 is a schematic block diagram showing an example of a synchronization protection circuit that can be used as the ninth and second synchronization protection circuits 31. FIG.

The structure and operation of the sync protection circuit of FIG. 21 are similar to those of the conventional sync protection circuit shown in FIG. Therefore, the part different from the conventional synchronization protection circuit shown in FIG. 35 will be mainly described. Hereinafter, FIG.
0 and FIG. 21.

First, a case where the synchronization protection circuit of FIG. 21 is used as the first synchronization protection circuit 29 will be described. In this case,
Signal X output from the false lock counter 35 of No. 1
Corresponds to the first false lock pulse FP in FIG. Figure 2
The signal Y received by the initial synchronization circuit 3, the false lock counter 35, and the positive lock counter 39 of FIG.
Corresponds to the false lock pulse FS. The signal SS ₁ output from the synchronization counter 5 in FIG. 21 corresponds to the synchronization timing signal SS in FIG. The synchronization pulse P in FIG.
This corresponds to the sync pulse P in FIG. The synchronization normal signal S in FIG. 21 corresponds to the synchronization signal S in FIG. Note that FIG.
It is assumed that there is no signal SS ₂ received by the initial synchronization circuit 3 of FIG.

Next, the case where the synchronization protection circuit of FIG. 21 is used as the second synchronization protection circuit 31 of FIG. 20 will be described.
The synchronization pulse P output from the positive lock counter 39 of FIG. 21 corresponds to the second false pulse FS of FIG. The signal SS ₂ received by the initial synchronization circuit 3 of FIG.
It corresponds to a synchronization timing signal SS of zero. It is assumed that there is no signal SS ₁ output from the synchronization counter 5 and no signal Y received by the initial synchronization circuit 3, the false lock counter 35, and the positive lock counter 39.

The case where the synchronization protection circuit of FIG. 21 is used as the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20 will be described below. Based on the above, in the specific description of each of the first synchronization protection circuit 31 and the second synchronization protection circuit 31 of FIG. 20, FIG.
To share.

The threshold TH1 in the discriminator 1 of the first sync protection circuit 29 is set smaller than the threshold TH2 in the discriminator 1 of the second sync protection circuit 31. FIG.
FIG. 21 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection system of FIG.

In FIG. 22, TH1 indicates the threshold value TH1 of the discriminator 1 of the first synchronization protection circuit 29 of FIG.
TH2 is the discriminator 1 of the second synchronization protection circuit 31 of FIG.
The threshold value TH2 is shown. Here, the arrow a is the synchronization point of the first synchronization protection circuit 29 in FIG. 20, and the arrow b is in FIG.
This is the synchronization point of the second synchronization protection circuit 31.

That is, let us consider a case where the first synchronization protection circuit 29 is synchronized with a signal having a smaller correlation than the signal with which the second synchronization protection circuit 31 is synchronized, among the correlation output signals C. It returns to FIG. 20 and FIG. 21, and demonstrates.

Here, it is assumed that the positive lock counter 39 of the first synchronization protection circuit 29 and the second protection circuit 31 overflow by the same count number. As shown in FIG. 22, the correlation of the correlation output signal C synchronized by the second synchronization protection circuit 31 is larger than the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29. The positive lock counter 39 of the synchronization protection circuit 31 first overflows, and it is determined that the second synchronization timing of the second synchronization protection circuit 31 is correct, and the first synchronization protection circuit 39 receives the second false lock pulse. It outputs FS (synchronization pulse P) and resets the first synchronization protection circuit 29.

Then, the first synchronization protection circuit 29 resynchronizes. Such an operation is performed by the first synchronization protection circuit 29.
Until the positive lock counter 39 of 6 overflows earlier than the positive lock counter 39 of the second synchronization protection circuit 31.
That is, until the correlation of the correlation output signal synchronized by the first synchronization protection circuit 29 becomes larger than the correlation of the correlation output signal C synchronized by the second synchronization protection circuit 31 (the first synchronization timing is 2) until it is correct from the synchronization timing of 2).

Next, the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29 is determined by the second synchronization protection circuit 31.
Consider a case where the correlation is larger than the correlation of the correlation output signal C synchronized with. At this time, the positive lock counter 39 of the first synchronization protection circuit 29 overflows earlier than the positive lock counter 39 of the second synchronization protection circuit 31, and the first synchronization protection circuit 29 judges that the synchronization is correct and the synchronization pulse P is output and the second synchronization protection circuit 31 is reset. This operation is repeated as long as the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29 is larger than the correlation of the correlation output signal C synchronized by the second synchronization protection circuit 31.

As described above, in the synchronization protection system according to the fourth embodiment of the present invention, the first synchronization protection circuit 2
9 and the second synchronization protection circuit 31 compete with each other (two synchronization protection circuits compete with each other), so that when the first synchronization protection circuit 29 is synchronized at the wrong position, the second synchronization protection circuit 31 causes The first synchronization protection circuit 29 is reset and resynchronized, and when the first synchronization protection circuit 29 is synchronized at the correct position, the second synchronization protection circuit 31 is operating due to autocorrelation or cross-correlation. However, since the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29 is large on average, the first synchronization protection circuit 29 maintains the synchronization.

Therefore, in the synchronization protection system according to the fourth embodiment of the present invention, synchronization at an erroneous position due to autocorrelation or cross-correlation does not occur, and the synchronization performance can be improved. Furthermore, in the synchronization protection system according to the fourth embodiment of the present invention, synchronization at an erroneous position due to autocorrelation or cross-correlation does not occur, and therefore, the discriminator 1 of the first synchronization protection circuit 29 is unnecessarily used. There is no need to raise the threshold value, and the initial synchronization circuit 3 of the first synchronization protection circuit 29
However, it is possible to move stably even under a low CN.

By the way, in the above description, the synchronization protection circuit of FIG. 21 is used for the second synchronization protection circuit 31 of FIG. 20, but the synchronization protection circuit of FIG. The gate 37, the false lock counter 35, and the flip-flop circuit 19) are provided. However, the second synchronization protection circuit 31 of FIG. 20 is for detecting whether there is a correlation output signal C having a correlation higher than the correlation of the correlation output signal C synchronized in the first synchronization protection circuit 29. Therefore, it is not necessary to detect whether the second synchronization protection circuit 31 itself is not synchronized at the wrong position.

Even if the second synchronization protection circuit 31 synchronizes with the correlation output signal C having a correlation smaller than the correlation of the correlation output signal C synchronized with the first synchronization protection circuit 29, there is no problem. Therefore, in the second synchronization protection circuit 31, the second synchronization protection circuit 31 shown in FIG.
When the synchronization protection circuit of No. 1 is used, the circuits (logic gate 37, false lock counter 35, flip-flop circuit 19) for breaking the synchronization can be removed. The above will be described in detail.

FIG. 23 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection system of FIG.

In FIG. 23, TH is a threshold value of the discriminator 1 of the first synchronization protection circuit 29 of FIG. 20, which is smaller than the threshold value of the discriminator 1 of the second synchronization protection circuit 31. . Here, it is assumed that the first synchronization protection circuit 29 of FIG. 20 is synchronized with the signal C1 of the correlation output signals C. Since the signal C1 exceeds the threshold value TH of the first synchronization protection circuit 29, the first synchronization protection circuit 29 remains in synchronization.

However, the correlation output signal C includes the signals C2 and C3 separately, and originally, it is necessary to synchronize with the signal C2. At this time, the second synchronization protection circuit 31
Is erroneously synchronized with the signal C3 that does not exceed the threshold value of the second synchronization protection circuit 31. In this case, FIG.
When the synchronization protection circuit of FIG. 21 is used as the second synchronization protection circuit 31 of FIG. 21, the synchronization protection circuit of FIG. 21 includes a circuit for preventing synchronization at an incorrect position.
If it is synchronized with the signal C2, it is determined that it is synchronized with the wrong position, and the signal C2 is resynchronized. That is, the second synchronization protection circuit 31 resynchronizes with the signal C2 having a larger amplitude than the signal C1 synchronized with the first synchronization protection circuit 29.

However, in FIG. 20, when the second synchronization protection circuit 31 is synchronized at the wrong position (the signal C3 smaller than the signal C1 synchronized by the first synchronization protection circuit 29).
(In the case of synchronization with), the second synchronization protection circuit 31 is reset by the synchronization pulse P of the first synchronization protection circuit 29, and the initial synchronization is restored. If the second synchronization protection circuit 31 resynchronizes and synchronizes with the signal C2 (greater than the signal C1 synchronized with the first synchronization protection circuit 29), the second
The synchronization protection circuit resets the first synchronization protection circuit 29 by the second false lock pulse FS (synchronization pulse P in FIG. 21). Therefore, the first synchronization protection circuit 29 resynchronizes and resynchronizes with the signal C2 having a higher correlation than the signal C1.

From the above, when the synchronization protection circuit of FIG. 21 is used as the second synchronization protection circuit 31 of FIG. 20, a circuit (logic gate 37, erroneous lock counter 35, flip-flop circuit) for releasing synchronization is used. 19) can be removed. As described above, in the synchronization protection system according to the fourth embodiment of the present invention, when the first synchronization protection circuit synchronizes with the second synchronization protection circuit at the wrong position, When the synchronization protection circuit of FIG. 21 is used as the second synchronization protection circuit, the circuit that removes the synchronization can be eliminated and the circuit scale of the second synchronization protection circuit can be eliminated. Can be made smaller.

Next, the same circuits as the sync protection circuit according to the first embodiment shown in FIG. 1 are used for the first sync protection circuit 29 and the second sync protection circuit 31 of the sync protection system of FIG. The case will be described.

FIG. 24 is a schematic block diagram showing an example of a sync protection circuit that can be used for the first sync protection circuit 29 and the second sync protection circuit 31 of the sync protection system of FIG.

The structure and operation of the sync protection circuit of FIG. 24 are similar to those of the sync protection circuit according to the first embodiment shown in FIG. However, the difference from the configuration of the first synchronization protection circuit shown in FIG. 1 is that the synchronization protection circuit of FIG. 24 includes an OR circuit 33. Below, mainly
Explain the different parts.

First, the case where the synchronization protection circuit of FIG. 24 is used as the first synchronization protection circuit 29 of FIG. 20 will be described.

In FIG. 24, the signal X from the first adder 11 corresponds to the first false lock pulse FP in FIG. The signal Y input to the OR circuit 33 in FIG. 24 corresponds to the second false lock pulse FS in FIG. The output signal SS ₁ from the sync counter 5 in FIG. 24 corresponds to the sync timing signal SS in FIG. The sync pulse P in FIG. 24 corresponds to the sync pulse P in FIG. The synchronization normal signal S of FIG. 24 corresponds to the synchronization signal S of FIG.

When the synchronization protection circuit of FIG. 24 is used as the first synchronization protection circuit 29, there is no signal SS ₂ input to the initial synchronization circuit 3. Here, the OR circuit 3
When the out-of-synchronization signal N or the signal Y (second false lock pulse FS) is input to 3, the initial synchronization circuit 3, the first adder 11 and the second adder 15 are reset.

Next, the case where the synchronization protection circuit of FIG. 24 is used as the second synchronization protection circuit 31 of FIG. 20 will be described. The synchronization pulse P from the second adder 15 in FIG. 24 corresponds to the second false lock pulse FS in FIG. The signal SS ₂ input to the initial synchronization circuit 3 of FIG. 24 corresponds to the synchronization timing signal SS of FIG. When the synchronization protection circuit of FIG. 24 is used as the second synchronization protection circuit 31 of FIG. 20, the signal SS ₁ , the signal Y and the OR circuit 33 are not provided.

A case where the synchronization protection circuit of FIG. 24 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20 will be described below. Based on the above, the detailed description of each of the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG.
Share 4

A predetermined target value at which the addition amount of the second adder 15 in FIG. 24 overflows is set to the first synchronization protection circuit 29.
Is smaller than that of the second synchronization protection circuit 31. This case will be described in detail below.

FIG. 25 is a diagram showing an example of the waveform of the correlation output signal C input to the synchronization protection system of FIG.

In FIG. 25, the arrow ST1 indicates the synchronization point of the first synchronization protection circuit 29, and the arrow ST2 indicates the synchronization point of the second synchronization protection circuit 31. That is, the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29 is
Correlation output signal C synchronized by the second synchronization protection circuit 31
Is smaller than the correlation of.

FIG. 26 shows the relationship between the addition amount of the second adder 15 of the first synchronization protection circuit 29 and the second synchronization protection circuit 31 and the time when the correlation output signal C of FIG. 25 is input. FIG.

The vertical axis represents the amount of addition and the horizontal axis represents time. The line indicated by arrow A2 indicates the relationship between the addition amount in the second adder 15 of the second synchronization protection circuit 31 and time. The line indicated by arrow A1 shows the relationship between the addition amount of the second adder 15 of the first synchronization protection circuit 29 and time.
AA2 is a predetermined target value at which the addition amount of the second adder 15 of the second synchronization protection circuit 31 overflows. AA
1 is a predetermined target value at which the addition amount of the second adder 15 of the first synchronization protection circuit 29 overflows.

The sync point of the first sync protection circuit 29 is shown in FIG.
When the synchronization point of the second synchronization protection circuit 31 is at the position shown by arrow ST2 in FIG.
As shown in FIG. 26, the addition amount of the second synchronization protection circuit 31 reaches the predetermined target value AA2 earlier than the addition amount of the first synchronization protection circuit 29 and overflows. , Outputs the second false lock pulse FS (synchronization pulse P in FIG. 24) to the first synchronization protection circuit 29,
The synchronization protection circuit 29 is reset, and the first synchronization protection circuit 29 resynchronizes.

Next, consider a case where the synchronization point of the first synchronization protection circuit 29 is the arrow ST2 in FIG. 25 and the synchronization point of the second synchronization protection circuit 31 is the arrow ST1. That is, the correlation of the correlation output signal C synchronized by the first synchronization protection circuit 29 is larger than the correlation of the correlation output signal C synchronized by the second synchronization protection circuit 31.

At this time, the addition amount of the second adder 15 of the first synchronization protection circuit 29 reaches a predetermined target value earlier than the addition amount of the second synchronization protection circuit 31 and overflows. Of the second synchronization protection circuit 31 outputs the synchronization pulse P to the second synchronization protection circuit 31.
Reset. Then, the second synchronization protection circuit 31 resynchronizes.

As described above, in the synchronization protection system of the fourth embodiment, the discriminator 1 of FIG. 24 adjusts the synchronization timing of the first synchronization protection circuit and the second synchronization protection circuit.
The predetermined target value at which the second adder 15 overflows is changed by the first synchronization protection circuit and the second synchronization protection circuit instead of the threshold value. By doing so, in the synchronization protection system according to the fourth embodiment, in the relationship between the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20, the first synchronization protection circuit of FIG. The same effect as that when the synchronization protection circuit of FIG. 21 is used for the circuit 29 and the second synchronization protection circuit 31 is obtained. Further, the first synchronization protection circuit 2 of FIG.
Each of the ninth and second synchronization protection circuits 31 has the same effect as the synchronization protection circuit according to the first embodiment shown in FIG. Furthermore, since the predetermined target value for overflow of the second adder 15 of the first synchronization protection circuit 29 and the second synchronization protection circuit 31 can be set in small increments, the degree of freedom in designing the synchronization protection system is increased and the synchronization performance is improved. Can be improved.

Further, in the second synchronization protection circuit 31, FIG.
For the same reason as described in the case of using the synchronization protection circuit of FIG. 24, a circuit for removing synchronization (difference signal output circuit 7, first gate) even when the synchronization protection circuit of FIG. 24 is used for the second synchronization protection circuit 31. 9, the first adder 11 and the flip-flop circuit 19) can be removed, and the circuit scale of the second synchronization protection circuit 31 can be reduced.

Next, the case where the same circuits as the synchronization protection circuit according to the second embodiment shown in FIG. 11 are used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20 will be described. .

FIG. 27 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

The structure and operation of the synchronization protection circuit of FIG. 27 are almost the same as those of the synchronization protection circuit of FIG. However,
The synchronization protection circuit of FIG. 27 further includes an OR circuit 33 in addition to the synchronization protection circuit of FIG. The differences will be mainly described below.

First, the case where the synchronization protection circuit of FIG. 27 is used as the first synchronization protection circuit 29 will be described. 27, the synchronization normal signal S corresponds to the synchronization signal S of FIG. The signal SS ₁ output from the synchronous counter 5 is as shown in FIG.
It corresponds to a synchronization timing signal SS of zero. 27 OR
The signal Y input to the circuit 33 corresponds to the second false lock pulse FS in FIG. The signal X output from the protection counter 21 corresponds to the first false lock pulse FP. Note that the synchronization pulse P output from the adder 25 in FIG.
Corresponds to the synchronization pulse P in FIG. It is assumed that there is no signal SS ₂ input to the initial synchronization circuit 3.

When the out-of-synchronization signal N or the signal Y (second false lock pulse FS) is input to the OR circuit 33, the initial synchronization circuit 3, the adder 25 and the protection counter 21 are reset. .

The second synchronization protection circuit 31 shown in FIG.
The case of using the synchronization protection circuit will be described. SS ₂ input to the initial synchronization circuit 3 corresponds to the synchronization timing signal SS of FIG. The synchronization pulse P output from the adder 25 corresponds to the second false lock pulse FS in FIG. It is assumed that the signal SS ₁ from the synchronous counter 5, the signal Y and the OR circuit 33 are not provided.

As described above, the operation when the synchronization protection circuit of FIG. 27 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG.
The relationship of the sync protection circuit 31 is the same as the operation when the sync protection circuit of FIG. 24 is used for the first sync protection circuit 29 and the second sync protection circuit 31.

Therefore, when the synchronization protection circuit of FIG. 27 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20, the first synchronization protection circuit 29 and the second synchronization protection circuit are used. With respect to the relationship with 31, the same effect as when the synchronization protection circuit of FIG. 24 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 is obtained. Further, when the synchronization protection circuit of FIG. 27 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31, the first synchronization protection circuit 29 is used.
And the second synchronization protection circuit 31 have the same effects as the synchronization protection circuit of FIG. 11 according to the second embodiment. Also,
When the synchronization protection circuit of FIG. 27 is used as the second synchronization protection circuit 31, a circuit for removing synchronization (protection counter 21,
Since the OR circuit 17 and the flip-flop circuit 19) can be omitted, the second synchronization protection circuit can be downsized.

Next, the case where the same circuits as the synchronization protection circuit according to the third embodiment shown in FIG. 16 are used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20 will be described.

FIG. 28 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

The structure and operation of the synchronization protection circuit of FIG. 28 are almost the same as the structure and operation of the synchronization protection circuit of FIG. However, the synchronization protection circuit of FIG. 28 is further provided with an OR circuit 33 in addition to the configuration of the synchronization protection circuit of FIG. The differences will be mainly described below.

First, the case where the synchronization protection circuit of FIG. 28 is used as the first synchronization protection circuit 29 of FIG. 20 will be described.
The signal SS ₁ from the synchronization counter 5 in FIG. 28 corresponds to the synchronization timing signal SS in FIG. The signal Y input to the OR circuit 33 in FIG. 28 corresponds to the second false lock pulse FS in FIG. The sync pulse P from the protection counter 21 of FIG. 28 corresponds to the sync pulse P of FIG. The normal synchronization signal S from the flip-flop circuit 19 corresponds to the synchronization signal S in FIG. It is assumed that there is no SS ₂ input to the initial synchronization circuit 3.

Here, when the out-of-synchronization signal N or the signal Y (second false lock pulse FS) is input to the OR circuit 33, the initial synchronization circuit 3, the adder 25 and the protection counter 21 are reset. .

Next, a description will be given of a circuit using the synchronization protection circuit of FIG. 28 as the second synchronization protection circuit 31 of FIG.
The signal SS ₂ input to the initial synchronization circuit 3 of FIG. 28 corresponds to the synchronization timing signal SS of FIG. The synchronization pulse P from the protection counter 21 of FIG. 28 corresponds to the second false lock pulse FS of FIG. It is assumed that the signal SS ₁ , the signal Y and the OR circuit 33 from the synchronous counter 5 of FIG. 28 are not provided.

A case where the synchronization protection circuit of FIG. 28 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20 will be described below. Note that, based on the above, a detailed description of each of the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG.
To share.

When the synchronization protection circuit of FIG. 28 is used as the first synchronization protection circuit 29 and the second synchronization protection circuit 31, the synchronization timing of the first synchronization protection circuit 29 and the second synchronization protection circuit 31 is changed. The adjustment is performed by setting a predetermined target value at which the addition amount of the adder 25 overflows as in the case of using the synchronization protection circuit of FIG. 24 for the first synchronization protection circuit 29 and the second synchronization protection circuit 31. To do. However, in this case, the first synchronization protection circuit 29 is set to be larger than the second synchronization protection circuit 31. This is because the adder 25 adds the difference signals, which is the reverse of the case where the synchronization protection circuit of FIG. 24 is used.

By doing so, when the synchronization protection circuit of FIG. 28 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31, the first synchronization protection circuit 29 and the second synchronization protection circuit 29 are used. With respect to the relationship with the sync protection circuit 31, the same effects as those when the sync protection circuit of FIG. 24 is used for the first sync protection circuit 29 and the second sync protection circuit 31 are obtained. Furthermore, the first
Each of the synchronization protection circuit 29 and the second protection circuit 31 has the same effect as the synchronization protection circuit according to the third embodiment shown in FIG. In addition, the second synchronization protection circuit 3
When the synchronization protection circuit of FIG. 26 is used in FIG. 1, a circuit for removing synchronization (difference signal output circuit 7, gate 23, adder 25, OR circuit 17, and flip-flop circuit 19)
Can be removed, so that the second synchronization protection circuit 31
Can be reduced in size.

In the above description, similar circuits are used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 20, but the first synchronization protection circuit 29 and the second synchronization protection circuit are used. Any of the synchronization protection circuits shown in FIGS. 21, 24, 27, and 28 can be used for each 31.

The first synchronization protection circuit 29 and the second synchronization protection circuit 29
When the synchronization protection circuit 31 of FIG. 24, FIG. 27 and FIG. 28 is used as the synchronization protection circuit 31 of FIG.
The gate width determination circuit 26 and the gate width control circuit 27 used in the synchronization protection circuit can be further provided, and in this case, the first synchronization protection circuit 29 and the second synchronization protection circuit 29 are provided.
Each of the synchronization protection circuits 31 has the same effect as the synchronization protection circuits of FIGS. 10, 15 and 19.

When any of the synchronization protection circuits of FIGS. 24 and 28 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31, the first synchronization protection circuit 29 and the second synchronization protection circuit 29 are used. The synchronization timing of the synchronization protection circuit 39 can be adjusted by changing the predetermined target value at which the first adder 11 in FIG. 24 overflows and the predetermined target value at which the adder 25 in FIG. 28 overflows. .
For example, when the synchronization protection circuit of FIG. 24 is used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31,
The predetermined target value at which the first adder 11 of the synchronization protection circuit overflows is set to be larger than the predetermined target value at which the first adder 11 of the second synchronization protection circuit overflows.

(Fifth Embodiment) FIG. 29 shows the fifth embodiment of the present invention.
FIG. 3 is a schematic block diagram showing a synchronization protection system according to an embodiment of the present invention.

The synchronization protection system according to the fifth embodiment can also be used in the receiver of the general spread spectrum communication system of FIG. 34 described in the section of the prior art. Therefore, a case where the synchronization protection system according to the fifth embodiment is used as the synchronization protection circuit 57 of the receiver of the spread spectrum communication system of FIG. 34 will be described.

In FIG. 29, the synchronization protection system according to the fifth embodiment of the present invention comprises a first synchronization protection circuit 29 and a second synchronization protection circuit 31.

In the synchronization protection system according to the fourth embodiment of FIG. 20, when the synchronization timing of the second synchronization protection circuit 31 is more correct than the synchronization timing of the first synchronization protection circuit 29, the second synchronization protection circuit. 31 outputs the second false lock pulse FS to the first synchronization protection circuit 29,
The synchronization protection circuit 29 of No. 1 was reset and the first synchronization protection circuit 29 was resynchronized, whereas in the synchronization protection system according to the fifth embodiment shown in FIG.
When the synchronization timing of the synchronization protection circuit 31 is correct, the second synchronization protection circuit 3 outputs the second erroneous lock pulse FS, and at the same time, the transition signal T to the first synchronization protection circuit 29.
S, and the first synchronization protection circuit 29 outputs the transition signal T
Upon receiving S, the synchronization timing of the first synchronization protection circuit 29 is set to the synchronization timing of the second synchronization circuit 31. In addition,
When the first sync protection circuit 29 is in sync, it outputs a sync pulse P. When the first synchronization protection circuit 29 itself determines that its own synchronization timing is incorrect, it outputs the first false lock pulse FP.

The first synchronization protection circuit 29 and the second synchronization protection circuit 31 of the synchronization protection system of FIG.
A circuit similar to the synchronization protection circuit shown in FIGS. 1, 24, 27, and 28 can be used. A case where the same circuits as the synchronization protection circuit of FIG. 21 are used for the first synchronization protection circuit and the second synchronization protection circuit 31 will be described.

FIG. 30 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

The synchronization protection circuit of FIG. 30 is obtained by adding a transition circuit 41 to the configuration of the synchronization protection circuit of FIG. Therefore, the operation will be described mainly on the points different from the synchronization protection circuit of FIG.

When the synchronization protection circuit of FIG. 30 is used as the first synchronization protection circuit 29 of FIG. 29, the second synchronization protection circuit 3
When the synchronization timing of 1 is correct, the transition circuit 41 outputs the transition signal TS ₁ (corresponding to the transition signal TS of FIG. 27) to the second signal.
The synchronization timing of the initial synchronization circuit 3 is set to the synchronization timing of the second synchronization protection circuit 31, and the false lock counter 35, the positive lock counter 39 and the flip-flop circuit 19 are returned to the initial state. In this case, it is assumed that there is no signal TS ₂ from the positive lock counter 39.

When the synchronization protection circuit of FIG. 30 is used as the second synchronization protection circuit 31 of FIG. 29, when the synchronization timing of the second synchronization protection circuit 31 is correct, the positive lock counter 39 transfers the transition signal TS ₂ (see FIG. Corresponding to the transition signal TS of 29) is output to the first synchronization protection circuit 29. In this case, the transition circuit 41 and the signal TS ₁ are not provided.

Here, when the synchronization protection circuit of FIG. 30 is used as the second synchronization protection circuit 31 of FIG. 29, a circuit (logic gate 37, erroneous lock counter 3) for removing synchronization is used.
5 and the flip-flop circuit 19) can be removed, and the second synchronization protection circuit 31 can be downsized.

Next, the case where the same circuits as the synchronization protection circuit of FIG. 24 are used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 29 will be described.

FIG. 31 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

The synchronization protection circuit shown in FIG. 31 is obtained by adding a transition circuit 41 to the configuration of the synchronization protection circuit shown in FIG. Therefore, the operation of the synchronization protection circuit of FIG.
Since the operation is the same as that of the synchronization protection circuit, the difference will be mainly described.

When the synchronization protection circuit of FIG. 31 is used as the first synchronization protection circuit 29 of FIG. 29, when the synchronization timing of the second synchronization protection circuit 31 is correct, the transition circuit 41
Receives the transition signal TS ₁ (corresponding to the transition signal TS of FIG. 29) from the second synchronization protection circuit 31, resets the first adder 11 and the second adder 15, and sets the synchronization timing of the initial synchronization circuit 3. The synchronization timing of the second synchronization protection circuit 31 is set. In this case, it is assumed that there is no signal TS ₂ from the second adder 15.

When the synchronization protection circuit of FIG. 31 is used as the second synchronization protection circuit 31 of FIG. 29, the second synchronization protection circuit 3
When the synchronization timing of 1 is correct, the second adder 15
Outputs a transition signal TS ₂ (corresponding to the transition signal TS in FIG. 29) to the first synchronization protection circuit 29. In this case, the transition circuit 41 and the signal TS ₁ are not provided.

Here, the synchronization protection circuit of FIG.
The gate width determination circuit 26 and the gate width control circuit 27 of the synchronization protection circuit can be provided. further,
When the synchronization protection circuit of FIG. 31 is used as the second synchronization protection circuit 31, a circuit for removing synchronization (difference signal output signal circuit 7, first gate 9, first adder 11, OR circuit 17 and flip-flop 17) is used. Circuit 19) can be eliminated, and the second synchronization protection circuit 31 can be miniaturized.

Next, the first synchronization protection circuit and the second synchronization protection circuit of FIG.
The case where a circuit similar to the synchronization protection circuit of FIG. 27 is used for the synchronization protection circuit 31 of FIG.

FIG. 32 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

In FIG. 32, the synchronization protection circuit is obtained by providing a transition circuit 41 in the configuration of the synchronization protection circuit of FIG. Therefore, the operation of the synchronization protection circuit of FIG. 32 is similar to the operation of the synchronization protection circuit of FIG. 27, and the difference will be mainly described.

When the synchronization protection circuit of FIG. 32 is used as the first synchronization protection circuit 29 of FIG. 29, the second synchronization protection circuit 3
When the synchronization timing of 1 is correct, the transition circuit 41 outputs the transition signal TS ₁ (corresponding to the transition signal TS of FIG. 29) to the second signal.
The synchronization timing of the initial synchronization circuit 3 is set to the synchronization timing of the second synchronization protection circuit 31, and the adder 25 and the protection counter 21 are reset. In this case, it is assumed that there is no signal TS ₂ from the protection counter 21.

When the synchronization protection circuit of FIG. 32 is used as the second synchronization protection circuit 31 of FIG. 29, when the synchronization timing of the second synchronization protection circuit 31 is correct, the transition signal TS ₂ from the protection counter 21 (see FIG. 29). Corresponding to the transition signal TS) to the first synchronization protection circuit 29. In this case, the transition circuit 41 and the signal TS ₁ are not provided.
Here, the gate width determination circuit 26 and the gate width control circuit 27 of the synchronization protection circuit of FIG. 15 can be provided in the synchronization protection circuit of FIG. Further, when the synchronization protection circuit of FIG. 32 is used for the second synchronization protection circuit, the circuit for removing synchronization (the protection counter 21, the OR circuit 27 and the flip-flop circuit 19) can be removed, and the second protection circuit can be removed.
The circuit scale of the synchronization protection circuit 31 can be reduced.

Next, the case where the same circuits as the synchronization protection circuit of FIG. 28 are used for the first synchronization protection circuit 29 and the second synchronization protection circuit 31 of FIG. 29 will be described.

FIG. 33 shows the first synchronization protection circuit 2 of FIG.
It is a schematic block diagram which shows an example of the synchronization protection circuit which can be used for 9 and the 2nd synchronization protection circuit 31.

The synchronization protection circuit of FIG. 33 is obtained by providing a transition circuit 41 in the configuration of the synchronization protection circuit of FIG. Therefore, the operation of the synchronization protection circuit of FIG. 33 is similar to the operation of the synchronization protection circuit of FIG. 28, and therefore the difference will be mainly described.

When the synchronization protection circuit of FIG. 33 is used as the first synchronization protection circuit 29 of FIG. 29, when the synchronization timing of the second synchronization protection circuit 31 is correct, the transition circuit 41
Receives the transition signal TS ₁ (corresponding to the transition signal TS of FIG. 29) from the second synchronization protection circuit 31, sets the synchronization timing of the initial synchronization circuit 3 to the synchronization timing of the second synchronization protection circuit 31, and adds 25 and the protection counter 21 are reset. In this case, it is assumed that there is no signal TS ₂ from the protection counter 21.

When the synchronization protection circuit of FIG. 33 is used as the second synchronization protection circuit 31 of FIG. 29, when the synchronization timing of the second synchronization protection circuit is correct, the protection counter 21
Outputs a transition signal TS ₂ (corresponding to the transition signal TS in FIG. 29) to the first synchronization protection circuit 29. In this case, the transition circuit 41 and the signal TS ₁ are not provided.

Further, in the synchronization protection circuit of FIG. 33, a circuit for removing synchronization (difference signal output circuit 7, gate 23,
The adder 25, the OR circuit 17, and the flip-flop circuit 19) can be removed, and the second synchronization protection circuit 31
The circuit scale of can be reduced. In addition, the first synchronization protection circuit 29 and the second synchronization protection circuit 31 have the same configuration as in FIG.
When the synchronization protection circuit of No. 3 is used, the gate width determination circuit 26 and the gate width control circuit 27 of the synchronization protection circuit of FIG. 19 can be provided.

As described above, in the synchronization protection system of the fifth embodiment of the present invention, when the synchronization timing of the second synchronization protection circuit is more correct than the synchronization timing of the first synchronization protection circuit, the second synchronization At the same time when it is determined that the synchronization timing of the protection circuit is correct, the synchronization timing of the first synchronization protection circuit is set to the synchronization timing of the second synchronization protection circuit. Therefore, in the synchronization protection system according to the fifth embodiment, it is possible to eliminate the time required for the initial synchronization of the first synchronization protection circuit, and it is possible to match the correct synchronization timing at high speed. Further, in the synchronization protection system according to the fifth embodiment, there is no initial synchronization process of the first synchronization protection circuit, so there is no risk of mistakenly synchronizing at the wrong position again.

Furthermore, the synchronization protection system according to the fifth embodiment has the same effect as the synchronization protection system according to the fourth embodiment.

[0283]

As described above, in the synchronization protection system according to the first aspect of the present invention, since the synchronization is protected by using the two synchronization protection means that synchronize at different synchronization timings,
In the first synchronization protection means, it is possible to prevent erroneous synchronization with a correlation output signal based on autocorrelation and cross-correlation.

In the synchronization protection system of claim 2,
The second synchronization timing in the second synchronization protection means is
When the first synchronization timing in the first synchronization protection means is correct, the first synchronization timing is set to the second synchronization timing, so that the time required for the initial synchronization of the first synchronization protection means can be shortened. , It is possible to synchronize the correlation output signal at the correct position at high speed.

Further, in the synchronization protection system of the second aspect, since the synchronization is protected by using the two synchronization protection means that synchronize at different synchronization timings, the first synchronization protection means is based on the autocorrelation and the cross-correlation. It is possible to prevent erroneous synchronization with the correlation output signal.

In the synchronization protection system of claim 3,
Since it is not necessary to provide means for breaking the synchronization in the second synchronization protection means, it is possible to reduce the circuit scale of the second synchronization protection means.

Further, in the synchronization protection system of the third aspect, since the synchronization is protected by using the two synchronization protection means which synchronize at different synchronization timings, the first synchronization protection means is based on the autocorrelation and the cross-correlation. It is possible to prevent erroneous synchronization with the correlation output signal.
Alternatively, in the synchronization protection system of claim 3, the second
The second synchronization timing in the synchronization protection means of
Since the first synchronization timing is set to the second synchronization timing when the first synchronization timing in the synchronization protection means is correct, the time required for the initial synchronization of the first synchronization protection means can be shortened and the high speed can be achieved. In addition, the correlation output signal can be synchronized at the correct position.

In the synchronization protection system of claim 4,
The actual addition value in the first adding means and the second adding means in the first synchronization protection means is approximated to the addition value when the difference signal and the correlation output signal having no level fluctuation due to ideal noise are input. It becomes a thing.

As a result, in the synchronization protection system according to claim 4, the first synchronization protection means has the first target value of the first addition means, the second target value of the second addition means, and the synchronization acquisition means. The predetermined condition in can be finely set, that is, the degree of freedom in design is increased and the synchronization performance can be improved.

In the synchronization protection system of claim 5,
In the first synchronization protection means, the actual addition value in the adding means approximates to the ideal addition value when a correlation output signal having no level fluctuation due to noise is input.

As a result, in the synchronization protection system of the fifth aspect, the first synchronization protection means can finely set the predetermined target value of the addition means and the predetermined condition of the synchronization acquisition means, that is, the degree of freedom in design. Can be increased and the synchronization performance can be improved.

In the synchronization protection system of claim 6,
In the first protection means, the actual addition value in the addition means is
It is an approximation of the ideal addition value of the difference signal with no level fluctuation due to noise.

As a result, in the synchronization protection system of the sixth aspect, the first synchronization protection means can finely set the predetermined target value of the addition means and the predetermined condition of the synchronization acquisition means, that is, the degree of freedom in design. Can be increased and the synchronization performance can be improved.

In the synchronization protection system of claim 7,
In the second synchronization protection means, the first addition means and the second addition means
The actual added value in the adding means is approximate to the ideal added value when the difference signal and the correlation output signal having no level fluctuation due to noise are input.

As a result, in the synchronization protection system according to claim 7, the second synchronization protection means has the first target value of the first addition means, the second target value of the second addition means, and the synchronization acquisition means. The predetermined condition in can be finely set, that is, the degree of freedom in design is increased and the synchronization performance can be improved.

In the synchronization protection system of claim 8,
In the second synchronization protection means, the actual added value in the adding means approximates to the ideal added value when a correlation output signal having no level fluctuation due to noise is input.

As a result, in the synchronization protection system according to the eighth aspect, the second protection means can finely set the predetermined target value of the addition means and the predetermined condition of the synchronization acquisition means, that is, the degree of freedom in design is increased. Therefore, the synchronization performance can be improved.

In the synchronization protection system of claim 9,
In the second synchronization protection means, the actual addition value in the addition means becomes close to the ideal addition value of the difference signal without level fluctuation due to noise. As a result, in the synchronization protection system according to claim 9, In the second synchronization protection means, the predetermined target value of the addition means and the predetermined condition of the synchronization acquisition means can be finely set, that is, the degree of freedom in design is increased and the synchronization performance can be improved.

In the synchronization protection system of the tenth aspect, in the second synchronization protection means, the actual addition value in the addition means is the addition when a correlation output signal having no level fluctuation due to ideal noise is input. It is close to the value.

As a result, in the synchronization protection system according to the tenth aspect, the second synchronization protection means can finely set the predetermined target value and the predetermined condition in the synchronization acquisition means, that is, the degree of freedom in design is increased. , The synchronization performance can be improved.

In the synchronization protection system of the eleventh aspect, the first protection means outputs the difference signal and the correlation output signal,
Since each of them is added with an arbitrary time width, the multipath can be strengthened and stable synchronization protection can be performed.

In the synchronization protection system according to the twelfth aspect, since the first synchronization protection means adds the correlation output signals with an arbitrary time width, the multipath can be strengthened and stable synchronization protection can be achieved. Can be done.

In the synchronization protection system according to the thirteenth aspect, since the first synchronization protection means adds the difference signals with an arbitrary time width, multipath can be strengthened and stable synchronization protection can be performed. it can.

In the synchronization protection system of the fourteenth aspect, since the second synchronization protection means adds the difference signal and the correlation output signal with arbitrary time widths,
It can be made strong against multipath and stable synchronization protection can be performed.

In the synchronization protection system of the fifteenth aspect, since the second synchronization protection means adds the correlation output signals with an arbitrary time width, multipath can be strengthened and stable synchronization protection can be achieved. Can be done.

[0306] In the synchronization protection system according to claim 16,
Since the second synchronization protection means adds the difference signals with an arbitrary time width, the multipath can be strengthened and stable synchronization protection can be performed.

According to the seventeenth aspect of the present invention, in the first synchronization protection means, even if the correlation output signal spreads backward in time, it is possible to achieve synchronization at the maximum received power and to stabilize. Synchronization protection can be performed.

In the synchronization protection system of the eighteenth aspect, the first synchronization protection means adjusts the time width setting means so that the integral of the correlation output signal is maximized, so that the effect of PDI can be improved. It is possible to enable stable synchronization protection.

According to the nineteenth aspect of the present invention, in the second aspect of the second aspect of the present invention, even if the correlation output signal spreads backwards in time, the second synchronizing means can synchronize at the maximum received power and stabilize. Synchronization protection can be performed.

In the synchronization protection system according to the twentieth aspect, since the second synchronization protection means adjusts the time width setting means so that the integral of the correlation output signal is maximized, the PD
The effect of I can be improved, and stable synchronization protection can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a synchronization protection circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection circuit of FIG.

FIG. 3 is a diagram showing a timing at which a first gate and a second gate of FIG. 1 are turned on / off for each spreading code period.

FIG. 4 is a diagram showing an example of waveforms of a correlation output signal C and a difference signal D in FIG.

FIG. 5 is a diagram for explaining a predetermined reference value B shown in FIG.

FIG. 6 is a diagram showing the relationship between the signals input to the first adder and the second adder of FIG. 1 and the amount of addition thereof.

7 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection circuit of FIG.

8 is a diagram showing a relationship between an addition amount and time in the second adder of FIG.

FIG. 9 is a diagram showing an example of a waveform of a multipath signal.

FIG. 10 is a schematic block diagram showing a modification of the synchronization protection circuit of the first embodiment shown in FIG. 1, which can effectively deal with multipath signals.

FIG. 11 is a schematic block diagram showing a synchronization protection circuit according to a second embodiment of the present invention.

12 is a diagram showing the relationship between the addition amount of the adder and the count number of the protection counter when the synchronization protection circuit of FIG. 11 is synchronized at the correct position.

13 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection circuit of FIG.

14 is a diagram showing a relationship between an addition amount of an adder and a count number of a protection counter when the synchronization protection circuit of FIG. 11 is synchronized at an incorrect position.

FIG. 15 is a schematic block diagram showing a modification of the synchronization protection circuit of the second embodiment shown in FIG. 11, which can effectively deal with multipath signals.

FIG. 16 is a schematic block diagram showing a synchronization protection circuit according to a third embodiment of the present invention.

17 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection circuit of FIG.

18 is a diagram showing the relationship between the addition amount of the adder and the count number of the protection counter of the synchronization protection circuit of FIG.

FIG. 19 is a schematic block diagram showing a modification of the synchronization protection circuit of the third embodiment shown in FIG. 16, which can effectively deal with multipath signals.

FIG. 20 is a schematic block diagram showing a synchronization protection system according to a fourth embodiment of the present invention.

21 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

22 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection system of FIG.

23 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection system of FIG.

24 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

25 is a diagram showing an example of a waveform of a correlation output signal C input to the synchronization protection system of FIG.

26 is a diagram showing the relationship between the addition amount of the adders in the first synchronization protection circuit and the second synchronization protection circuit and time in the synchronization protection system of FIG.

27 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

28 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

FIG. 29 is a schematic block diagram showing a synchronization protection system according to a fifth embodiment of the present invention.

30 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

FIG. 31 is a schematic block diagram showing an example of a sync protection circuit that can be used in the sync protection system of FIG. 29.

32 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

33 is a schematic block diagram showing an example of a synchronization protection circuit that can be used in the synchronization protection system of FIG.

FIG. 34 is a schematic block diagram showing a part of a receiver of a general spread spectrum communication system.

FIG. 35 is a schematic block diagram showing a conventional synchronization protection circuit.

36 is a diagram showing an example of a waveform of a correlation output signal C input to the conventional synchronization protection circuit of FIG. 35.

FIG. 37 is a diagram showing the relationship between the count number of the positive lock counter of the conventional synchronization protection circuit of FIG. 35 and time.

[Explanation of symbols]

 1 discriminator 3 initial synchronization circuit 5 synchronization counter 7 difference signal output circuit 9 first gate 11 first adder 13 second gate 15 second adder 17 OR circuit 19 flip-flop circuit 21 protection counter 23 gate 25 adder 26 gate Width determination circuit 27 Gate width control circuit 28 Demodulation circuit 29 First synchronization protection circuit 31 Second synchronization protection circuit 32 Cycle counter 33 AND circuit 35 False lock counter 37 Logic gate 39 Positive lock counter 41 Transition circuit 43 Distributor 45, 47 Multiplier 49, 51 Correlator 53 Local signal generator 55 Square sum circuit 57 Synchronization protection circuit

Claims (20)

[Claims] 1. A synchronization protection system for protecting synchronization of correlation timing using a correlation output signal based on a signal from a correlator that performs correlation with a spread code in a receiver of a spread spectrum communication system, wherein the correlation First synchronization protection means for protecting synchronization at a first synchronization timing using an output signal and returning to an initial state in response to a predetermined signal; and using the correlation output signal for the first synchronization timing The synchronization of the correlation output signal that protects the synchronization at the different second synchronization timing and that is synchronized at the second synchronization timing is the first synchronization protection means.
Second synchronization protection means for outputting the predetermined signal for returning the first synchronization protection means to the initial state when the correlation is larger than the correlation of the correlation output signal synchronized at the synchronization timing of. , Synchronization protection system. 2. A synchronization protection system for protecting synchronization of correlation timing using a correlation output signal based on a signal from a correlator that performs correlation with a spread code in a receiver of a spread spectrum communication system, wherein the correlation First synchronization protection means for protecting synchronization at a first synchronization timing by using an output signal, and synchronization protection at a second synchronization timing different from the first synchronization timing by using the correlation output signal. The output signal in which the correlation between the second synchronization protection means and the correlation output signal synchronized at the second synchronization timing is synchronized at the first synchronization timing in the first synchronization protection means. And a timing transition means for setting the first synchronization timing of the first synchronization protection means to the second synchronization timing when the correlation is larger than the correlation of Sync protection system. 3. A synchronization protection system for protecting synchronization of correlation timing by using a correlation output signal based on a signal from a correlator that performs correlation with a spread code in a receiver of a spread spectrum communication system, wherein: First synchronization protection means for protecting synchronization at a first synchronization timing by using an output signal, and synchronization protection at a second synchronization timing different from the first synchronization timing by using the correlation output signal. The correlation output of the second synchronization protection means and the correlation of the correlation output signal synchronized at the second synchronization timing is synchronized at the first synchronization timing by the first synchronization protection means. When the correlation of the signal is larger than the correlation, the first synchronization protection means is returned to the initial state, or the first synchronization timing of the first synchronization protection means is set to the second synchronization timing. The synchronization timing of the correlation output signal is synchronized with the first synchronization timing. A reset signal for returning the second synchronization protection unit to an initial state when the correlation is larger than the correlation of the correlation output signal synchronized at the synchronization timing of the second synchronization protection unit. A synchronization protection system that returns to the initial state by. 4. The first synchronization protection means uses the correlation output signal satisfying a predetermined condition to perform a synchronization acquisition means and a difference between a predetermined reference value and the correlation output signal. A first addition that obtains and outputs a difference signal output unit that outputs a difference signal and a first target value, and sequentially adds the difference signals that match the first synchronization timing captured by the synchronization capturing unit. Means, second adding means for sequentially adding the correlation output signals having a second target value and matching the first synchronization timing, and an addition value of the first adding means or the second adding means. 4. Any one of claims 1 to 3, further comprising: a determination unit that determines whether or not the synchronization is normal, depending on whether any one of the added values of 1 reaches the first target value or the second target value earlier. The synchronization protection system according to item 1. 5. The first synchronization protection means has a synchronization acquisition means for performing synchronization acquisition by using the correlation output signal satisfying a predetermined condition, and a predetermined target value, and is acquired by the synchronization acquisition means. And a correlation output signal that has a predetermined target number and that satisfies the predetermined condition that matches the first synchronization timing. Whether the synchronization is normal or not, depending on the counting means for counting, and whether the addition value of the adding means or the count value of the counting means reaches the predetermined target value or the predetermined target number earlier. The synchronization protection system according to any one of claims 1 to 3, further comprising: a determination unit that determines 6. The first synchronization protection means obtains a difference between a predetermined reference value and the correlation output signal, and a synchronization acquisition means for performing synchronization acquisition using the correlation output signal satisfying a predetermined condition. A difference signal outputting means for outputting a difference signal; an adding means having a predetermined target value and sequentially adding the difference signals in synchronization with the first synchronization timing captured by the synchronization capturing means; Counting means for counting the correlation output signals having the target number and satisfying the predetermined condition that matches the first synchronization timing, and either the added value of the adding means or the counted value of the counting means. 4. The synchronization protection according to claim 1, further comprising: a determination unit that determines whether or not synchronization is normal depending on whether the predetermined target value or the predetermined target number is reached earlier. system. 7. The second synchronization protection means uses the correlation output signal satisfying a predetermined condition to perform a synchronization acquisition means and a difference between a predetermined reference value and the correlation output signal. A first addition for obtaining the difference signal and outputting the difference signal sequentially, and having the first target value, and sequentially adding the difference signals that match the second synchronization timing captured by the synchronization capturing means. Means, second adding means for sequentially adding the correlation output signals having a second target value and matching the second synchronization timing, and an addition value of the first adding means or the second adding means. 4. Any one of claims 1 to 3, further comprising: a determination unit that determines whether or not the synchronization is normal, depending on whether any one of the added values of 1 reaches the first target value or the second target value earlier. The synchronization protection system according to item 1. 8. The second synchronization protection means has a synchronization acquisition means for performing synchronization acquisition using the correlation output signal satisfying a predetermined condition, and a predetermined target value, and is acquired by the synchronization acquisition means. Done second
Adder means for sequentially adding the correlation output signals matching the synchronization timing, and counting the correlation output signals having a predetermined target number and satisfying the predetermined condition matching the second synchronization timing. A judgment for judging whether or not the synchronization is normal, depending on which of the counting means and the addition value of the adding means or the counting value of the counting means reaches the predetermined target value or the predetermined target number earlier. A synchronization protection system according to any one of claims 1 to 3, including means. 9. The second synchronization protection means obtains the difference between a predetermined reference value and the correlation output signal, and a synchronization acquisition means for performing synchronization acquisition using the correlation output signal satisfying a predetermined condition. A difference signal output means for outputting a difference signal, and a second target having a predetermined target value and captured by the synchronization capturing means.
Counting means for sequentially adding the difference signals matching the synchronization timing, and counting a correlation output signal having a predetermined target number and satisfying the predetermined condition matching the second synchronization timing. Determining means for determining whether or not the synchronization is normal, depending on whether the predetermined target value or the predetermined target number, whichever of the addition value of the adding means or the count value of the counting means, is reached earlier. The synchronization protection system according to claim 1, further comprising: 10. The second synchronization protection means uses the correlation output signal satisfying a predetermined condition to perform synchronization acquisition means, and the second synchronization timing acquired by the synchronization acquisition means. 4. The synchronization protection system according to claim 3, further comprising: an addition unit that sequentially adds the correlation output signals that match the above, and a determination unit that determines whether or not synchronization is normal based on the added value of the addition unit. 11. The first synchronization protection unit sets an arbitrary time width, and the difference signal and the correlation output signal of the set time width are respectively set to the first addition unit and the second addition. The synchronization protection system according to claim 4, further comprising a time width setting means for outputting to the means. 12. The first synchronization protection means further comprises time width setting means for setting an arbitrary time width and outputting the correlation output signal having the set time width to the adding means. Item 6. The synchronization protection system according to item 5. 13. The first synchronization protection means further comprises time width setting means for setting an arbitrary time width and outputting the difference signal having the set time width to the adding means. 6. The synchronization protection system according to 6. 14. The second synchronization protection unit sets an arbitrary time width, and the difference signal and the correlation output signal are respectively set to the first addition unit and the second addition in the set time width. 8. The synchronization protection system according to claim 7, further comprising time width setting means for outputting to the means. 15. The second synchronization protection means further comprises time width setting means for setting an arbitrary time width and outputting the correlation output signal to the adding means at the set time width. Item 11. The synchronization protection system according to item 8 or 10. 16. The second synchronization protection means further comprises time width setting means for setting an arbitrary time width and outputting the difference signal to the adding means at the set time width. 9. The synchronization protection system according to item 9. 17. The time width setting means sets a peak timing of the correlation output signal that matches the first synchronization timing in the arbitrary time width.
The synchronization protection system according to any one of claims 11 to 13, wherein the later time period is wider than the previous time period. 18. The first synchronization protection means further comprises an adjusting means for adjusting the time width setting means so that the integral of the correlation output signal in the arbitrary time width becomes maximum. 14. The synchronization protection system according to any one of items 11 to 13. 19. The time width setting means sets, with respect to a peak timing of the correlation output signal that matches the second synchronization timing, of the arbitrary time width,
17. The synchronization protection system according to claim 14, wherein the later time period is wider than the previous time period. 20. The second synchronization protection means further comprises an adjusting means for adjusting the time width setting means so that the integration of the correlation output signal in the arbitrary time width is maximized. The synchronization protection system according to any one of 14 to 16.