JPH08287136A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a wiring design method suitable for high-speed logic integrated circuit devices, etc., which are extremely miniaturized and have large capacities, and to speed up the process and reduce the chip size. Constitution: Among the signal paths included in a high speed logic integrated circuit device such as a gate array, especially the inter-block signal lines arranged over a relatively long distance, as shown in FIG. A wide wiring having a wiring width that is, for example, three times the basic pitch p of the wiring channel, that is, 3p, which is provided in a three-quarter section on the gate G1 side, and a basic pitch provided in a one-fourth section on the sink gate G2 side. A combination wiring including a normal width wiring having a wiring width p is used. With this, compared to the case where the entire width is set to the wiring width,
The average number of required wiring channels is reduced while equalizing or shortening the transmission delay time of signal lines between blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is particularly effective when used for a high-speed logic integrated circuit device having a bipolar transistor (hereinafter abbreviated as a transistor) as a basic element and its signal path wiring design. It is about technology.

[0002]

2. Description of the Related Art There is a high speed logic integrated circuit device such as a gate array having a transistor as its basic element. Further, there is an automatic placement and routing design system for automatically designing the placement of circuit elements and wiring of a high speed logic integrated circuit device or the like by a computer.

[0003]

In the conventional automatic placement and routing design system used for placement design of high-speed logic integrated circuit devices and the like, most signal paths except DC wiring such as power supply paths are the basis of wiring channels. It is composed of a so-called normal width wiring having a wiring width of ½ of the pitch, and a normal wiring is used for a clock signal line which requires particularly good transmission characteristics and a block-to-block signal line which is routed over a relatively long distance. A wide wiring having a wiring width that is a multiple of the wiring width is assigned.
That is, in the conventional automatic placement and routing design system, although different wiring types are used, all sections of the signal path including the clock signal line and the inter-block signal line have the same wiring width. The wiring width is not intentionally changed midway. This has not been a problem in conventional high-speed logic integrated circuit devices, etc., which are not miniaturized or scaled up so much, but in recent years when the miniaturization or scale-up is remarkable, it is not always an optimum solution, and high-speed logic integrated circuits It has been clarified by the inventors of the present application that there are restrictions on the speedup of the device and the reduction of the chip size.

An object of the present invention is to provide a wiring design method suitable for a high-speed logic integrated circuit device or the like which is remarkably miniaturized and has a large scale. Another object of the present invention is to increase the speed of a high-speed logic integrated circuit device or the like and reduce the chip size thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, among the signal paths included in a high-speed logic integrated circuit device such as a gate array, the inter-block signal lines, which are routed over a relatively long distance, are provided on the source gate side thereof and have a predetermined basic pitch of the wiring channels. A wide wiring having a wiring width of several times and a normal width wiring provided on the sink gate side and having a basic pitch as the wiring width are combined at a predetermined ratio in the extension direction.

[0007]

According to the above means, the average required number of wiring channels can be reduced while making the transmission delay time of the signal lines between blocks equal or shorter than the case where the entire section is composed of wide wiring. Can be reduced. As a result, it is possible to realize a wiring design method suitable for a high-speed logic integrated circuit device or the like which is extremely miniaturized and large-scaled, and it is possible to increase the speed of the high-speed logic integrated circuit device and reduce the chip size.

[0008]

1 is a block diagram showing an embodiment of a signal path included in a high speed logic integrated circuit device (semiconductor device) to which the present invention is applied. 2 shows a connection diagram of an embodiment for explaining various connection forms between the source gate G1 and the sink gate G2 of FIG. 1, and FIG. 3 describes layout images of the various connection forms. A conceptual diagram of an embodiment for doing so is shown. Further, FIG. 4 shows an equivalent circuit diagram of one embodiment of the various connection forms of FIG. 2, and FIG. 5 is a diagram for explaining the relationship between the wiring length and the transmission delay time of the various connection forms. A characteristic diagram of one embodiment is shown. Based on these figures, the basic configuration and connection form of the high-speed logic integrated circuit device of this embodiment and its features will be described. Each circuit element shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known bipolar integrated circuit manufacturing technique together with other circuit elements (not shown) of the high speed logic integrated circuit device. Further, the characteristic diagram of FIG. 5 is obtained as a result of the computer simulation performed by the inventors of the present application for a gate having a relatively large driving capability.

In FIG. 1, the high-speed logic integrated circuit device of this embodiment has a source gate G1 which receives at its input node the output signal of the preceding stage circuit (not shown), that is, the input signal Si.
Based on the signal path, that is, the wiring WL that transmits the output signal of the source gate G1 and the wiring width and the wiring length of which are W and L, respectively, and the output signal of the source gate G1 transmitted through this wiring WL. And a sync gate G2 for forming a predetermined output signal So and transmitting it to a not-shown subsequent circuit of the high speed logic integrated circuit device.

Here, the source gate G1 is not particularly limited, but a current switch circuit centered on the differential transistors T1 and T2, a transistor T3 and a resistor R.
And an emitter follower circuit composed of three. this house,
The collectors of transistors T1 and T2 are coupled to ground potential GND via corresponding resistors R1 or R2, and their commonly coupled emitters are coupled to power supply voltage VEE via a predetermined constant current source S1. Also, the transistor T
The base of 1 is coupled to the input node of the source gate G1 to be supplied with the input signal Si, and the base of the transistor T2 is supplied with a predetermined reference voltage VBB. further,
The collector of the transistor T2 is coupled to the base of the transistor T3 forming the emitter follower circuit, and the emitter of the transistor T3 is coupled to the output node of the source gate G1.

As a result, the output signal of the source gate G1 has a high level lower than the ground potential GND by the base-emitter voltage of the transistor T3 constituting the emitter follower circuit when the input signal Si is at a high level higher than the reference voltage VBB. And the input signal Si is set to the reference voltage V
When the low level is lower than BB, the predetermined low level is lower than the low level determined by the current value of the constant current source S1 and the resistance value of the resistor R2 by the base-emitter voltage of the transistor T3. The sink gate G2 has the same configuration as the source gate G1 and selectively sets the output signal So to a predetermined high level according to the output signal of the source gate G1.

Next, the wiring WL provided between the source gate G1 and the sink gate G2 can take, for example, five types of connection forms shown in FIG. That is, as shown in FIG. 2 (a), the first is a connection mode by a so-called normal width wiring in which the basic pitch p of the wiring channels is the wiring width W, and the second is a connection form. As shown by, for example, 3 times the basic pitch p, that is, 3p is set to the wiring width W.
It is a connection form using wide wiring. In this embodiment, the wiring length L between the source gate G1 and the sink gate G2 is 4 which is the basic wiring length g assumed as a unit of the wiring length.
In other words, in the connection form of FIGS. 2A and 2B, the wiring width is the same in all sections having a wiring length of 4 g. Further, in the automatic placement / wiring design system for which the high-speed logic integrated circuit device of this embodiment is designed, wiring channels are assumed at the basic pitch p as shown in FIG. 3, and wiring is performed along these wiring channels. The placement is done.

Therefore, the normal width wiring shown in FIG.
As shown in FIG. 3A, one of the wiring channels having the basic pitch p is exclusively arranged, and both ends thereof are connected to the output node G1out of the source gate G1 or the sink gate G2 via predetermined connection wirings. Input node G2in
Respectively combined with. As shown in FIG. 3B, the wide wiring shown in FIG. 2B is arranged so as to occupy three wiring channels, that is, two wirings having a normal width including a space between the wirings. Both ends are similarly connected to the output node G1out of the source gate G1 via a predetermined connection wiring.
Alternatively, they are respectively coupled to the input node G2in of the sink gate G2. As a result, when the connection form of FIG. 2A is represented by an equivalent circuit, as shown in FIG. 4A, the entire section has the unit resistance value Rn and the unit capacitance value Cn of the normal width wiring.
2B is a serial-parallel circuit composed of
As shown in FIG. 4B, the entire section is a serial / parallel circuit including the unit resistance value Rb and the unit capacitance value Cb of the wide wiring.

On the other hand, in the third connection form, as shown in FIG. 2C, the wiring length L1 of one quarter, that is, g close to the source gate G1 in the extension direction is three times the basic pitch, that is, 3p. Wide wiring with the wiring width W1 (first wiring)
And the wiring length L2 of the remaining three quarters close to the sink gate G2, that is, 3g is a normal width wiring (second wiring) having the basic pitch p as the wiring width W2, so to speak, a connection form by a 1: 3 combination wiring Is. The fourth is shown in FIG.
As shown in (d), the half of the wiring length L1 close to the source gate G1, that is, 2g is 3p, and the wiring width W is 3p.
This is a connection form of 1: 1 combination wiring, which is a wide wiring having a width of 1 and a wiring width L2 that is a half of the wiring close to the sink gate G2, that is, 2g is a normal width wiring having a wiring width W2. Further, as shown in FIG. 2 (e), the fifth is a three-quarter wiring length L1 close to the source gate G1, that is, a wide wiring having a wiring width W1 of 3g at 3g, and a sink gate G2. Wiring length L2 close to 1/4
In other words, g is a connection form of 3: 1 combination wiring, which is a normal width wiring having a wiring width W2 of p.

Among them, the combination wiring of FIG. 2C has its source gate G1 as shown in FIG. 3C.
Of the output node G1out is occupied by three wiring channels, and the other three quarters of the sink gate G2 near the input node G2in are occupied by one wiring channel. In the combination wiring of FIG. 2D, as shown in FIG. 3D, one half of the source gate G1 close to the output node G1out is arranged exclusively for three wiring channels, and the sink gate is formed. The other half, which is close to the input node G2in of G2, is arranged so as to occupy one wiring channel. Further, in the combination wiring of FIG. 2 (e), as shown in FIG. 3 (e), three-quarters of the source gate G1 near the output node G1out are arranged so as to occupy three wiring channels and sink. The remaining quarter near the input node G2in of the gate G2 is arranged exclusively for one wiring channel.

From the above, when the combination wiring of FIG. 2C is represented by an equivalent circuit, as shown in FIG. 4C, a quarter of the section is the unit resistance value Rb of the wide wiring and The serial-parallel circuit has the unit capacitance value Cb, and the remaining three-quarters section is the serial-parallel circuit having the unit resistance value Rn and the unit capacitance value Cn of the normal width wiring. As shown in FIG. 4D, the combination wiring of FIG. 2D is a serial-parallel circuit in which one half of the section is composed of the unit resistance value Rb and the unit capacitance value Cb of the wide wiring, and the rest. A half section is a serial / parallel circuit having a unit resistance value Rn and a unit capacitance value Cn of the normal width wiring. Further, in the combination wiring of FIG. 2E, as shown in FIG. 4E, three-quarters of the section has a unit resistance value Rb and a unit capacitance value C of the wide wiring.
The serial-parallel circuit is composed of b, and the remaining quarter is a serial-parallel circuit composed of the unit resistance value Rn and the unit capacitance value Cn of the normal width wiring.

As is well known, the transmission delay time of the signal path starting from the input node of the source gate G1 and ending at the input node of the sink gate G2 is the delay time from the input node of the source gate G1 to the output node, that is, the circuit. It is obtained as the sum of the load delay and the delay time from the output node of the source gate G1 to the input node of the sink gate G2, that is, the wiring resistance delay. The value of the circuit load delay is determined by the load driving capability of the source gate G1 and the load capacitance coupled to its output node, that is, the sum of the wiring capacitance of the wiring WL and the input capacitance of the sink gate G2, and the value of the wiring resistance delay The value is mainly determined by the product of the wiring resistance and the wiring capacitance of the wiring WL. Further, assuming that the structure of the wiring WL in the thickness direction is constant, the unit resistance value Rn with respect to the wiring width W is
Is inversely proportional, the unit capacitance value Cn is directly proportional, and the wiring resistance delay is proportional to the square of the wiring length. However, since the fringe capacitance having substantially the same value is coupled to each wiring regardless of the wiring width W, the degree of reduction of the wiring capacitance with respect to the reduction of the wiring width W becomes gradually gradual. Therefore, the wiring width W
On the other hand, while reducing the value of the circuit load delay, which is determined by the wiring capacitance, gradually increases the value of the wiring resistance delay on the other side, apparently it is predominantly affected by the wiring resistance. Becomes

Here, the inventors of the present application performed a simulation for obtaining delay time characteristics of various connection configurations of FIG. 2 for a gate having a relatively large driving ability, and obtained the results of FIG. That is, the entire section is composed of normal width wiring.
In the connection form of (a), the wiring length is almost 2 for the above reason.
The transmission delay time increases in proportion to the power of the power, and its value is generally larger than that of other connection forms due to the influence of the wiring resistance, as shown by the dotted line in FIG. Further, in the connection form of FIG. 2B in which the entire section is composed of wide wiring, as shown by a thick solid line in FIG.
The transmission delay time becomes smaller as a whole as compared with the connection form of No. 1, and the difference becomes larger as the wiring length becomes longer. On the other hand, the ratio of the wide wiring is relatively small in FIG.
In the connection configurations of (c) and (d), as shown by the thin solid line in FIG. 5, the transmission delay time is generally smaller than that in the connection configuration of FIG. Although it is larger than that of the connection form, particularly in the connection form of FIG. 2E in which the ratio of the wide wiring and the normal width wiring is 3: 1,
It is equal to or smaller than that of (b).

By the way, in the connection form of FIG. 2 (e), as described above, three-quarters close to the output node of the source gate G1 are arranged so as to occupy two wiring channels, and the input of the sink gate G2 is set. The remaining one-quarter of the nodes are arranged to occupy one wiring channel. In other words, the connection form of FIG. 2 (e) can be arranged such that the quarter section near the input node of the sink gate G2 occupies only one wiring channel, which results in the transmission delay time. It is possible to reduce the average number of required wiring channels while reducing the number. As a result, it is possible to realize a wiring design method suitable for a high-speed logic integrated circuit device which is remarkably miniaturized and has a large scale, and it is possible to increase the speed of the high-speed logic integrated circuit device and reduce the chip size.

The operational effects obtained from the above embodiments are as follows. That is, (1) the inter-block signal line or the like that is routed over a relatively long distance among the signal paths included in a high-speed logic integrated circuit device such as a gate array is provided on the source gate side of the wiring channel A wide wiring having a wiring width that is a predetermined number of times the pitch and a normal width wiring that has the basic pitch as the wiring width and is provided on the sink gate side are combined at a predetermined ratio in the extension direction, so that the entire As compared with the case of using wide wiring, it is possible to obtain the effect that the average number of required wiring channels can be reduced while making the transmission delay time of the inter-block signal line or the like equal or shorter. (2) According to the above item (1), it is possible to obtain an effect that a wiring design method suitable for a high-speed logic integrated circuit device or the like that is extremely miniaturized and has a large scale can be realized. (3) According to the above items (1) and (2), it is possible to obtain an effect that the high speed logic integrated circuit device and the like can be speeded up and the chip size can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the source gate G1 and the sink gate G2 can have a plurality of input nodes, and the specific circuit configuration, the polarity of the power supply voltage, the conductivity type of the transistor, and the like are various embodiments. sell. In FIG. 2, the wiring width and the ratio of the wide wiring and the normal width wiring in each combination wiring can be set arbitrarily. Further, the number of wiring types forming the combination wiring is not particularly limited to two types of wide wiring and normal width wiring. In FIG. 3, the wiring width of the wide wiring has only to be substantially wide, and for example, a space between the wirings may be sandwiched between them. Also,
In this embodiment, the output node G1o of the source gate G1
The connection wirings for both ut and the input node G2in of the sink gate G2 are drawn out downward, but the direction thereof does not particularly limit the present invention. Further, the basic pitch p of the wiring channels is set to the same pitch so that the inter-wiring spaces between the adjacent wiring layers can be alternately provided, but this is not the case unless it is necessary because it is a single layer. .

In the above description, the invention mainly made by the present inventor is applied to a high-speed logic integrated circuit device having a bipolar transistor as a basic element and its inter-block signal line, which is the field of application of the invention. However, the present invention is not limited to this, and for example, various signal lines and M arranged over a relatively long distance can be used.
The present invention can also be applied to various logic integrated circuit devices including OSFETs (metal oxide semiconductor field effect transistors) as basic elements and computers including the same. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor device including a wiring routed over a relatively long distance and a system including such a semiconductor device.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, among the signal paths included in a high-speed logic integrated circuit device such as a gate array, the inter-block signal lines, which are routed over a relatively long distance, are provided on the source gate side thereof and have a predetermined basic pitch of the wiring channels. A wide wiring with a wiring width of several times and a normal width wiring with the basic pitch as the wiring width provided on the sink gate side are combined at a predetermined ratio in the extension direction, so that the entire wiring becomes wider. In comparison with the above case, the average number of required wiring channels can be reduced while equalizing or shortening the transmission delay time of the signal lines between blocks and the like. As a result, it is possible to realize a wiring designing method suitable for a high-speed logic integrated circuit device or the like that is extremely miniaturized and large-scaled, and thereby it is possible to speed up the high-speed logic integrated circuit device and reduce the chip size.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a signal path included in a high speed logic integrated circuit device to which the present invention is applied.

FIG. 2 is a connection diagram showing an embodiment for explaining various connection forms between the source gate and the sink gate of FIG.

FIG. 3 is a conceptual diagram showing an example for explaining layout images of various connection forms of FIG.

FIG. 4 is an equivalent circuit diagram showing an example of various connection forms of FIG.

5 is a characteristic diagram showing an example for explaining a relationship between a wiring length and a transmission delay time in various connection forms of FIG.

[Explanation of symbols]

Si ... Input signal, So ... Output signal, G1 ...
・ Source gate, G2 ... Sink gate, T1 to T3
... Bipolar transistor, S1 ... Constant current source,
R1 to R3 ... Resistance, WL ... Wiring. p: channel basic pitch, g: basic wiring length. G1out ...
An output node of the source gate G1, G2in ... An input node of the sink gate G2. Rn ... Unit resistance value of normal width wiring, Rb ... Unit resistance value of wide wiring, Cn ...
-Unit capacitance value of normal width wiring, Cb ... Unit capacitance value of wide wiring.

Claims (3)

[Claims] 1. A semiconductor device comprising a signal path formed by combining wirings having substantially different wiring widths in a predetermined ratio in the extension direction thereof. 2. The signal path includes a first wiring having a relatively wide wiring width provided on the source gate side and a second wiring having a relatively narrow wiring width provided on the sink gate side. The semiconductor device according to claim 1, wherein: 3. The first wiring has a wiring width which is a predetermined multiple of a basic pitch of wiring channels, and the second wiring has the basic pitch as its wiring width. The semiconductor device according to claim 2, wherein the semiconductor device is present.