JPH08286927A - Assembler processing method - Google Patents

Abstract

(57) [Abstract] [Purpose] In the assembler processing method, the processor-dependent information (peripheral resource information, instruction configuration information) can be dealt with flexibly in response to processor specification changes by not separating it from the assembler body. To provide. [Structure] A peripheral resource information file 101 and an instruction structure information file 102 are provided outside, and an assembler body 104 is provided.
In the processor information processing unit 105, the symbol information table 106 and the instruction configuration information table 107
And the assembly language expansion processing unit 108
Based on the table information, the object code of the assembly instruction word in the source file 103 is generated and the syntax is checked. [Effect] When the specifications of the processor are changed, the number of man-hours required for changing the assembler can be reduced, and the assembler for another processor can be handled with a slight change, thereby reducing the number of development man-hours.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an assembler processing system, and more particularly to an assembler processing system for a processor having a dedicated architecture.

[0002]

2. Description of the Related Art Conventionally, in the assembler processing system,
Peripheral resource information and instruction configuration information that are processor-specific information are incorporated in the assembler as assembler-specific information. In this case, when the specification of the processor is changed, it is necessary to reconstruct the assembler (correct the program). For such an assembler processing method, for example, "Assembler assemble processing method"
(Japanese Patent Publication No. 3-53333).

[0003]

The development of controlware (hereinafter referred to as "C / W") for controlling a dedicated processor is generally performed in parallel with hardware.
/ W There is a high possibility that hardware specifications will change during development. In this case, it is necessary to change the assembler as well as the C / W. The change work must be carried out in a short period of time and the assembler system must be provided to the C / W designer.

Therefore, in the above-mentioned conventional technique, it is necessary to reconstruct the assembler, and the time and period required for the change become large.

An object of the present invention is to provide an assembler capable of flexibly coping with a specification change of a processor by separating processor-dependent information (peripheral resource information, instruction configuration information) from the assembler body without incorporating it. .

[0006]

According to the present invention, a file defining peripheral resource information, a file defining instruction configuration information, a means for analyzing peripheral resource information and registering it in a table, and an instruction configuration information A means for analyzing and registering in a table, a means for converting a source program into an object code based on the table group, and a means for checking the syntax rule of the source program based on the table group are provided.

[0007]

According to the above means, the file in which the peripheral resource information is defined is composed of the resource name, the conversion code and the resource attribute indicating the type of resource. The file defining the instruction configuration information is composed of assembly instruction word names, conversion codes, object code formats and syntax rule information. These files are input by an editor, and can be easily changed.

The means for analyzing the peripheral resource information and registering it in the table and the means for analyzing the instruction structure information and registering it in the table check whether or not the definition information in the file is described in a prescribed format, and define it. Register information in the table. By repeating the processing for all the definition information, the processor-specific information is registered in the assembler.

The means for converting the source program into an object code and the means for checking the syntax rules search the above table using each element (assembly instruction word, peripheral resource information, etc.) decomposed by the syntax decomposition process as a search key, Convert to object code and check syntax according to table information. An assembler system capable of flexibly coping with the specification change of the processor is realized by the processing method.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the present invention. In the figure, 101 is a peripheral resource information file that defines peripheral resource information, 102 is an instruction configuration information file that defines instruction configuration information, 103 is a source file that stores a source program, 104 is an assembler body, and 105 is peripheral resource information. A processor information processing unit that reads and analyzes the file 101 and the instruction configuration information file 102 and registers them in the table, 106 is a symbol information table that stores the peripheral resource information analyzed by the processor information processing unit 105, and 107 is a processor information processing unit 105. An instruction configuration information table storing the analyzed instruction configuration information, 108 reads the source file 103, analyzes it,
Symbol information table 106 and instruction structure information table 1
An assembly language expansion processing unit for performing object code generation and syntax check based on 07, 109 is a file output unit for outputting the object code generated by the assembly language expansion processing unit 108 and a source list to each file, and 110 is an accumulation of the object code. The object file 111 is a list file for accumulating the source list.

In the assembler body 104, the processor information processing unit 105 is executed to register the processor-specific information in the assembler, and then the assembly language expansion processing unit 108 is executed to generate the object code and check the syntax. It will be possible. Further, the file output unit is not directly related to the present invention, and therefore its explanation is omitted.

FIG. 2 shows the relationship between the peripheral resource information file 101 and the symbol information table 106 in the processor information processing unit 105. The peripheral resource information file 101 is composed of a resource name, a conversion code, and a resource attribute (coding) indicating the type of resource. The first example in this figure shows the resource name "REG1"
Indicates that the conversion code is “(10) ₁₆ ” and the resource attribute is “register”.

The symbol information table 106 stores these pieces of information, and at the same time, the assembly language expansion processing unit 1
In addition to the peripheral resource information processed in 08, branch destination label information defined in the source file 103 is also stored. Further, when a symbol (peripheral resource information, branch destination label information, etc.) is registered in the symbol information table 106, name duplication check is performed.

FIG. 3 shows the relationship between the instruction configuration information file 102 and the instruction configuration information table 107 in the processor information processing unit 105. The instruction configuration information file 102 is composed of an assembly instruction word name, a conversion code, an object code format (instruction length and storage position of each code), and syntax rule information (operand attribute). In the example of this figure, the assembly instruction word name “ADD” has a conversion code of “(10) ₁₆ ”, an object code format of “4 byte instruction, and the instruction code is stored in the range of 0 byte to 1 byte. , The first operand code is stored in the range from the first byte to 1 byte, and the second operand code is 2
Stored in the range of 1 byte from the byte ”, the syntax rule information is" register is described in the first operand and register is described in the second operand ".

The instruction structure information table 107 stores these pieces of information. When registering a command word in the command configuration information table 107, a name duplication check is performed.

The peripheral resource information file 101 and the instruction configuration information file 102 can be input by an editor, and can be easily changed.

FIG. 4 is a flow chart of object code generation and syntax check processing in the assembly language expansion processing unit 108. This assembler is an example of a two-pass assembler, and it is premised that all symbol information in the source file 103 is analyzed in the first pass and registered in the symbol information table 106.
Below, the source file 10 based on the information of the examples of FIGS.
Source step in 3 “ADD REG1, RE
G2 "object code generation and syntax check processing will be described.

In step 401, the source file 103
More 1 source step is read and the syntax is decomposed.
The syntax decomposition is to recognize the delimiter of the character string and acquire the character strings of the command word, the first operand, and the second operand according to the description position. In this example, the command word is "AD
D ", the first operand is" REG1 ", and the second operand is" REG2 ".

In step 402, the instruction word acquired in step 401 is used as a key, and the instruction structure information table 10
7 is obtained and the array element number of the table is acquired. In the case of this example, the instruction configuration information table 1 of the instruction word “ADD”
The sequence number of 07 is "20".

Step 403 is the determination of the search result of step 402. In the case of this example, the instruction word "ADD"
Exists in the instruction configuration information table 107, the process proceeds to step 404. If the command word does not exist, an undefined command error occurs, and the error process of step 411 (error message output etc.) is executed to perform the process of the next source step (from step 401).

In step 404, an object code is generated according to the object code format indicated by the array element number in the instruction structure information table 107. In this example, the instruction word “ADD” is a 4-byte instruction and the instruction code “(1
0) ₁₆ "is stored in the range from the 0th byte to the 1st byte, and the generated object code is" (1000000
0) ₁₆ ”.

Steps 405 to 409 are processing of operands. By repeating these processes for the number of operands, it becomes possible to generate the object code and syntax check the operand of the assembly instruction word of one source step. The details will be described below.

In step 405, it is determined whether the processing for the operand information indicated by the array element number of the instruction configuration information table 107 has been completed or the processing for the number of operands of one source step in the source file 103 has been completed.
Some of the assembly instruction words have no operands, and some have one operand. These are expressed by the presence or absence of the description symbols “OP1, OP2” in the instruction configuration information file 102. In this example, the command word "AD
According to the operand information of the instruction structure information table 107, “D” is an instruction word with two operands, and since the number of operands of one source step in the source file 103 is also two, the following processing is repeated twice. Become.

In step 406, the operand obtained in step 401 is used as a key to search the symbol information table 106 and the array element number of the table is obtained.
In the case of this example, the array element number of the symbol information table 106 of the first operand “REG1” is “32”.

In step 407, it is judged whether or not the symbol retrieved in step 406 is a defined symbol. The defined symbols are symbols defined in the peripheral resource information file 101 and the source file 103. The undefined symbol indicates a symbol which is used without being defined (for example, there is no branch destination definition and it is used as an operand of an assembly instruction word). These can be determined by the attributes in the symbol information table 106. In the case of this example, since the first operand “REG1” is a defined symbol, the process proceeds to step 408. If it is an undefined symbol, a syntax error occurs and step 41
The error processing 1 (error message output, etc.) is executed, and the processing of the next source step (from step 401) is performed. Step 408 is the instruction configuration information table 10.
It is determined whether the operand attribute in 7 and the symbol attribute in the symbol information table 106 match. In the case of this example, the first operand “REG1” matches because the operand attribute in the instruction configuration information table 107 is “register” and the attribute in the symbol information table 106 is “register”, and the process proceeds to step 409. If they do not match, a syntax error occurs, and the error process of step 411 (error message output etc.) is executed to perform the process of the next source step (from step 401).

In step 409, the object code of the operand is generated according to the object code format indicated by the array element number of the instruction structure information table 107. In the case of this example, the conversion code of the first operand “REG1” is “(10) ₁₆ ” according to the symbol information table 106 and is stored in the range of 1 byte from the first byte, and the generated object code is “(1010000).
0) ₁₆ ”.

By repeating steps 405 to 409 as many times as the number of operands, the generation of the object code of the operand of the assembly instruction word and the syntax check are completed. In the case of this example, the completed object code is “(10102000) ₁₆ ”.

Step 410 includes steps 401 to 4
After the processing sequence of 09 is completed, the number of operands is checked for excess or deficiency. In the case of this example, the number of operands in the instruction configuration information table 107 is two, and the source file 103
Since the number of operands in the two is the same and the two match, the processing of the next source step (from step 401) is performed. If they do not match, a syntax error occurs, and the error process of step 411 (error message output etc.) is executed to perform the process of the next source step (from step 401).

As described above, from step 401 to step 411, the instruction configuration information table 107 and the symbol information table 10
By processing based on 6, it is possible to generate the object code of the assembly instruction word and check the syntax rule.

[0031]

As described above, according to the present invention, in the processing method of the conventional assembler, the processor-dependent information (peripheral resource information, instruction configuration information) is not incorporated in the assembler body but is processed separately. This has the effect of reducing the man-hours for changing the assembler when changing the specifications of the processor, and it is also possible to reduce the development man-hours by making slight changes to the assembler for other processors.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a relationship diagram of a peripheral resource information file and a symbol information table.

FIG. 3 is a relationship diagram of an instruction configuration information file and an instruction configuration information table.

FIG. 4 is a flowchart of object code generation and syntax check processing.

[Explanation of symbols]

101 ... Peripheral resource information file, 102 ... Instruction configuration information file, 103 ... Source file, 10
4 ... Assembler main body, 105 ... Processor information processing unit,
106 ... Symbol information table, 107 ... Instruction configuration information table, 108 ... Assembly language expansion processing unit, 1
09 ... File output unit, 110 ... Object file, 111 ... List file.

Claims (2)

[Claims] 1. A assembler for inputting a source program written in an assembly language which is a kind of computer language to generate an object code and outputting an object file and a list file. A file that defines information about peripheral resources specific to the processor (hereinafter referred to as "peripheral resource information"), a means for analyzing the file before converting the source program into an object code, and registering the table in a table, and a table based on the table information. An assembler object code generation processing method characterized in that it has means for converting to object code and has peripheral resource information depending on the processor externally. 2. In the assembler, information on object configuration and instruction syntax rules (hereinafter referred to as "instruction configuration information").
, A file that defines the file), a unit that analyzes the file before assembling and registers it in a table, and a unit that checks the syntax based on the table information and converts it into an object code. An assembler object code generation and syntax check processing method characterized by having it externally.