JPH08272679A - Industrial computer - Google Patents

Abstract

PURPOSE: To provide an industrial computer which effectively uses the internal memory of an IC for CPU. CONSTITUTION: An input/output board b0, which is provided with an internal RAM b05 and an external RAM b06 storing their own operation information and a VME bus controller b04 and is controlled based on control data inputted to the VME bus controller b04 through a VME bus 1, and a main CPU board (a) which is provided with a VME bus controller a4 communicating with the VME bus controller b04 and reads out operation information stored in the internal RAM b05 and the external RAM b06 to monitor and control the operation of the input/output board b0 are provided, and mapping registers b08 and b09 which assign the addresses of the internal RAM b05 and the external RAM b06 to the address space of the VME bus 1 are provided in the VME bus controller b04 correspondingly to the internal RAM b05 and the external RAM b06.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an industrial computer suitable for controlling equipment.

[0002]

2. Description of the Related Art An industrial computer used for controlling equipment has a plurality of input / output boards so that a plurality of equipment can be controlled simultaneously. Each of these input / output boards has a CPU (local CPU), and this local CPU directly controls an external device. Each I / O board is connected to a main CPU (central processing unit) board via a system bus such as a VME bus, and each local CPU is controlled by the main CPU mounted on the main CPU board. Are monitored and controlled.

Further, in such an industrial computer, a CSR (control status register) used by the main CPU board for monitoring the input / output board is part of the VMEbus address space managed by the VMEbus.
Is provided. The CSR is composed of a plurality of registers corresponding to respective uses, and a plurality of CSRs are provided corresponding to each input / output board. Also, one such CSR is the base address register.
This base address register is a register that points to the address of the memory that stores the operating state of the I / O board. The addresses set in the base address register are different from each other so that the main CPU board can access the operation state of each input / output board within the above-mentioned VMEbus address space so as not to overlap with each other. The value is set. The main CPU monitors and controls the operating state of each I / O board via this base address register.

[0004]

By the way, in recent years, CP
A highly integrated LSI is supplied as an LSI for U.
In such a CPU LSI, peripheral circuits of a conventional CPU LSI such as a memory circuit or an interrupt circuit are LS
I have taken it inside. That is, such a CPU
LSIs are highly integrated for the purpose of cost reduction and reduction of mounting area. Therefore, such a CPU
When the above-mentioned input / output board is configured by using the dedicated LSI, the cost of the board and the board size can be reduced.

In this case, however, such an L for CPU is used.
Since the capacity of the memory provided inside the SI is relatively small, all the data that must be stored in the input / output board cannot be stored in the internal memory of the CPU LSI. That is, in this case, it is necessary to provide a separate external memory circuit in the input / output board.

Further, when there are two memory circuits such as the internal memory of the CPU LSI and the external memory circuit in this way, the memory capacity of the external memory circuit can be freely set to some extent. After all, because of the complexity of using different circuits
No internal memory was used, and the I / O board was operated using only the external memory circuit. Therefore, the CPU
There is a problem that the internal memory of the application LSI is wasted without being effectively used. Further, in this case, since the internal memory of the CPU LSI is not used, it is necessary to increase the memory capacity of the external memory circuit, which causes a problem of cost increase.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide an industrial computer capable of effectively utilizing the internal memory of the CPU IC.

[0008]

In order to achieve the above-mentioned object, the present invention has a plurality of storage means for storing its own operation information and a first communication means, and is provided via a system bus. An input / output board controlled based on control data input to the communication means; and a second communication means for communicating with the first communication means via the system bus,
In an industrial computer having a main board for reading out the operation information stored in the storage means by the second communication means to monitor and control the operation of the input / output board, the address of the storage means is set to the system. A plurality of registers to be assigned to the address space of the bus are provided in the communication means in association with the storage means.

[0009]

According to the present invention, the address of each of the plurality of storage means is assigned to the address space of the system bus by the register corresponding to the storage means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a schematic configuration diagram of the industrial computer according to the present embodiment. As shown in the figure, the industrial computer A is composed of a main body A-1, a main CPU board a, and seven input / output boards b0 to b6. A plurality of connectors (not shown) for connecting the boards b0 to b6 to external devices are provided.

The main CPU board a and each of the input / output boards b0 to b6 are formed in a card board form which can be inserted into and removed from the main body A-1. Corresponding slots are provided respectively. A slot number is assigned in advance to each slot. For example, a slot number "# 0" is set to the slot in which the input / output board b0 is inserted. Further, slot numbers # 1 to # 6 are sequentially set in the slots in which the input / output boards b1 to b6 are inserted.

Further, the input / output board b0 displays a RUN lamp c0 indicating that this board is operating normally, a FAIL lamp d0 indicating that it is in an abnormal state, and an abnormal state in more detailed numerical values. A 7-segment LED (light emitting diode) e0 is provided, and the other input / output boards b1 to b6 are similarly configured.

Next, FIG. 3 is a block diagram showing a connection state of the above-mentioned boards. The main CPU board a and each of the input / output boards b0 to b6 are connected via the VME bus 1. This VMEbus 1 is an international standard system bus used in industrial computers and the like. The main CPU board a includes the main CPU a1 and RO
It is composed of Ma2 (read-only memory), RAMa3 (read / write memory), and VMEbus controller a4. Main CPUa1 is RO
Operates according to the program stored in Ma2, V
Each I / O board b0 through ME bus controller a4
The operation of b6 is monitored and controlled. RAMa3 is the main CPU
When a1 executes the program, it sets various flags or stores operation data.

The input / output board b0 is a local CPU b0.
1, ROMb02, RAMb03, and VMEbus controller b04. Local CPU b01
Is the main CPU via the VMEbus controller b04
Communicate with board a. That is, the input / output board b0
The VMEbus controller b04 sends the VMEbus controller a4 of the main CPU board a via the VMEbus1.
By communicating with the main C
It is monitored and controlled by the PU board a. Local CP
Ub01 is transferred from the main CPU board a to RAM
The device 0 is controlled on the basis of the control data stored in b03, and various data exchanged with the device 0 at this time are stored as control operation information at a specific address in the RAM b03. The other input / output boards b1 to b6 are also constructed exactly the same as the input / output board b0.

FIG. 4 is a block diagram showing the internal connection of the input / output board b0. In this figure, reference numeral b05 is an internal RAM provided in the local CPU b01, b06 is an external RAM provided individually in the input / output board b0, and b07 is a mutual connection of the local CPU b01, the external RAM b06, and the VMEbus controller b04. Internal bus (local bus) connected to, and b08 and b09 are internal RAMb
This is a mapping register that maps each address of 05 and external RAMb06 to the VMEbus address space.

The internal RAMb05 and the external RAMb06 are
Internal addresses corresponding to the internal bus b07 are set respectively, and the above-mentioned control operation information is stored, for example.
The local CPU b01 writes the data to the internal RAMb05 based on this internal address and the internal RAMbb.
The data is read from 05, and the data is written to the external RAM b06 and the data is read from the external RAM b06 via the internal bus b07 based on the internal address.

On the other hand, the mapping registers b08 and b09 provided in the VMEbus controller b04 map these internal addresses to the VMEbus address space managed by the VMEbus 1. That is, the mapping registers b08 and b09 have VME in the VMEbus address space corresponding to the internal RAMb05 and the external RAMb06.
ME address is stored. Main CPU board a
Accesses the VME addresses stored in the mapping registers b08 and b09, respectively, to read the control operation information stored in the internal RAMb05 and the external RAMb06. The RAMb03 described above is configured by an internal RAMb05, an external RAMb06, a memory provided in the VMEbus controller b04, and the like.

Next, FIG. 5 is an address map showing the structure of the CSR space. According to the specifications of the VME bus, a CSR space for the main CPU board to monitor and control the input / output board is provided in a predetermined address space (A24 space). This CSR space is 512
A maximum of 21 I / O boards with a capacity of kilobytes, that is, a maximum of 21 I / O boards can be controlled. Now, in this embodiment, the computer is composed of a total of seven input / output boards b0 to b6, and the CSR space corresponding to each input / output board b0 to b6 is the above-mentioned main body A-.
The CSR space C corresponding to the slot numbers # 0 to # 6 of 1
SR0 to CSR6.

Next, FIG. 6 is an address map showing details of the CSR space. For example, the CSR space CSR0 corresponding to the I / O board b0 is provided with a control register R01, a status register R02, a 7-segment register R03, an ID register R04, a correction register R05, and a base address register R06. Each of these registers is mapped to the illustrated address with a capacity of 2 bytes.

Each of these registers is provided in the memory in the VMEbus controller b04, and the main CPU board a monitors and controls the operation of the input / output board b by accessing these registers.
The other input / output boards b1 to b6 (the input / output boards b
The respective registers described above are similarly mapped to the respective CSR areas CSR1 to CSR6 provided corresponding to the slot numbers corresponding to 1 to b6.

The control register R01 has addresses FFFC to FFFE.
It is a register mapped to 2 bytes (hexadecimal display), and the main CPU board a writes control data for instructing initialization (reset) or self-diagnosis of the input / output board b0. Local CPU b01 is the main CPU
The board a performs processing such as initialization or self-diagnosis based on the control data written in the control register R01.

The status register R02 has addresses FFF8 to FFFA.
The main CPU board a is a register for writing control data instructing the input / output board b0 to display the self-diagnosis result. The local CPU b01 is
When the control data for instructing the display of the self-diagnosis result is written in the status register R02, the FAIL lamp d0 is turned on when it is determined that the diagnosis result is abnormal, and the RUN lamp c0 is turned on during normal operation (normal operation).

The 7-segment register R03 is an address
This register is mapped to FFF4 to FFF6, and is a register in which the main CPU board a writes control data instructing the input / output board b0 to display the content of the self-diagnosis result. When the control data for instructing the display of the content of the self-diagnosis result is written in the 7-segment register R03, the local CPU b01 displays the number in the 7-segment LEDe corresponding to the content of the abnormality.
Display at 0.

The ID register R04 has addresses FFF0 to FFF2.
Is a register for mapping the ID number of the input / output board b0 to the main CPU board a. When the ID register R04 is read, the local CPU b01 outputs the ID number set for itself to the main CPU board a.

The revision register R05 has addresses FFEC to FFEE.
Is a read register that maps the revision information of the input / output board b0 to the main CPU board a. When the revision register R05 is read from the local CPU b01, the revision information of the input / output board b0 is read by the main CPU b01.
Output to U board a.

The base address register R06 is mapped to the addresses FFE8 to FFEA, and the internal RAMb05 and the external RAMb in which the above-mentioned control operation information is stored.
The VME address when the internal address of 06 is mapped onto the VME bus address space is stored. That is, the internal addresses of the internal RAMb05 and the external RAMb06 are VMs set in the base address register R06.
Mapped to E address. Here, the area on the VMEbus address space to which the control operation information is mapped is referred to as a communication area. The main CPU board a uses this base address register R06
The operating state of the input / output board b0 is judged by accessing the communication area indicated by the address.

FIG. 7 is an address map showing the VMEbus address space. In this figure, the symbol M is a main memory to which the addresses of the ROMa2 and RAMa3 of the main CPU board a are mapped. Reference numerals CK0 to CK6 are communication areas, and base address registers R06 to R6 of the respective input / output boards b0 to b6.
Based on the respective VME addresses set in 66, the internal addresses corresponding to the control operation information are mapped in the respective input / output boards b0 to b6 so as not to overlap each other.

Next, in the above-mentioned industrial computer, when the power is turned on and the main CPU board a is activated, the main CPU a1 first initializes each of the input / output boards b0 to b6 according to the program stored in the ROMa2. That is, each RAMb in each I / O board b0 to b6
Reset the memory contents of 03 to b63. Then, in the VMEbus address space shown in FIG.
The communication areas CK0 to CK6 corresponding to b6 are mapped as follows.

First, the main CPU a1 confirms the capacity of the main memory M and maps the area occupied by the main memory M in the VME bus address space to, for example, VME addresses 0000 0000 to 1FFF 0000. This VM
By mapping the main memory M to the E address, the unused addresses in the VME bus address space are VME addresses 1FFF 0001 to FFFF FFFF. continue,
The main CPU a1 VM maps the communication area CK0 of the input / output board b0 corresponding to the slot number # 0 to the VME addresses 2000 0000 to 3FFF 0000 stored in the base address register R06 described above.
Instruct the E-bus controller b04.

At this time, the VMEbus controller b04
1, the VME address 2000 0000 stored in the mapping register b08 corresponds to the internal address where the control operation information is stored in the external RAM b06.
The VME address stored in the mapping register b08 is mapped to the internal address where the control operation information is stored in the internal RAM b05.
Map to 3000 0001 to 3FFF 0000. As a result, the control operation information stored in the internal RAM b05 and the external RA
The control operation information stored in Mb06 is mapped to the continuous address space of the communication area CK0.

Thereafter, similarly, each slot number # 1 to #
The communication areas CK1 to CK6 corresponding to the input / output boards b1 to b6 mounted on the No. 6 are respectively mapped to the addresses shown in the figure.

[0032]

As described above, according to the industrial computer of the present invention, the addresses of the plurality of storage means are allocated to the address space of the system bus by the registers corresponding to the storage means. The main board can read the information stored in each storage means. That is, it is possible to use all the storage means provided in the input / output board, and it is possible to effectively utilize the storage means in the input / output board.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a VMEbus address space and an internal address space in the present invention.

FIG. 2 is a perspective view showing the configuration of an industrial computer of the present invention.

FIG. 3 is a diagram showing a connection between a main CPU board and an input / output board in the present invention.

FIG. 4 is a diagram showing internal connections of an input / output board according to the present invention.

FIG. 5 is an address map showing an outline of a CSR area in the present invention.

FIG. 6 is an address map showing details of the CSR area in the present invention.

FIG. 7 is an address map of the VMEbus address space in the present invention.

[Explanation of symbols]

 A Industrial computer A-1 Main body a Main CPU board b0 to b6 I / O board a1 Main CPU a2, b02 to b62 ROM a3, b03 to b63 RAM a4, b04 to b64 VMEbus controller b05 Internal RAM b06 External RAM b08, b09 Mapping register 1 VMEbus R01 Control register R02 Status register R03 7-segment register R04 ID register R05 Revision register R06 Base address register M Main memory CK0 to CK6 Communication area CSR0 to CSR6 CSR area

Claims (1)

[Claims] 1. An input / output board which has a plurality of storage means for storing its own operation information and a first communication means and is controlled based on control data input to the communication means via a system bus. And second communication means for communicating with the first communication means via the system bus, and the operation information stored in the storage means is read by the second communication means to input / output the input / output data. In an industrial computer having a main board for monitoring and controlling the operation of the board, a plurality of registers for allocating the addresses of the storage means to the address space of the system bus are provided in the communication means in association with the storage means. An industrial computer that features.