JPH08274796A - Bus interface - Google Patents

Abstract

PURPOSE: To prevent adverse influence on the information transmitting function of a bus by the use of simple circuit constitution even if the supply of operating power is stopped to a signal processing circuit connected to the bus and to protect the said signal processing circuit against a bus-side voltage. CONSTITUTION: A signal on the bus 1 is inputted to the reception terminal 33 of the signal processing circuit 3 through voltage divider resistors R2 and R3 of an interface 5 for reception. A signal outputted from the transmission terminal 3 of the signal processing circuit 3 is sent out to the bus 1 through a transistor(TR) 61. When the supply of a source voltage VD2 to the signal processing circuit 3 is stopped, the side of the bus 1 is not fixed at a low level because of an R2 having a higher resistance value than a resistor R1 and the tR 61 which is OFF and when a voltage VD1 is higher than the VD2, a voltage below the voltage VD3 is applied to the reception terminal 33 by the voltage divider resistor R2 and R3 and the voltage VD1 is not applied directly to the transmission terminal 34 because of the TR1, so the signal processing circuit 3 is protected against the high voltage VD1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface for connecting a signal transmitting / receiving circuit for receiving a control signal on a bus or sending an information signal on the bus to the bus.

[0002]

2. Description of the Related Art In recent video tape recorders and the like, as shown in FIG. 4, a signal processing circuit 3 (actually, a plurality of signal processing circuits 3 is provided on a bus 1 output from a microcomputer 2 which controls the entire apparatus. In the figure, only one is shown as a representative).

A voltage VD1 is applied to the bus 1 via a pull-up resistor R1 and is maintained at a high level. When the transmission unit connected to the bus 1 provided in the microcomputer 2 becomes high impedance or low impedance, a high-level control signal and a low-level control signal are placed on the bus 1 and the signal processing circuit 3 is supplied. Send.

The receiving circuit 32 receives the control signal on the bus 1 via a protection resistor R2 (interface), and processes a video signal or the like input from the signal line 4 based on the received control signal. At this time, the transmission circuit 31 of the signal processing circuit 3 becomes high impedance or low impedance, so that the information signal indicating the state of the input video signal or the like is placed on the bus 1 via the protection resistor R2, It is transmitted to the microcomputer 2.

By the way, the signal processing circuit 3 operates at the voltage VD2, but when the supply of the voltage VD2 is stopped,
Either or both of the transmission circuit 31 and the reception circuit 32 of the signal processing circuit 3 are fixed to low impedance, and the bus 1 is fixed to low level.
Will not be able to convey information.

Therefore, among the plurality of devices connected to the bus 1, when the power supply to the signal processing circuit 3 has to be turned off, a circuit for electrically disconnecting the signal processing circuit 3 from the bus 1 is required. As a result, the bus line configuration becomes complicated and the circuit scale becomes large.

Further, the power source voltage VD1 pulling up the bus 1 is the power source voltage V operating the signal processing circuit 3.
If it is higher than D2, the voltage applied to the transmission / reception circuits 31, 32 of the signal processing circuit 3 must be made lower than the voltage value of VD2 to protect the signal processing circuit 3. However, since the value of the protection resistor R2 is selected to be much smaller than the value of the pull-up resistor R1, the protection circuit for protecting the signal processing circuit 3 is configured by a simple circuit such as resistance division. However, there is a drawback that the circuit scale of the protection circuit becomes large and the cost of the device increases.

The protection resistor R2 is inserted to suppress static electricity or noise flowing from the bus 1 into the signal processing circuit 3 to protect the signal processing circuit 3, but its value is determined by the transmission circuit 31. The value should be sufficiently small with respect to the resistor R1 so that 1 can have a low impedance.

[0009]

In the conventional bus interface for connecting the bus and the signal processing circuit as described above,
When the power supply to the signal processing circuit is stopped, the backflow of the current from the bus to the signal processing circuit causes the bus to be fixed at a low level, and the information transmission to other signal processing circuits using this bus is prevented. Since it becomes impossible to do so, a circuit for electrically disconnecting the signal processing circuit 3 from the bus 1 is required, and there is a drawback that the bus line configuration becomes complicated and the circuit scale becomes large accordingly.

Also, the voltage VD pulling up the bus 1
1 is a power supply voltage VD2 for operating the signal processing circuit 3
If it is higher than that, the voltage applied to the signal processing circuit 3 from the bus must be made lower than the power supply voltage VD2 to protect the signal processing circuit 3. However, in the conventional bus interface, a simple circuit such as resistance division is used. It is impossible to construct a protection circuit for protecting the above-mentioned signal processing circuit only by adding it, and there is a drawback that the circuit scale of the protection circuit becomes large and the cost of the device increases.

Therefore, in view of the above circumstances, the present invention is designed so that even if the supply of operating power to the circuit connected to the bus is stopped,
An object of the present invention is to provide a bus interface having a simple configuration that can protect the circuit from the voltage on the bus side when the voltage on the bus side is high without adversely affecting the information transfer function of the bus.

[0012]

According to a first aspect of the present invention, there is provided a signal transmitting / receiving circuit in a system comprising a plurality of signal transmitting / receiving circuits connected to a bus for transmitting a signal when a voltage level becomes a high level or a low level. In a bus interface for connecting a signal on the bus to the signal transmission / reception circuit, and a switch circuit for switching according to a transmission signal output from the signal transmission / reception circuit. And a transmission interface for transmitting the transmission signal to the bus through the switch circuit.

According to a second aspect of the present invention, the high-impedance circuit comprises a resistance voltage dividing circuit including a resistor having a resistance value sufficiently higher than a resistance to which a voltage pulling up the bus is applied. Have

According to a third aspect of the present invention, the switch circuit has a configuration in which the transmission signal is input to a base and a collector is a transistor connected to the bus.

[0015]

In the bus interface of the present invention, the receiving interface inputs the signal on the bus to the signal transmitting / receiving circuit through the high impedance circuit. The switch circuit of the transmission interface sends the transmission signal to the bus by switching according to the transmission signal output from the signal transmission / reception circuit.

According to another aspect of the bus interface of the present invention, the high-impedance resistance voltage dividing circuit divides the signal on the bus and inputs it to the signal transmitting / receiving circuit.

In the bus interface of the invention of claim 3, when the transmission signal is inputted to the base, the transistor sends the transmission signal from the collector onto the bus.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the bus interface of the present invention. Reference numeral 1 is a bus for transmitting control signals and information signals, 2 is a microcomputer for totally controlling operations of various circuits connected to the bus 1, and 3 is a bus for transmitting information signals and control signals via the bus 1. A signal processing circuit for receiving, 4 is a signal line through which a signal processed by the signal processing circuit 3 or a signal processed by the signal processing circuit 3 is transmitted,
Reference numeral 5 is a reception interface for connecting the bus 1 and the reception terminal 33 of the signal processing circuit 3, 6 is a transmission interface for connecting the bus 1 and the transmission terminal 34 of the signal processing circuit 3, and 31 is the signal processing circuit 3 on the bus 1. Is a transmission circuit for transmitting a signal to the receiver, and 32 is a reception circuit for the signal processing circuit 3 to receive a signal on the bus 1. However, the receiving interface 5 and the transmitting interface 6 form a bus interface, and the signal processing circuit 3 is connected to the bus 1.

Next, the operation of this embodiment will be described. The voltage VD1 is applied to the bus 1 via the pull-up resistor R1 and is maintained at a high level. When a transmitting / receiving unit (not shown) connected to the bus 1 provided in the microcomputer 2 becomes high impedance or low impedance, a high level control signal and a low level control signal are placed on the bus 1. For example, a control signal is transmitted to the signal processing circuit 3.

The receiving circuit 32 of the signal processing circuit 3 receives the control signal on the bus 1 via the receiving interface 5, and processes the video signal or the like input from the signal line 4 based on the received control signal. To do. At this time, the transmission circuit 31 of the signal processing circuit 3 becomes high impedance or low impedance, so that the information signal indicating the state of the input video signal is put on the bus 1 via the transmission interface 6. , To the microcomputer 2.
The transmitting / receiving unit of the microcomputer 2 receives the information signal on the bus 1.

Here, since the bus interface of this example is divided into the receiving interface 5 and the transmitting interface 6, the receiving interface 5 has the receiving circuit 32.
And the transmission interface 6 can be designed according to the characteristics of the transmission circuit 31.

Therefore, the receiving interface 5 is the bus 1
Since it is not necessary to pull in to low impedance, the function can be achieved even in high impedance. On the other hand, since the transmission interface 6 does not need to capture a signal on the bus 1, that is, a voltage change, there is no problem even if the voltage on the bus 1 is not directly applied to the transmission terminal 34.

Therefore, the receiving interface 5 of this example is composed of a resistance dividing circuit formed by resistors R2 and R3 as shown in FIG. 2, and the resistance value of the resistor R2 is different from that of the pull-up resistor R1. Can be set higher. As a result, the signal on the bus 1 is divided by the resistors R2 and R3 and input to the receiving terminal 33.

Here, the power supply voltage VD to the signal processing circuit 3
When the supply of 2 is stopped, the impedance of the receiving interface 5 is kept relatively high by the resistor R2, so that the backflow of current from the bus 1 to the signal processing circuit 3 does not occur and the bus 1 goes low. You will not be locked into a level.

The voltage VD pulling up the bus 1
1 is a power supply voltage VD2 for operating the signal processing circuit 3
If higher than R, the resistance R of the receiving interface 5
2 and the value of the resistor R3 while keeping the value of the resistor R2 high,
If properly selected, the voltage VD1 is divided by the voltage dividing circuit of the resistors R2 and R3 to VD2 or less and is input to the receiving terminal 33. Therefore, the voltage applied to the receiving circuit 32 is set to the voltage VD2 or less. The receiving circuit 32 can be protected.

When the voltage VD1 is not higher than the voltage VD2, it is not necessary to form the receiving interface 5 with a voltage dividing circuit, and only the resistor R2 having a high resistance value may be used.

Next, the transmission interface 6 of this example is N
It is composed of a PN type transistor 61. When sending,
The signal output from the transmission terminal 34 of the signal processing circuit 3 is input to the base of the transistor 61 via the resistor R4,
The signal is output from the collector side of the transistor 61 onto the bus 1. At this time, since the polarity of the transmission signal is inverted by the transistor 61, it is assumed that the signal output from the transmission terminal 34 has the polarity inverted.

Here, the power supply voltage VD to the signal processing circuit 3
When the supply of 2 is stopped, the base of the transistor 61 is fixed to the low level, and the transistor 61 is turned off. As a result, the collector of the transistor 61,
A high impedance is maintained between the emitters, and the bus 1 is never fixed at a low level.

Further, since the voltage VD1 on the bus 1 is applied to the collector of the transistor 61 and not directly to the transmission terminal 34, the voltage VD1 pulling up the bus 1 is the power supply for operating the signal processing circuit 3. Even when the voltage is higher than the voltage VD2, the voltage VD1 is not applied to the transmission terminal 34, and there is no problem.

According to this embodiment, since the bus interface is divided into the transmitting interface and the receiving interface, the receiving interface 5 can be configured by a simple high impedance circuit, and the power supply voltage VD2 is supplied to the signal processing circuit 3. It is possible to prevent the bus 1 from being fixed at a low level when the signal is stopped, and prevent the information transmission function of the bus 1 from being adversely affected. Further, when the voltage VD1 pulling up the bus 1 is higher than the power supply voltage VD2 for operating the signal processing circuit 3, the receiving interface 5 is operated by a simple voltage dividing circuit while maintaining high impedance. With this configuration, the voltage applied to the receiving circuit 32 can be reduced to the voltage VD2 or less by this voltage dividing circuit, and the signal processing circuit 3 can be protected.

Further, the transmission interface 6 can be constituted by a simple active switch circuit (transistor 61), and when the supply of the power supply voltage VD2 to the signal processing circuit 3 is stopped, the bus 1 and the transmission terminal 34 are connected to the switch circuit. By shutting off at 1, it is possible to prevent the bus 1 from being fixed at a low level and prevent the information transmission function of the bus 1 from being adversely affected. Further, even when the voltage VD1 pulling up the bus 1 is higher than the power supply voltage VD2 for operating the signal processing circuit 3, the voltage VD1 is not directly applied to the transmission terminal 34 by the switch circuit, so that the signal processing is performed. The circuit 3 can be protected.

Moreover, since the receiving and transmitting interfaces 5 and 6 are composed of the simple voltage dividing circuit and active switch circuit as described above, the circuit scale is not increased or the cost of the device is not increased. The above effects can be obtained.

By forming the transmission interface 6 inside the signal processing circuit 3 as shown in FIG. 3 and forming an IC, the number of external parts such as transistors can be reduced, and the device can be miniaturized. At the same time, its assembly can be facilitated.

[0034]

As described above, according to the bus interface of the present invention, the information transmission function of the bus is maintained even if the supply of operating power to the signal processing circuit connected to the bus is stopped by the simple circuit configuration. It is possible to prevent an adverse effect and to protect the signal processing circuit from the voltage on the bus side when the voltage on the bus side is high.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus interface of the present invention.

2 is a circuit diagram showing a detailed example of a receiving / transmitting interface shown in FIG.

FIG. 3 is a circuit diagram showing an application example of the bus interface shown in FIG.

FIG. 4 is a block diagram showing an example of a conventional bus interface.

[Explanation of symbols]

1 ... Bus 2 ... Microcomputer 3 ... Signal processing circuit 4 ... Signal line 5 ... Reception interface 6 ... Transmission interface 31 ... Transmission circuit 32 ... Reception circuit 33 ... Reception terminal 34 ... Transmission terminal 61 ... Transistors R1 to R4 ... Resistance

Claims (3)

[Claims] 1. A bus interface for connecting the signal transmission / reception circuit to the bus in a system comprising a plurality of signal transmission / reception circuits connected to a bus for transmitting a signal when a voltage level becomes a high level or a low level. The reception interface including a high impedance circuit for inputting a signal on the bus to the signal transmission / reception circuit, and a switch circuit for switching according to a transmission signal output from the signal transmission / reception circuit, and the transmission signal through the switch circuit And a transmission interface for transmitting the data on the bus. 2. The high-impedance circuit comprises a resistance voltage dividing circuit having a resistance having a resistance value sufficiently higher than a resistance applied with a voltage pulling up the bus. 1. The bus interface described in 1. 3. The bus interface according to claim 1, wherein the switch circuit is a transistor whose base is supplied with the transmission signal and whose collector is connected to the bus.